JPH02188966A - Mos semiconductor device - Google Patents

Abstract

PURPOSE:To realize a circuit which is small in occupying area and large in resistance against a hot carrier effect and can reduce the consumption of the standby current and make high-speed switching operations because of a reduction in signal delay by using a MOS transistor having a longitudinal structure in which side walls of a plurality of columnar semiconductor layers are used is channels, and so on. CONSTITUTION:This MOS semiconductor device is constituted of a semiconductor substrate 1, a plurality of columnar semiconductor layers 5 and 6 formed and arranged on the substrate 1 in such a state that they are separated from each other by prescribed intervals by means of grooves 4, gate insulating films 7 respectively formed on outer peripheral surfaces of the layers 5 and 6, gate electrodes 8 continuously installed along the grooves 4 so as to surround the layers 5 and 6 on which the insulating films 7 are formed, diffused layers 9-12 which are respectively formed on tops of the layers 5 and 6 and bottom sections of the grooves surrounding the layers 5 and 6 and become sources and drains, first main electrodes 14 and 15 commonly connected to the diffused layers 9 and 11 on the tops of the layers 5 and 6, and second main electrodes 16 and 17 connected to the diffused layers 10 and 12 in the bottom sections of the grooves 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention (Industrial Application Field) The present invention relates to a MOS type semiconductor device, and in particular to a MOS transistor structure that makes it possible to effectively utilize the substrate area and an integrated circuit using the same. Regarding circuits.

(Prior Art) Semiconductor integrated circuits, especially integrated circuits using MOS transistors, are becoming increasingly highly integrated. With this increase in integration, the MOS transistors used therein are being miniaturized to the submicron region. The basic circuit of a digital circuit is an inverter circuit, but as the MOS transistors that make up this inverter circuit become smaller, various problems arise. First, as the gate size of a MOS transistor becomes smaller, bunch-through occurs between the source and drain due to the so-called short channel effect, making it difficult to suppress leakage current. As a result, the standby current of the inverter circuit increases. Second, M
The internal electric field of the OS transistor becomes high, and the hot carrier effect causes variations in the transistor's threshold value and mutual conductance, resulting in deterioration of transistor characteristics and deterioration of circuit characteristics (operating speed, operating margin, etc.). Third, even if the gate length becomes shorter due to miniaturization, the gate width must be greater than a certain level in order to secure the necessary amount of current.

As a result, it is difficult to sufficiently reduce the area occupied by the inverter circuit. For example, dynamic RAM (DRAM)
), although memory cell miniaturization technology has progressed at a remarkable pace, there are many parts in which the gate width cannot be made small in order to secure the necessary amount of current in one peripheral circuit, and this makes it difficult to miniaturize the entire DRAM chip. It's hindering.

In addition, when the gate electrode is formed with a polycrystalline silicon film,
A CR time constant composed of this polycrystalline silicon film resistor and gate capacitor causes a delay in signal propagation to the gate electrode. Due to the miniaturization of devices, the thickness of the gate oxide film is reduced and the switching speed is improved, so that the signal delay at the gate electrode now occupies most of the switching time of the inverter. Furthermore, the junction capacitance of the source and drain is also increasing due to the increase in substrate concentration with miniaturization, which causes a decrease in the switching speed.

(Problem to be solved by the invention) As mentioned above, with conventional MOS integrated circuit technology.

It is difficult to suppress leakage current in the inverter circuit.

Reliability decreases due to hot carrier effect.

There are also problems in that it is difficult to reduce the area occupied by the circuit due to the need to secure the necessary amount of current, and the delay at the gate electrode is large, making it impossible to increase the gate width. Similar problems exist not only in inverter circuits but also in flip-flop circuits.

An object of the present invention is to provide a MOS type semiconductor device that solves these problems.

[Structure of the Invention] (Means for Solving the Problems) A MOS transistor according to the present invention is constructed using a plurality of columnar semiconductor layers arranged and separated by grooves on a semiconductor substrate. A gate insulating film is formed on the side surfaces of the plurality of columnar semiconductor layers, and a gate electrode is continuously provided in the groove so as to surround these columnar semiconductor layers.

Source and drain diffusion layers are formed on the top surface of each columnar semiconductor layer and at the bottom of the groove, respectively, a first main electrode is commonly connected to the top diffusion layer of the plurality of columnar semiconductor layers, and a second main electrode is formed at the bottom of the groove. Connected to the diffusion layer.

Preferably, the pattern dimensions of the plurality of columnar semiconductor layers constituting one MOS transistor are approximately the minimum processing dimension, and the distance between the columnar semiconductor layers is approximately 2 to 2 of the minimum processing dimension.
It should be about 3 times or less.

In the present invention, the basic circuits of integrated circuits such as inverters and flip-flops are constructed using the above-described MOS transistors.

(Function) In the structure of the present invention, the subthreshold characteristic of the MOS transistor is steep, and the subthreshold swing is extremely small. This is due to the strong controllability of the gate over the channel, as will be explained in detail later.

Therefore, leakage current from the inverter circuit, etc. is effectively suppressed.

In addition, the side walls of the columnar semiconductor layer become channel regions.

Unlike a normal planar MOS transistor, there is no part where the channel region contacts the field region.

Therefore, the high electric field at the edge of the field does not affect the channel region, and the hot carrier effect is suppressed.

Further, the channel length can be increased by increasing the height of the columnar semiconductor layer, that is, the depth of the groove, without increasing the occupied area, which is also effective in suppressing the hot carrier effect. By suppressing this hot carrier effect, highly reliable inverter circuits and flip-flop circuits can be obtained.

Furthermore, since the channel region is provided to surround the plurality of columnar semiconductor layers, a large gate width can be realized with a small chip occupation area.

This is especially effective in reducing the occupied area in parts that require a certain amount of current. Furthermore, if the pattern size of one columnar semiconductor layer is, for example, a small rectangle with the minimum processing size (in reality, it will have a round shape due to rounding during processing), it will easily extend from the drain layer at the bottom of the groove during operation. A state is obtained in which the depletion layer electrically isolates the columnar semiconductor layer region from the semiconductor layer region below it, or a state in which the interior of the columnar semiconductor layer is depleted due to the depletion layer extending from the side surface.

This also leads to an improvement in subthreshold silt characteristics, and also makes it possible to obtain characteristics with extremely low substrate bias dependence.

In addition, since the gate width utilization rate per unit area of the substrate is high, when compared with the same gate width, it is
The junction area of the source and drain can be made extremely small compared to a transistor. This improves the operating speed.

Since the gate electrode is arranged so as to surround the plurality of columnar semiconductor layers, the signal delay at the gate electrode is also reduced, which also contributes to improving the operating speed.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIGS. 1(a) and 1(b) are a plan view and an equivalent circuit diagram of a CMOS inverter circuit according to an embodiment. Figure 2 (a), (b)
), (C) and (d) are respectively A in Fig. 1(a).
-A'B-B'c-c' and DD' cross-sectional views.

An n-type well 2 and an n-type well 3 are formed in a silicon substrate 1, and a plurality of columnar silicon layers 5 and 6 that are surrounded by a groove 4 and project like an island are arranged in each well region. MOS by columnar silicon layer 5 arranged in 2 rows x 4 columns
A transistor Qp is formed, and an n-channel MOS transistor QN is formed by columnar silicon layers 6 arranged in two rows and two columns.

MOS transistors QP and QN are connected to each columnar silicon layer 5.
, 6 as a channel region, and has a vertical structure. That is, an element isolation oxide film is formed in the element isolation region within the trench 4, a gate oxide film 7 is formed on the outer peripheral surface of the silicon layers 5 and 6, and a gate electrode 8 is formed in the trench 4 so as to surround this outer periphery. embedded and arranged continuously.

This gate electrode 8 is formed by depositing a p-type or n-type polycrystalline silicon film, for example, and etching it on the side surfaces of the columnar silicon layers 5 and 6 by a resist process and anisotropic etching such as reactive ion etching.

This can be achieved by leaving it in a flat area that becomes the joining area of the gate electrodes of both transistors. After forming this gate electrode 8, p
A plurality of columnar silicon layers 5 are formed by ion implantation of type impurities.
Source diffusion layer 9 on each top surface and drain diffusion layer 1 on the bottom of each groove.
0 is formed, and similarly by ion implantation of n-type impurities, n
Source and drain layers 11 and 12 on the channel side are formed. Note that in the groove regions between each of the plurality of columnar silicon layers 5 and between each of the plurality of columnar silicon layers 6, drain diffusion layers 10 are formed in advance, respectively, before forming the gate electrode.
．． 12 is formed. The substrate on which the elements have been formed is covered with a CVD oxide film 13, contact holes are opened in this, and necessary terminal wiring, that is, VCC wiring 14. Vss wiring,
Input terminal (V in) wiring 16. Output terminal (Vout)
A wiring 17 is formed.

In this example, the device parameters are set such that when the channel of each transistor is inverted during the operation of the inverter circuit, each columnar silicon layer region is electrically isolated from the regions below it by a depletion layer extending from the drain layer. is set. Particularly preferably, the pattern size of one columnar silicon layer is set to about the minimum processing size. Specifically, FIG. 3 shows the state of one silicon layer on the n-channel MOS transistor Qp side.

When the depletion layers 19 extending from the drain 12 formed at the bottom of the trench come into contact with each other, the columnar silicon layer 6 is separated from the substrate region below and becomes a floating state. For example, in order to satisfy such conditions, the impurity concentration of the p-type well 3 should be 3 x 10''
/cm3. The width of the columnar silicon layer 3 may be 1 μm, and the thickness of the gate oxide film may be 120 μm. Similar conditions are satisfied on the n-channel side as well.

The advantages of the inverter circuit according to this embodiment will be specifically clarified while comparing with the conventional structure. In the structure of this embodiment, the channel length of the MOS transistor is approximately the depth of the trench 4. The channel width required now is p-channel MO
38.4μm with S transistor Qp, n-channel MOS
The thickness of the transistor is 19.2 μm. Columnar silicon layer 5
If one side of the rectangular planes of and 6 is 1 μm, then 1 is the number of columnar silicon layers 5 and 6 of n-channel MOS transistor Qp and n-channel MOS transistor QN.
The desired channel width can be obtained by setting the number of channels to 8 and 4, respectively, as shown in Figure (a). At this time, the area occupied by the pattern in Figure 1(a) is approximately +5.4
XL2.3mH, 4μm2. For comparison,
FIG. 23 shows a pattern when a CMOS inverter circuit having a conventional planar structure and a similar current driving ability is constructed. Channel length is 0.5 for both p channel and n channel
μm, and the channel width is 38.4 μm on the p-channel side.
The n-channel side is 19.2 μm. At this time, the area occupied by the inverter circuit is approximately a xeo, e-181,
It becomes 8Bm2.

As is clear from the above comparison results, according to this embodiment, the area occupied by the five circuits can be significantly reduced. In a portion where the required amount of current is small, that is, in a portion where the channel width may be small, the contact hole area occupies a large proportion of the circuit occupation area. The area of this contact hole is the same between the present invention and the conventional structure. Therefore, the effect of the present invention in reducing the occupied area is greatly exhibited.

This is a circuit portion with a large channel width. In this sense, the present invention can be applied to peripheral circuits such as DRAMs to obtain great effects. In DRAM.

Technology to increase integration by introducing a trenched capacitor structure into memory cells is promising in the future, but if trenches are dug in the inverter part of one peripheral circuit at the same time as trenching in the memory cell area, it will be possible to improve the process efficiency. It's advantageous.

FIGS. 19(a) and 19(b) show a conventional planar structure p-channel MOS transistor and an example p-channel MOS transistor, respectively.
This shows the subthreshold characteristics of the transistor.

Channel width/channel length are both W/L = 8
．． Ournlo, 8 tt m.

The relationship between channel width W and channel length in this embodiment is clearly shown in FIG. 18. The gate oxide film is also 200
The measurement conditions are drain voltage Vd - 0.05V, and substrate bias Vsub -0, 2, 4, 6 [V].
and changed it. The transistor of this embodiment clearly has a steeper subthreshold characteristic than the conventional structure. Also, the swing S (-dVg /d (log
Id)) is 98mV/de in the conventional structure.
cade, whereas in this example, 72m
Very small V/decade. This shows that in this example, the controllability of the gate over the channel is strong. In particular, when the dimensions of the unit silicon layer are small, the silicon layer is easily completely depleted when a gate voltage is applied, and the change in channel potential with respect to the gate voltage becomes large, so that this effect becomes noticeable. Because of this subthreshold characteristic, this embodiment has the advantage that the standby current of the inverter circuit can be suppressed. As is clear from the comparison of FIGS. 19(a) and 19(b), in this embodiment, the substrate bias V in the region where the drain current rises, that is, the region where channel inversion occurs.
There is no variation depending on the sub. This is because, as explained in FIG. 3, in this embodiment, during channel inversion, the transistor portion is substantially electrically isolated from the substrate region below it by the depletion layer from the drain layer. As a result, the circuit of this embodiment exhibits strong resistance to substrate noise.

FIGS. 20(a) and 20(b) show the mutual conductance deterioration amount ΔGm/Gmo and the drain current deterioration amount ΔI ds/ when hot carrier effect stress is applied to the n-channel MO8 transistor in the inverter circuit of this example. The stress time dependence of I dso is shown in comparison with that of an n-channel MOS transistor with a conventional structure. From this data, it can be seen that in the structure of this example, the amount of deterioration in characteristics is small and reliability is improved. An inverter circuit using such highly reliable transistors is advantageous in terms of operating speed and operating margin.

FIGS. 22(a) and 22(b) compare and show the static characteristics of transistors with a conventional structure and a structure of the present invention. Channel width W and channel length are W/L-4.0μm10.8
pm, the gate oxide film thickness is Tox -200, and the substrate bias voltage is Vsub=OV.As shown in FIG. 21, in the conventional structure, this is formed with an occupied area of 5×6-30 μm2, and in the present invention, it is formed with an occupied area of 5×2. 4-12μm2
is formed. As described above, even if the transistor area of the present invention is 1/2 or less, the same drain current as that of the conventional structure can be obtained, and the device has high driving ability. Therefore, according to the embodiments of the present invention, it is possible to increase the degree of integration of various integrated circuits.

In the embodiment described above, the gate electrodes 8 of the n-channel MO8 transistor and the p-channel MOS transistor are continuously formed in common, but these may be made different depending on how the channels are configured. The pattern of the embodiment in that case is shown in FIG. 4 in correspondence with FIG. 1(a). Gate electrode 81 on the p-channel side and gate electrode 8 on the n-channel side
2 are formed separately, and these are commonly connected by an input wiring 16. This will increase the area slightly.

It becomes possible to optimize the characteristics of each transistor.

The present invention can be similarly applied to inverter circuits other than CMOS inverters. Other such embodiments will now be described. In addition, in the drawings below, Figures 1 and 2
Portions corresponding to those in the figures are given the same reference numerals and detailed explanations will be omitted.

FIGS. 5(a) and 5(b) are a plan view showing an embodiment of an E/R type inverter circuit and its equivalent circuit.

Figures 6(a) and (b) are A- in Figure 5(a), respectively.
A', BB' sectional view. A plurality of (two in the figure) columnar silicon layers 6 are formed in the p-type silicon layer 3 (which may be a well or the substrate itself) by grooves 4 as in the previous embodiment, and the columnar silicon layers 6 are covered with the previous layer. As in the example, n
A channel and E type MOS transistor QN are formed.

Adjacent to this transistor, a resistor 20 made of, for example, a polycrystalline silicon film is formed as a load element R.

According to this embodiment, the occupied area can be further reduced as is clear from the comparison with FIG.

FIGS. 7(a) and 7(b) are a plan view showing an embodiment of an E/D type inverter and its equivalent circuit. Figure 8(a),(b)
) are respectively AA'B-B' cross-sectional views of FIG. 7(a). In this embodiment, each p-type silicon layer 3 has two columnar silicon layers 6. , 62 for the driver, respectively, in the same manner as in the previous embodiment.
A live MOS transistor QNE and a load n-channel, D-type MOS transistor QND are formed. In this case, since the MOS transistor on the load side is of the D type, the n-type layer 21 is formed on the side wall of the columnar silicon layer 62.
A process of forming is necessary.

FIGS. 9(a) and 9(b) are a plan view of an embodiment of an E/E type inverter circuit and its equivalent circuit. Figure 10(a), (
b) is a sectional view taken along line A-A'B-B' in FIG. 9(a). This embodiment is similar to the previous embodiment except that both the driver and the load are E-type n-channel MOS transistors QNE11QNE2, and the gate on the load side is connected to the VCC wiring 14.

FIGS. 11(a) and 11(b) are a plan view of an embodiment of a dynamic inverter circuit and its equivalent circuit. Figures 12 (, a) and (b) are A-A in Figure 11 (a), respectively.
', BB' sectional view. This embodiment has the exception that an independent terminal wiring 22 is provided for the gate terminal on the load side so that the inverted and amplified signal φB of the input terminal V1n is input thereto.

This is basically the same as the previous embodiment.

E/R type inverter, E/D type inverter, E/
The E type inverter and the dynamic type inverter are composed of only n-channel MO8 transistors and do not require a well isolation region, which simplifies the process and reduces the occupied area. A similar configuration can be constructed using only p-channel MOS transistors.

In the above description, only the case where the gate electrode completely surrounds the outer periphery of the columnar semiconductor layer is shown, but the present invention is also effective when the gate electrode does not constitute a complete closed circuit.

In the above, a MOS constructed using multiple silicon layers is described.
Although an embodiment in which transistors are applied to an inverter circuit has been described, the present invention can be similarly applied to other circuits. For example, a flip-flop is a basic circuit of various integrated circuits. Next, an embodiment in which the present invention is applied to a flip-flop circuit will be described.

FIGS. 13(a) and 13(b) are plan views of an embodiment in which the present invention is applied to a DRAM bit line sense amplifier, and its A-A'
FIG. FIG. 14 shows its equivalent circuit.

FIGS. 13(a) and 13(b) show two n-channel MOS transistors Q1. This is an NMOS sense amplifier section composed of a flip-flop consisting of Q2.

A p-type well 32 is formed in a silicon substrate 31.
A plurality of columnar silicon layers 34 (34, 342, . . . ) protruding like islands are formed in the mold well 32 surrounded by the groove 33. MOS)-transistor Ql has two silicon layers 3431. Using 3432,
The other MOS transistor Q2 is constructed using the other two silicon layers 34□1 and 34□2. That is, two silicon layers 342°3 each.
A gate insulating film 35 is formed on the outer peripheral surface of 43, and a gate electrode 36 made of a polycrystalline silicon film is embedded in the groove so as to surround this outer peripheral surface. silicon layer 342
1 342 and the groove 33 are formed with n medium-sized diffusion layers 37 and 38 that will serve as a drain and a source. The paired bit lines 391 and 392 are arranged by polycrystalline silicon films in contact with the drains of the MOS transistors Q□lQ2, that is, the n medium type diffusion layers 37 on the upper surfaces of the silicon layers 342 and 343, respectively. The gate electrode 36 of the MOS transistor Q1 is taken out to the top of the silicon layer 344 diagonally below the right side in the layout shown in FIG. 13(a).
Bit line 392 is now in contact with this gate electrode 36.

The gate electrode 36 of the MOS transistor Q2 is located on the silicon layer 341 located diagonally upward to the left in the layout shown in FIG. 13(a).
It is taken out to the top, and the bit line 391 is brought into contact with this gate electrode 36 here. That is, the columnar silicon layer 3
41 and 344 are not provided to form a MOS transistor, but are provided as pedestals to ensure bit line contact when connecting the bit line to the gate electrode. These silicon layers 341°34
This is because by taking out the gate electrode on top of the gate electrode 4, the drain layer and the gate electrode contact portion become substantially on the same plane, and the depth of the contact hole of the bit line can be made uniform. Groove 3
The source diffusion layer 38 formed at the bottom of 3 is a common source ψ
This is a node, and the Al wiring 40 is in contact with this node. Although this common source node is not shown in FIG. 13, it is connected to the ground potential VSS via the activation MO5 transistor Q3, as shown in the equivalent circuit of FIG.

Although not shown in the figure, a PMOS sense amplifier using a p-channel MOS transistor is formed along the same bit line with a similar structure and layout.

As explained in the previous embodiment of the inverter circuit, the bit line sense amplifier according to this embodiment also occupies a much smaller chip area due to the gate width than when a planar MOS transistor is used. Furthermore, the subthreshold characteristic of the MOS transistor is steep, the signal delay at the gate electrode is small, and high-speed operation is possible.

Further, in this embodiment, during operation of the sense amplifier MOS transistor, the depletion layer extends from the side surface of the silicon layer 34 toward the center, as shown in FIG. Therefore, if the dimensions and impurity concentration of the silicon layer 34 are selected, for example, if one silicon layer is made as large as the minimum processing dimension, the center of the silicon layer 34 can be easily depleted.
4, the resistance seen in the vertical direction is sufficiently large. As a result, a flip-flop operation that is resistant to substrate noise can be obtained. Furthermore, restricting the extension of the depletion layer means that the controllability of the gate channel is strong, as explained in the previous embodiment, and thereby excellent characteristics can be obtained.

An embodiment in which the present invention is applied to an SRAM will be described below. M
In a typical SRAM using an OS transistor, a memory cell is constructed by a flip-flop, and this flip-flop can have a vertical structure using a plurality of columnar silicon layers as in the above embodiment.

FIG. 16 is a plan view of the SRAM cell portion of this embodiment, and FIG. 17 is its equivalent circuit. By forming grooves in the silicon substrate in the same manner as in the previous embodiment, columnar silicon layers 41 (411°, 412, . . . ) are formed in an array. Transfer gate MOS transistors T1 and T
2 are formed using one silicon layer 411 and one silicon layer 412, respectively. Its structure is basically the same as that of the previous embodiment, and a drain diffusion layer is formed on the upper surface of the silicon layer and a source diffusion layer is formed in the groove.
．． A gate electrode 42.412 made of a polycrystalline silicon film surrounds the gate electrode 412. is formed.

The gate electrode 421 is connected to two MOS transistors Tl and T.
2 are continuously formed to constitute a word line WL. One driver MOS transistor T3 uses two silicon layers 4131 and 4132, and the other driver MOS transistor T4 uses the other two silicon layers 41
bl, 4162, respectively.

These MOS transistors also have the same structure as in the previous embodiment.

The gate electrode 422 of the MOS transistor T3 extends to the silicon layer 414 serving as a pedestal, and a polycrystalline silicon film wiring 432 connecting the drains of the MOS transistors T2 and T4 is brought into contact with the gate electrode 422 here. Similarly, the gate electrode 423 of the MOS transistor T4 extends to the silicon layer 415 serving as a pedestal, and the polycrystalline silicon film wiring 43 connecting the drains of the MOS transistors T1 and T3 is connected to the gate electrode 423.
I have contacted 23. Drain wiring 431, 4
32 are high-resistance polycrystalline silicon films 44 as load resistors, respectively. , 442 to a power supply (Vcc) wiring 433 made of a polycrystalline silicon film. Data line 45 made of Al film. ．． 452 and ground (Vs s
) line 453 is shown cut in the middle. Data lines 451 and 452 are each connected to a MOS transistor T1.
The contact portions 461+462 are arranged in contact with the source diffusion layer formed in the +72 groove portion. The ground line 453 is a MOS transistor T 3 *
Contact portion 4 to the source diffusion layer common to T 4
They are arranged in contact with each other at 63.

A region 47 surrounded by a dashed line in the figure indicates an element region.

This embodiment also provides the same effects as the previous embodiment. However, in the case of an SRAM cell, it does not originally require a large gate width like a DRAM bit line sense amplifier. Therefore, although the effect of reducing the occupied area is not so great, the effect of improving characteristics by configuring the driver MOS transistor using a plurality of small silicon layers is large.

In Figure 16, an SR using a high resistance polycrystalline silicon load is shown.
Although an AM embodiment has been given, the present invention can be similarly applied to an SRAM including a complete CMOS type flip-flop, an E/E type flip-flop, or an E/D type flip-flop.

[Effects of the Invention] As described above, according to the present invention, by using a vertically structured MOS transistor in which the side walls of a plurality of columnar semiconductor layers serve as channels, various M
An OS integrated circuit can be obtained. Furthermore, since the channel region is not in contact with the field, it has strong resistance to hot carrier effects, and excellent circuit characteristics can be obtained. Furthermore, by improving the subthreshold characteristics, current consumption during standby can be significantly reduced. In particular, by making the dimensions of the unit silicon layer as small as the minimum processing dimensions, the source width can be reduced to the required gate width.

The junction capacitance of the drain can be made very small, and at the same time, the signal delay at the gate electrode can be significantly reduced, thereby realizing a circuit capable of high-speed switching operation.

[Brief explanation of the drawing]

1(a) and 1(b) are a plan view and an equivalent circuit diagram showing a CMOS inverter circuit according to an embodiment of the present invention, and FIG.
a) to (d) are plan views of each part thereof. FIG. 3 is a diagram for explaining the operating characteristics of the transistor of the above embodiment, and FIG. 4 is a plan view showing an embodiment in which the gate electrodes of the two transistors of FIG. 1(a) are made independent.
FIGS. 5(a) and 5(b) are a plan view and an equivalent circuit diagram showing an embodiment of an E/R type inverter circuit, and FIGS. 6(a) and 6(b) are plan views of various parts thereof. Fig. 7 is a plan view and its equivalent circuit diagram showing an example of an E/E type eraser dual circuit, Figs. / Plan view and equivalent circuit diagram showing the E-type element 2 circuit embodiment, FIG. 10(a)
(b) is a plan view of each part. FIGS. 11(a) and 11(b) are a plan view and an equivalent circuit diagram of an embodiment of a dynamic inverter circuit, and FIG. 12(a)(
b) is a plan view of each part, and Figures 13(a) and (b) are DRA
Plan view and cross-sectional view of an embodiment of M sense amplifier, No. 14
The figure is an equivalent circuit diagram of the sense amplifier, FIG. 15 is a diagram for explaining the operating characteristics of the MOS transistor of this embodiment, FIG. 16 is a plan view of the SRAM embodiment, and FIG.
7 is its equivalent circuit diagram, FIGS. 18(a) and 18(b) are diagrams schematically showing the p-channel MOS transistor structure of the embodiment shown in FIG. p of the example of
A diagram showing the subthreshold characteristics of a channel MOS transistor in comparison with a conventional structure. FIGS. 20(a) and 20(b) are also diagrams showing characteristic changes due to hot carrier effect stress in comparison with a conventional structure. FIG. 21 is a diagram showing test results. Figures 22(a) and 22(b) are diagrams showing the static characteristics compared with the conventional structure, and Figure 23 is FIG. 3 is a plan view showing a conventional MOS transistor structure having device parameters corresponding to FIG. 1... Silicon substrate, 2... N-type well, 3...
P-type well, 4...groove, 5, 6... columnar silicon layer. 7... Gate oxide film, 8... Gate electrode, 9.10
...p-type source 2 drain diffusion layer, 11.12...
- N-type source and drain diffusion layer 113...CVD oxide film. 14 to 17...-A, 9 wiring, 19... depletion layer. Applicant's representative Patent attorney Takehiko Suzue (a) Figure 3 Figure 1 Figure 4 ■CC (b) (a) Figure 7 (a) (b) Figure 8 (a) (b) Figure (b) Figure 10 Figure 14 Figure 15 Figure 16

Claims (5)

[Claims] (1) A semiconductor substrate, a plurality of columnar semiconductor layers formed on the substrate in an array separated by grooves at predetermined intervals, a gate insulating film formed on the outer peripheral surface of each of the plurality of columnar semiconductor layers, and A gate electrode is continuously disposed along the groove so as to surround each of the plurality of columnar semiconductor layers on which a gate insulating film is formed, and the gate electrode surrounds each top surface of the plurality of columnar semiconductor layers and each semiconductor layer. Diffusion layers forming sources and drains formed at the bottom of the trench, a first main electrode commonly connected to the diffusion layer on the top surface of the plurality of columnar semiconductor layers, and a first main electrode connected to the diffusion layer at the bottom of the trench. A MOS type semiconductor device characterized by having two main electrodes. (2) In a semiconductor device including an inverter circuit configured using MOS transistors, the MOS transistors constituting the inverter circuit are formed by arraying a plurality of columnar semiconductor layers separated by grooves on a semiconductor substrate, and each columnar semiconductor layer is separated by a groove. A gate insulating film is formed on the outer circumferential surface of the semiconductor layer, and a gate electrode is continuously disposed in the groove so as to surround the plurality of columnar semiconductor layers, and the gate electrode is disposed continuously in the groove to surround the plurality of columnar semiconductor layers. A MOS type semiconductor device characterized in that it has a structure in which source and drain diffusion layers are formed at the bottom of a surrounding groove. (3) In a semiconductor device including a flip-flop circuit configured using MOS transistors, the MOS transistors constituting the flip-flop circuit are formed by arraying a plurality of columnar semiconductor layers separated by grooves on a semiconductor substrate; A gate insulating film is formed on the outer circumferential surface of each columnar semiconductor layer, a gate electrode is continuously disposed in the groove so as to surround the plurality of columnar semiconductor layers, and a gate electrode is continuously provided on the upper surface of each columnar semiconductor layer and each columnar semiconductor layer. A MOS type semiconductor device characterized in that it has a structure in which source and drain diffusion layers are formed at the bottom of a trench surrounding the layers. (4) The columnar semiconductor layer is electrically isolated from the underlying semiconductor region by a depletion layer extending from the outer peripheral surface during operation, or is internally depleted. 3. MOS type semiconductor device according to any one of 3. (5) The MOS type semiconductor device according to claim 1, wherein the columnar semiconductor layer is patterned to have a minimum processing size.