JPH02188955A - Semiconductor storage device and manufacture thereof - Google Patents

Abstract

PURPOSE:To restrain a leakage current from being generated between storage capacitors and to double a storage capacity by a method wherein one pair of storage capacitors provided respectively with counter electrodes on both sides of storage electrodes are formed in one pair of groove parts between which one pair of transfer transistors are sandwiched. CONSTITUTION:One pair of groove parts 3a, 3b are formed inside a semiconductor substrate 1 where elements have been isolated. The following are provided: a first storage capacitor and a second storage capacitor C1, C2 which have been formed in the first groove part and the second groove part 3a, 3b; and one pair of transfer transistors T1, T2 which have been formed in a region on the substrate 1 between the first groove part and the second groove part 3a, 3b. The individual transfer transistors T1, T2 are composed of gate electrodes G1, G2, sources S1, S2 and a common drain D. The individual storage capacitors C1, C2 are composed of the following: a first storage electrode and a second storage electrode 7a, 7b which are stretched respectively from the sources S1, S2 of the individual transfer transistors T1, T2; and a first counter electrode and a second counter electrode 5a, 11a or the first counter electrode and a third counter electrode 5a, 11b which are faced via the first storage electrode and the second electrode 7a, 7b and via a first capacity insulating film and a second capacity insulating film 6, 10.

Description

[Detailed Description of the Invention] B) Industrial Field of Application The present invention relates to a semiconductor memory device and a method for manufacturing the same. More specifically, the present invention relates to a semiconductor memory device and a method for manufacturing the same. Access memory (D
This article concerns the structure of a RAM cell and its formation method.

<Explanation> Conventional technology FIGS. 3(a) and 3(b) are explanatory diagrams relating to a conventional example.

Figure (a) shows a pair of storage capacitors in one groove as seen in Japanese Patent Publication No. 63-164459,
A semiconductor memory device is shown in which a pair of transfer transistors are formed above the semiconductor memory device.

In the figure, a pair of storage capacitors (C11, Cl2)
consists of a counter electrode (22) formed in a groove (26) of a P-type Si substrate (21), a capacitive insulating film (23), and storage electrodes (24a, 24b).

The transfer transistor (1'11.T12) has a gate <G
11. G12), sources (511, 512) and a common drain (D).

Storage electrodes (24a, 24b) and transfer transistors (
The source (511, 512) of the storage electrode (24a, 24b) is connected to the source (511, 512) of the storage electrode (24a, 24b) through a connection region provided in the insulating film 25) of the storage electrode (24a, 24b).

W is the intercell distance, and a pair of storage capacitors (C11
, Cl2) between the storage electrodes (24a, 24b).

FIG. 2B shows an equivalent circuit diagram of a conventional semiconductor memory device.

In the figure, storage capacitors (C11, Cl2) are connected to transfer transistors (1'11, I'12), respectively, and constitute a set of DRAMs.

(c) Problems to be Solved by the Invention According to the conventional example, the storage electrode (24a) and the storage electrode (24b) are paired in a state where the inter-cell distance W is maintained in one groove (26). storage capacitor (C1
1, Cl2) is provided.

For this reason, if the inter-cell distance W is reduced as semiconductor integrated circuit devices become smaller, it becomes extremely difficult to remove the polysilicon layer that will serve as the storage electrode only on the bottom surface of the trench (26) by photolithography.

Each storage capacitor (C11) or (C12) is composed of a storage electrode <24a, 24b) and a capacitive insulating film <23) sandwiched between a counter electrode <22).

Therefore, along with miniaturization, the amount of weight stored in the storage capacitor also decreases. This poses a problem in that the data storage performance of the DRAM deteriorates.

The present invention was created in view of the problems of the conventional example, and provides a semiconductor memory device and its manufacturing method that suppresses the occurrence of current leakage between storage capacitors and doubles the storage capacity. For the purpose of providing.

(d) Means for Solving the Problems As shown in FIG. 1.2, the semiconductor memory device and the method for manufacturing the same according to the present invention include a pair of grooves ( 3a and 3b) are provided separately, and a first groove portion (3a) provided in the first groove portion (3a) of the substrate <1)
a storage capacitor (C1), and a second storage capacitor (C1) provided in the second groove (3b) of the substrate (1).
a storage capacitor (C2); and a pair of transfer transistors (T1, T2) provided in a region on the semiconductor substrate (1) sandwiched by the first and second grooves (3a, 3b). , each transfer transistor (If, T2) has a gate electrode (G1, G2
), a source (S1, S2) and a common drain (D), each storage capacitor (C1, C2) extending from the source (S1, S2) of each transfer transistor (τ1.1:2), respectively. first and second storage electrodes (7a, 7b);
the first and second storage electrodes (7a, 7b);
The first and second capacitors face each other with the capacitive insulating film (6, 10) interposed therebetween.
It is characterized by consisting of zero opposing electrodes (5a, 11g) or first and third opposing electrodes (5a, 11b), and its formation method involves separating the elements of the semiconductor substrate (1) and forming the first storage capacitor. (CAI), a transfer transistor formation area (TA), and a second storage capacitor formation area (C
A2) and digging trenches in the semiconductor substrate (1) in the first and second storage capacitor formation regions (CA1 and CA2) to form the first and second trenches (3a, 3b). and then forming an insulating first film (4) on the inner surfaces of the first and second grooves (3g, 3b), and forming the first and second grooves (3a, 3b). selectively growing a conductive first film (5) on the semiconductor substrate (1) to form a first counter electrode (5a); ) selectively forming a first capacitive insulating film (6) on the first capacitive insulating film (6); and selectively growing a conductive second film (7) on the first capacitive insulating film (6). Then, the first and second storage electrodes (7a,
7b) and the first and second storage electrodes (7a, 7b) other than the transfer transistor formation area (TA).
forming a second capacitive insulating film (10) on the outer surface of the second capacitive insulating film (10); selectively growing a conductive third film (11) on the second capacitive insulating film (10); forming second and third counter electrodes (Lla, 11b) connected to the counter electrode (5a), and then forming the second and third counter electrodes (11a, 11).
b) forming and protecting an insulating second film (12) on the transfer transistor forming area (TA); forming a gate oxide film (on the transfer transistor forming area (rA)); 13), gate (G1.G2) and bit line (B1)
A common drain (0) connected to the common drain (0) and sources (S1, S2) connected to the first and second storage electrodes (7a, 7b)
The above object is achieved by forming a transfer transistor (T1, T2) consisting of the following steps.

(*) Function According to the present invention, the storage capacitor (ct, C2) is located in the first trench (3) between the transfer transistor (1.T2).
a, 3b).

Therefore, the first storage capacitor (
C1) and the second storage capacitor (C2) of the second groove portion (3b) can be made independent of the size of the inter-cell distance as in the conventional case.

As a result, the first groove part (3a) and the second groove part (3a)
There is no need to use extremely high-precision photolithography techniques to selectively remove the bottom polysilicon layer in b).

Further, according to the present invention, the first and second storage keys (C
1 and C2), respectively, are storage capacitors (COl, C0) composed of a counter electrode (5a) and a capacitive insulating film <6), if the storage electrodes (7a, 7b) are used as common storage electrodes.
2) can be formed. In addition, the counter electrode (11a
, 11b) and a capacitive insulating film (10) can form storage capacitors (CO3, C04).

As a result, the first storage capacitor (C1) connected to the transfer transistor (T1) becomes the storage capacitor (CO
I + C03) and the second storage capacitor (C2) can be a storage capacitor (CO2+C04), which makes it possible to double the storage capacity, respectively, compared to the structure of a conventional semiconductor memory device.

(F) Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

1 and 2 are diagrams for explaining a semiconductor memory device and its manufacturing method according to an embodiment of the present invention, and FIG. 1(a),
(b) shows an explanatory diagram of a semiconductor memory device according to an embodiment of the present invention.

Figure (a) is a sectional view showing the structure. In the figure, (C1, C2) are storage capacitors, and the P-type Si substrate (1) is separated by a field insulating film (2).
) are provided in the grooves (3a, 3b). Groove (3
a, 3b) are arranged with a transfer transistor (T1.I2) in between.

The storage capacitor (C1) has a counter electrode (5a), a capacitive insulating film (6), and a source (Sl) of the transfer transistor (T1) in a groove (3a) in which a Sin film (4) is formed on the inner surface. A storage capacitor (COI) consisting of a storage electrode (7a) extending from a storage electrode (7a), and a storage capacitor (CO2) consisting of a capacitive insulating film (10) and a counter electrode (11a) with the storage electrode (7a) in common. ing.

In addition, the storage capacitor (C2) also has Sio on the inner surface.
, a counter electrode (5a), a capacitive insulating film (6), and a storage electrode (7b) extending from the source (S2) of the transfer transistor (I2) in the groove (3b) in which the film (4) is formed.
) and a storage capacitor (CO3) consisting of a storage electrode (7
b) in common, the capacitive insulating film (10) and the counter electrode (1
1b) and a storage capacitor (CO2).

(T1.I2) is a transfer transistor and is provided in a region between storage capacitors (C1) and (C2). The transfer transistor (T1.I2) has a gate (G1
．． G2), sources (S1, S2) and common drain (D
). The gates (G1, G2) are connected to the word line, respectively, and the sources (S1, S2) are connected to the storage electrodes (7a, 7b) of the respective storage capacitors (CI, C2).
), and the common drain (D) is connected to the bit line (B1
)It is connected to the.

FIG. 2B shows an equivalent circuit diagram of a semiconductor memory device according to an embodiment of the present invention.

In the figure, storage capacitor (C1) is connected in parallel with storage capacitors (COI) and (CO3).

Also, the storage capacitor (C2) is a storage capacitor (CO
2) and (CO4) are connected in parallel.

Thereby, it is possible to increase the storage capacity compared to the conventional case.

FIGS. 2(a) to 2(i) are process diagrams for forming a semiconductor memory device according to an embodiment of the present invention.

In the figure, first, a P-type Si substrate (1) is thermally oxidized by selective LOCO8 method to form a field oxide film (2). As a result, the first storage capacitor formation region (C
AI), a transfer transistor formation area (TA), and a second storage capacitor formation area (CA2) are defined (see FIG.
, l) ).

Next, by trenching technology, both storage capacitor formation regions (
CA1. The P-type Si substrate <1) of CA2) is removed to form grooves (3a, 3b) with a depth of about 4 [μm].

Thereafter, a Sin film (4) having a thickness of about 200 (B) is formed on the inner surfaces of the grooves (3a, 3b) (FIG. 4(b)).

Next, a film with a thickness of 1,500 mm (thickness) was formed on the entire surface of the P-type Si substrate (1) on which the grooves (3a, 3b) were formed by low pressure CVD.
A poly-Si film (5) of about 100 mL is grown. After that, POCI,
The poly-Si film (5) is activated by diffusing phosphorus using the same method, and the counter electrode (5a) is formed by buttering.Then, a second film made of Sin and a film 15xaN4 is formed on the counter electrode (5a). 1 capacitive insulating film (6) is formed (see figure (c)
)).

Further, a P-type Si substrate (1) on which a capacitive insulating film (6) is formed
) was coated with a film thickness of 1500 [person] by low pressure CVD method.
A poly-Si film (7) of about 100 mL is grown. After that, HTO()! is applied to the transfer transistor formation area ('fA). igh
'! The @mparatura Oxide film (8) is protected by buttering, and phosphorus is injected into the poly-Si film (7) by ion implantation. After that, it is heat-treated and the poly-S
The i membrane (7) is activated ((d) in the same figure).

Next, the HTO film <8) was removed and the activated polyS
The i-film (7) is patterned to form storage electrodes (7a, 7
b) form. The storage electrodes (7a, 7b) are formed on both sides of the transfer transistor formation area (TA).

A second capacitive insulating film (10) made of a Si sail pattern/SiN4 film is formed on the storage electrodes (7g, 7b). here,
The first capacitive insulating film (6) and the second capacitive insulating film (10) are patterned (FIG. 4(e)).

Using a resist as a mask, the first capacitive insulating film (6) and the second capacitive insulating film (10) on the counter electrode (5a) are selectively removed. The removal method is performed by a wet etching method; for a Si film, an HF (hydrofluoric acid) based aqueous solution is used; for a Si, N film, a hot phosphoric acid aqueous solution is used.

Next, a P-type Si substrate (
1), a poly-Si film (11) is formed by low pressure CVD. After activating the poly-Si film (11) by diffusing phosphorus, the poly-Si film (11) is patterned using the resist film as a mask. At this time, a counter electrode (11a) is formed on the capacitive insulating film (10) in the groove (3a). Similarly, a counter electrode (ttb) is formed on the capacitive insulating film <10> of the groove (3b). In addition, the counter electrode (11a,
11b) and the counter electrode (5a) are joined at this time ((f) in the same figure).

Next, the counter electrodes (5a, 11a, 11b) are thermally oxidized to form a Si film <12>. The heat treatment conditions at this time were as follows: heating time was 30 minutes in an oxygen atmosphere.
[minutes] and the heating temperature is about 900 ("C). After that, Siow on the transfer transistor formation area (TA) is heated.
The removal method for removing the Si and N films is the same as that for the capacitive insulating films (6, 10) described above. Furthermore, the transfer transistor forming area (TA) is single crystallized. Single crystallization is performed by laser annealing, etc. ((g) in the same figure)
.

Thereafter, a gate oxide film (13) is formed in the transfer transistor formation area (TA). On top of that, the gate electrode (G1,
G2) and further monocrystalline poly-Si film (7)
Sources (S1, S2) and a common drain (D) are formed by diffusing impurities. This allows the source (Sl)
A transfer transistor (
T1) and a transfer transistor (T2) connected from the source (S2) to the storage electrode (7b) are formed (see FIG.
h)).

After the formation process shown in FIG. 6(h), the gate electrode (
An insulating film <14) is formed on the word extending Gl, G2), and then a bit line (B1) is formed on the common drain (D>) (FIG. 1(i)).

Through these steps, a semiconductor memory device having a structure as shown in FIG. 1(,) can be manufactured.

In this way, the storage capacitor (CLC2) is provided in the first groove portion (3a, 3b) between the transfer transistors (I'1.1:2).

Therefore, the first storage capacitor (
C1) and the second storage capacitor (C2) of the second groove portion (3b) can be made independent of the size of the inter-cell distance W as in the conventional case.

This eliminates the need for separating the first storage electrode (7a) and the second storage electrode (7b) at the bottom of the groove by photolithography as in the conventional art.

Further, according to the present invention, the first and second storage capacitors (C
1 and C2), respectively, are storage capacitors (COl, C0) composed of a counter electrode (5a) and a capacitive insulating film (6), if the storage electrodes (7a, 7b) are used as common storage electrodes.
3), a storage capacitor (CO2, C
04).

As a result, the first storage capacitor (C1) connected to the transfer transistor (T1) becomes the storage capacitor (CO
I + C02), the second storage capacitor (C2) can be a storage capacitor (CO3 + C04), and compared to the structure of a conventional semiconductor memory device, even if the device is downsized, the storage capacitance can be kept constant. It is possible to double the amount.

(G) As described in detail, according to the present invention, storage capacitors can be formed by separating into two groove portions regardless of the distance between cells as in the prior art.

This eliminates the need for separation by photolithography at the bottom of the groove between storage capacitors as in the prior art, making it extremely easy to manufacture.

Further, according to the present invention, the storage capacity can be doubled compared to the conventional one.

This makes it possible to manufacture highly integrated, high-performance semiconductor memory devices.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are a cross-sectional view and an equivalent circuit diagram of a semiconductor memory device according to an embodiment of the present invention, and FIGS. 2(a) to 2(b) are
(i) is a cross-sectional view explaining the formation process of a semiconductor memory device according to an embodiment of the present invention, and FIGS. 3(a) and (b) are cross-sectional views and equivalent circuit diagrams of a semiconductor memory device according to a conventional example. It is.

Claims (2)

[Claims] (1) A pair of grooves (3a, 3b) are provided separately in a semiconductor substrate (1) with element isolation, and a first groove provided in the first groove (3a) of the substrate (1).
a storage capacitor (C1), and a second storage capacitor (C1) provided in the second groove (3b) of the substrate (1).
a storage capacitor (C2), and a pair of transfer transistors (T1, T2) provided in a region on the semiconductor substrate (1) between the first and second trenches (3a, 3b), Each said transfer transistor (T1, T2) consists of a gate electrode (G1, G2), a source (S1, S2) and a common drain (D), and each said storage capacitor (C1, C2) consists of a gate electrode (G1, G2), a source (S1, S2) and a common drain (D); , T2) respectively extend from the sources (S1, S2), the first and second storage electrodes (7a, 7b), and the first and second capacitors. The first and second counter electrodes (5a, 11a) or the first and third counter electrodes (5
a, 11b). (2) The semiconductor substrate (1) is separated into a first storage capacitor formation area (CA1), a transfer transistor formation area (TA), and a second storage capacitor formation area (C
A2), and defining the first and second storage capacitor formation regions (CA1, CA
2), grooves are dug in the semiconductor substrate (1) to form the first and second grooves (3a, 3b), and then the first and second grooves (3a, 3b) are formed.
A step of forming an insulating first film (4) on the inner surfaces of the first and second grooves (3a, 3b); a first capacitive insulating film (5) selectively grown on the first counter electrode (5a); 6), and selectively growing a conductive second film (7) on the first capacitor insulating film (6) to form the first and second storage electrodes (7a, 7a,
7b), and forming the first and second areas other than the transfer transistor formation area (TA).
A second capacitive insulating film (
10), and selectively growing a conductive third film (11) on the second capacitive insulating film (10) to form a third conductive film (11) connected to the first counter electrode (5a). 2 and 3 counter electrodes (11a, 11b) are formed, and then the second and third counter electrodes (11a, 11b) are formed.
a step of forming and protecting an insulating second film (12) on the transfer transistor forming area (TA), a step of monocrystallizing the transfer transistor forming area (TA), and a step of forming a gate oxide film (13) on the transfer transistor forming area (TA). , gates (G1, G2) and bit lines (BL)
a common drain (D) connected to the common drain (D), and sources (S1, S2) connected to the first and second storage electrodes (7a) (7b).
1. A method of manufacturing a semiconductor memory device, comprising the step of forming transfer transistors (T1, T2).