JPH02183524A - Plasma ashing method - Google Patents
Plasma ashing methodInfo
- Publication number
- JPH02183524A JPH02183524A JP204389A JP204389A JPH02183524A JP H02183524 A JPH02183524 A JP H02183524A JP 204389 A JP204389 A JP 204389A JP 204389 A JP204389 A JP 204389A JP H02183524 A JPH02183524 A JP H02183524A
- Authority
- JP
- Japan
- Prior art keywords
- resist film
- substrate
- temperature
- eliminated
- surface layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004380 ashing Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 239000001301 oxygen Substances 0.000 claims abstract description 11
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 6
- 238000010438 heat treatment Methods 0.000 claims description 3
- 239000002344 surface layer Substances 0.000 abstract description 13
- 238000004880 explosion Methods 0.000 abstract description 7
- 238000006243 chemical reaction Methods 0.000 abstract description 4
- 230000035882 stress Effects 0.000 abstract description 3
- 239000012495 reaction gas Substances 0.000 abstract 3
- 230000008030 elimination Effects 0.000 abstract 1
- 238000003379 elimination reaction Methods 0.000 abstract 1
- 230000008642 heat stress Effects 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 6
- 238000003672 processing method Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 230000008646 thermal stress Effects 0.000 description 3
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 229910001882 dioxygen Inorganic materials 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 230000008016 vaporization Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Landscapes
- ing And Chemical Polishing (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、半導体の基板に塗布されたレジスト膜をプラ
ズマを利用してアッシング(灰化)することにより除去
するプラズマアッシング方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a plasma ashing method for removing a resist film coated on a semiconductor substrate by ashing (ashing) it using plasma.
(従来の技術)
微細なIC回路を加工するために、半導体基板の表面に
回路パターンを形成したレジスト膜を設け、該レジスト
膜を介してその下層の絶縁膜、半導体膜或いは金属膜を
エツチングすることが行なわれている。(Prior art) In order to process minute IC circuits, a resist film with a circuit pattern formed thereon is provided on the surface of a semiconductor substrate, and the underlying insulating film, semiconductor film, or metal film is etched through the resist film. things are being done.
該レジスト膜は、エツチング処理が終了したのち基板表
面から除去されるが、その除去方法には過酸化水素、有
機溶剤などの化学薬品を使用する湿式処理方法と、酸素
プラズマを用いてレジスト膜をアッシング(灰化)する
乾式処理方法とがある。The resist film is removed from the substrate surface after the etching process is completed, and there are two methods for removing it: wet processing using chemicals such as hydrogen peroxide and organic solvents, and oxygen plasma to remove the resist film. There is a dry processing method that involves ashing.
該湿式処理方法に使用される薬品には人体に有害なもの
が多く、除去作業の安全性の維持や廃液の公害防止に注
意を払う必要があって煩わしい。しかも使用される薬品
は多少は不純物を含むので、これが半導体回路のパター
ンの欠損や汚染の原因となり、超LSI等の微細な加工
には適しない。Many of the chemicals used in the wet treatment method are harmful to the human body, and care must be taken to maintain the safety of the removal work and prevent pollution of the waste liquid, which is troublesome. In addition, the chemicals used contain some impurities, which cause defects and contamination of semiconductor circuit patterns, making them unsuitable for microfabrication of ultra-LSIs and the like.
該乾式処理方法は、基板゛に塗布されたCx1lyNz
のレジスト膜に、酸素プラズマ中に生じた酸素ラジカル
を反応させ、該レジスト膜をCO□、N02及びN20
へ分解・気化することによって除去するので、湿式処理
方法のような人体への有害物の発生がなく、不純物を含
まないので基板の微細加工に適している。The dry processing method includes Cx1lyNz applied to a substrate.
The resist film is reacted with oxygen radicals generated in oxygen plasma, and the resist film is exposed to CO□, N02 and N20.
Since it is removed by decomposition and vaporization, it does not generate harmful substances to the human body unlike wet processing methods, and it does not contain impurities, so it is suitable for microfabrication of substrates.
該乾式処理方法の具体例は第1図及び第2図示の如くで
あり、レジスト膜が塗布された基板(1)を反応性ガス
の導入口り2)と真空排気口(3)を備えた真空処理室
(4)内の赤外線ランプ(5)の上方或いは温度調節制
御された埋設ヒータ(6)を備えたホットプレート(7
)上に置き、該導入口(2)から導入される酸素ガス或
いはこれに少量のCF4、N2もしくは■2を混入した
反応性ガスをマイクロ波放電部(2a)に於いてプラズ
マ化し、酸素ラジカルその他の該反応性ガスのラジカル
を加熱された基板(1)上のレジストと反応させ、該レ
ジスト膜を分解・気化して該排気口(3)から真空ポン
プにより排出することにより除去している。A specific example of the dry processing method is as shown in FIGS. 1 and 2, in which a substrate (1) coated with a resist film is provided with a reactive gas inlet 2) and a vacuum exhaust port (3). A hot plate (7) equipped with a temperature-controlled embedded heater (6) or above an infrared lamp (5) in a vacuum processing chamber (4).
), and oxygen gas introduced from the inlet (2) or a reactive gas mixed with a small amount of CF4, N2 or The radicals of the other reactive gases are removed by reacting with the resist on the heated substrate (1), decomposing and vaporizing the resist film, and discharging it from the exhaust port (3) using a vacuum pump. .
第1図示の場合、真空処理室<4)内のラック(8)上
に置かれた基板(1)は、赤外線ランプ(5)によって
、第3図の曲線Aのように約5秒で所定の温度にまで加
熱される。該基板(1)の温度管理は、該基板(1)の
表面から熱輻射される赤外線を検出して温度に換算する
赤外線温度計(9)によって管理され、該温度計(9)
の出力信号をランプ(5)の電源へフィードバックし、
電力をコントロールすることにより基板(1)の温度を
一定温度に保つ。In the case shown in Fig. 1, the substrate (1) placed on the rack (8) in the vacuum processing chamber (<4) is heated by the infrared lamp (5) in about 5 seconds as shown by curve A in Fig. 3. heated to a temperature of The temperature of the substrate (1) is managed by an infrared thermometer (9) that detects infrared rays thermally radiated from the surface of the substrate (1) and converts it into temperature.
Feedback the output signal to the power supply of the lamp (5),
The temperature of the substrate (1) is maintained at a constant temperature by controlling the power.
また、第2図示の場合、基板(1)はホットプレー ト
(7)との熱接触によって熱量が与えられ、第4図の曲
線Bで示すように約10秒後に所定の温度にまで加熱さ
れる。該ホットプレート(7)は熱電対式温度計(IO
により一定温度に管理される。In addition, in the case shown in Figure 2, the substrate (1) is given heat by thermal contact with the hot plate (7), and is heated to a predetermined temperature after about 10 seconds as shown by curve B in Figure 4. Ru. The hot plate (7) is equipped with a thermocouple thermometer (IO
The temperature is controlled at a constant temperature.
(発明が解決しようとする課題)
基板(1)に塗布されたレジスト膜をマスクとして利用
し、該基板(1)の表面に局部的に不純物をイオン注入
することが回路の微細化に伴い頻繁に行なわれるように
なってきている。この場合、第5図に見られるように、
マスクとして利用したレジスト膜qvはイオンビームに
よりその表層部分(11a)が硬化変質し、その内部に
ストレスを保有するようになり、該レジスト膜(Itを
前記乾式処理方法でアッシングして除去しようとすると
、第6図に見られるように、急激な熱応力でレジスト膜
(11)が爆発することがある。この爆発によるレジス
ト膜l′l′Dのフレイタは基板(1)上や真空処理室
(1)内にダクト、残留物として残り、基板〈1)に微
細な加工を施す上で障害となる。(Problem to be Solved by the Invention) With the miniaturization of circuits, it is becoming more common to locally implant impurity ions into the surface of the substrate (1) using a resist film coated on the substrate (1) as a mask. This is becoming more and more common. In this case, as seen in Figure 5,
The surface layer (11a) of the resist film qv used as a mask is hardened and altered by the ion beam, and it begins to contain stress within it. Then, as shown in Fig. 6, the resist film (11) may explode due to sudden thermal stress.The resist film (11) due to this explosion may be damaged on the substrate (1) or in the vacuum processing chamber. (1) remains as a duct and residue, which becomes an obstacle in performing fine processing on the substrate (1).
発明者の実験によれば、該レジスト膜(11)の爆発下
限温度は、イオン注入条件、レジストの種類によって異
なるが、約70〜160℃の範囲にあり、該レジスト膜
(′11)の幅が太い程爆発しやすいことが分った。According to the inventor's experiments, the lower limit explosion temperature of the resist film (11) is in the range of about 70 to 160°C, although it varies depending on the ion implantation conditions and the type of resist. It turns out that the thicker the material, the more likely it is to explode.
本発明は、レジスト膜を爆発させることなくアッシング
により除去する方法を提案することを目的とするもので
ある。An object of the present invention is to propose a method for removing a resist film by ashing without causing it to explode.
(課題を解決するための手段)
本発明では、真空処理室内にレジスト膜が塗布された基
板を設け、該レジスト膜を該基板を加熱し乍ら酸素プラ
ズマ中でアッシングして除去する方法に於いて、該基板
の温度を、該レジスト膜の表層が除去されるまで低温に
制御し、その後高温にてアッシングして該レジスト膜を
除去するようにし、レジスト膜が爆発を生じずに除去さ
れるようにした。(Means for Solving the Problems) In the present invention, a substrate coated with a resist film is provided in a vacuum processing chamber, and the resist film is removed by ashing in oxygen plasma while heating the substrate. and controlling the temperature of the substrate at a low temperature until the surface layer of the resist film is removed, and then ashing at a high temperature to remove the resist film, so that the resist film is removed without causing an explosion. I did it like that.
(作 用)
基板の表面に塗布されたレジスト膜を除去するために、
該基板を真空処理室内に置き、加熱し乍ら酸素プラズマ
を該室内に導入し、該レジスト膜をアッシングするが、
その際該基板の温度は最初は低温に制御され、次いで高
温に制御されるので、最初の低温の状態でイオンビーム
が照射されて硬化変質したレジスト膜の表層を急激な熱
応力を与えずに即ち爆発させずに除去し、その後該レジ
スト膜の内部を急速に高温化して高速でアッシングする
ことが出来、レジスト膜の爆発による前記した障害を解
消出来る。(Function) To remove the resist film applied to the surface of the substrate,
The substrate is placed in a vacuum processing chamber, and oxygen plasma is introduced into the chamber while being heated to ash the resist film.
At this time, the temperature of the substrate is first controlled to a low temperature and then to a high temperature, so that the surface layer of the resist film, which has been hardened and altered by being irradiated with the ion beam in the initial low temperature state, is not subjected to sudden thermal stress. In other words, it is possible to remove the resist film without causing an explosion, and then rapidly raise the temperature inside the resist film to perform high-speed ashing, thereby eliminating the above-mentioned problems caused by the explosion of the resist film.
(実施例)
本発明の実施例を図面第7図乃至第10図に基づき説明
する。第7図及び第8図に於いて符号(1)乃至00は
、第1図及び第2図示の符号(1)乃至(IGと同一の
ものを指称し、第7図はレジストが塗布されたシリコン
ウェハからなる半導体の基板(1)を、反応性ガスの導
入口(2)と真空排気口(3)を備えた真空処理室(4
)内の赤外線ランプ(5)の上方にラック(8)で支え
て設置した例を示す。(Example) An example of the present invention will be described based on FIGS. 7 to 10 of the drawings. In FIGS. 7 and 8, symbols (1) to 00 refer to the same symbols (1) to (IG) shown in FIGS. 1 and 2, and in FIG. 7, the resist is applied. A semiconductor substrate (1) made of a silicon wafer is placed in a vacuum processing chamber (4) equipped with a reactive gas inlet (2) and a vacuum exhaust port (3).
) shows an example in which the infrared lamp (5) is supported and installed above the infrared lamp (5) with a rack (8).
また第8図はレジストが塗布された基板(1)をホット
プレート(7)上に置いて加熱するようにした例を示す
。Further, FIG. 8 shows an example in which a substrate (1) coated with a resist is placed on a hot plate (7) and heated.
いずれの場合も、反応性ガスの導入口(2)には反応性
ガスをプラズマ化するマイクロ波放電部(2a)或いは
I?Fコイル等の放電手段が設けられ、酸素ガス或いは
これにCF、、N2もしくはN2を混入した反応性ガス
をプラズマにより励起して真空処理室(1)内へ導入す
るようになっている。また真空排気口(3)は適当な真
空ポンプに接続され、該真空処理室(1)内を例えば1
0−’Torr以下に維持するように排気する。In either case, the reactive gas inlet (2) is equipped with a microwave discharge section (2a) or I? which turns the reactive gas into plasma. A discharge means such as an F coil is provided, and oxygen gas or a reactive gas mixed with CF, N2, or N2 is excited by plasma and introduced into the vacuum processing chamber (1). Further, the vacuum exhaust port (3) is connected to a suitable vacuum pump, and the inside of the vacuum processing chamber (1) is
Evacuate to maintain the pressure below 0-'Torr.
第7図に於いて、基板(1)が第5図示のような表層(
11a)の硬化変質したC x )I y N zで表
わされるレジスト膜(′11を有する場合、当初は赤外
線ランプ(5)を点灯せずに導入口(2)から導入され
る酸素プラズマ等で励起された反応性ガスをレジスト膜
(fDに作用させ、該表層(11a)が酸素ラジカルや
反応性ガスのラジカルとの化学反応により分解・気化さ
れて除去されると、該ランプ(5)を点灯して基板(1
)を加熱し、酸素ラジカルや反応性ガスのラジカルとの
化学反応を促進させ、迅速にレジスト膜(I′Dの除去
を行なう。この場合の基板(1)の温度は第9図の曲線
Cで示すように制御され、該表層(Ila)を除去する
に必要な時間t1が過ぎるとランプ(5)を点灯し、従
来の場合と同様に約5秒後に200℃に達してレジスト
膜(′lvの迅速な除去が行なわれる。In FIG. 7, the substrate (1) has a surface layer (
When the resist film 11a) is hardened and altered and is represented by C The excited reactive gas acts on the resist film (fD), and when the surface layer (11a) is decomposed and vaporized and removed by a chemical reaction with oxygen radicals and reactive gas radicals, the lamp (5) is activated. Lights up and the board (1
) to accelerate the chemical reaction with oxygen radicals and reactive gas radicals, and quickly remove the resist film (I'D).The temperature of the substrate (1) in this case is as shown by curve C in FIG. When the time t1 necessary to remove the surface layer (Ila) has elapsed, the lamp (5) is turned on, and as in the conventional case, the temperature reaches 200°C after about 5 seconds and the resist film (' A quick removal of lv takes place.
第8図の場合、真空処理室<4)の外部に設けたエアシ
リンダからなる昇降装置■により昇降される複数本のピ
ン(Ieを、真空処理室(4)及びホットプレート(7
)を挿通して設け、基板(1)を最初は上昇したピン(
13により高温のホットプレート(7)の上方で支持し
て基板(1)の温度を低温に維持し、この間にレジスト
膜(11)の硬化した表層(Ila)を除去する。そし
てその除去後に昇降装置(′lbによりピンa3を降下
させ、基板(1)をホットプレート(7)上に載せ、基
板(1)に熱を与え乍ら残りのレジスト膜(11)を除
去する。この場合の基板(1)の温度の変化は第10図
の曲線りで示す如くであり、表層(11a)を除去する
に必要な時間t、過ぎると基板(1)をホットプレート
(7)上に降下させ、従来のホットプレートによる加熱
の場合と同様に約10秒後に200℃に達して残りのレ
ジスト膜(′lvの除去が行なわれる。In the case of Fig. 8, a plurality of pins (Ie) that are raised and lowered by a lifting device (2) consisting of an air cylinder provided outside the vacuum processing chamber (4) and a hot plate (7
), and the board (1) is initially raised with the pin (
13 to maintain the temperature of the substrate (1) at a low temperature by supporting it above a hot plate (7) at a high temperature, and during this time, the hardened surface layer (Ila) of the resist film (11) is removed. After the removal, the pin a3 is lowered by the lifting device ('lb), the substrate (1) is placed on the hot plate (7), and the remaining resist film (11) is removed while applying heat to the substrate (1). The change in temperature of the substrate (1) in this case is as shown by the curve in Figure 10, and after the time t required to remove the surface layer (11a), the substrate (1) is placed on the hot plate (7). After about 10 seconds, the temperature reaches 200° C. and the remaining resist film ('lv) is removed, as in the case of conventional heating using a hot plate.
これら第7図、第8図に示す場合、レジスト膜Cつは、
まず表層(11a)を低温で除去したのち残りを高温で
除去するので、内部にストレスを保有したレジスト膜(
′l′Dを熱応力で爆発させることなく除去出来、基板
(1)上や真空処理室(4)内がレジスト膜(lのフレ
ークで汚染されることを防げ、正確な微細回路の加工を
行なえる。In the case shown in FIGS. 7 and 8, the resist film C is
First, the surface layer (11a) is removed at low temperature and then the remaining layer is removed at high temperature, so the resist film (11a) with internal stress is removed (
'l'D can be removed without exploding due to thermal stress, preventing contamination of the substrate (1) and the inside of the vacuum processing chamber (4) with resist film (l flakes), and allowing accurate microcircuit processing. I can do it.
(発明の効果)
以上のように、本発明によるときは、基板に塗布された
レジスト膜をアッシングにより除去するに際し、該基板
の温度を該レジスト膜の表層が除去されるまで低温とし
、表層の除去後に温度とするようにしたので、レジスト
膜を爆発させることなくアッシングによる除去を行なえ
、微細な半導体回路の作成に好都合に適用出来る等の効
果がある。(Effects of the Invention) As described above, according to the present invention, when removing a resist film applied to a substrate by ashing, the temperature of the substrate is kept low until the surface layer of the resist film is removed. Since the resist film is heated to a temperature after the removal, the resist film can be removed by ashing without exploding, and the resist film can be advantageously applied to the production of fine semiconductor circuits.
第1図及び第2図は従来のアッシング方法を示す裁断側
面図、第3図は第1図示の場合の基板の温度変化を示す
線図、第4図は第2図示の場合の基板の温度変化を示す
線図、第5図及び第6図はレジスト膜の拡大断面図、第
7図及び第8図は本発明の実施例を示す裁断側面図、第
9図及び第10図は夫々第7図及び第8図の各場合の基
板の温度変化を示す線図である。Figures 1 and 2 are cut side views showing the conventional ashing method, Figure 3 is a diagram showing the temperature change of the substrate in the case shown in Figure 1, and Figure 4 is the temperature of the board in the case shown in Figure 2. Diagrams showing changes; FIGS. 5 and 6 are enlarged sectional views of the resist film; FIGS. 7 and 8 are cut side views showing examples of the present invention; FIGS. 9 and 10 are respectively FIG. 8 is a diagram showing temperature changes of the substrate in each case of FIGS. 7 and 8;
Claims (1)
レジスト膜を該基板を加熱し乍ら酸素プラズマ中でアッ
シングして除去する方法に於いて、該基板の温度を、該
レジスト膜の表層が除去されるまで低温に制御し、その
後高温にてアッシングして該レジスト膜を除去すること
を特徴とするプラズマアッシング方法。In this method, a substrate coated with a resist film is provided in a vacuum processing chamber, and the resist film is removed by ashing in oxygen plasma while heating the substrate. A plasma ashing method characterized by controlling the temperature at a low temperature until the resist film is removed, and then performing ashing at a high temperature to remove the resist film.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1002043A JP2785027B2 (en) | 1989-01-10 | 1989-01-10 | Plasma ashing method |
US07/462,380 US5226056A (en) | 1989-01-10 | 1990-01-09 | Plasma ashing method and apparatus therefor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP1002043A JP2785027B2 (en) | 1989-01-10 | 1989-01-10 | Plasma ashing method |
Publications (2)
Publication Number | Publication Date |
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JPH02183524A true JPH02183524A (en) | 1990-07-18 |
JP2785027B2 JP2785027B2 (en) | 1998-08-13 |
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Application Number | Title | Priority Date | Filing Date |
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JP1002043A Expired - Lifetime JP2785027B2 (en) | 1989-01-10 | 1989-01-10 | Plasma ashing method |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04192319A (en) * | 1990-07-23 | 1992-07-10 | Matsushita Electron Corp | Resist removing method |
US6043004A (en) * | 1997-09-19 | 2000-03-28 | Fujitsu Limited | Ashing method |
US6726800B2 (en) | 2001-06-27 | 2004-04-27 | Seiko Epson Corporation | Ashing apparatus, ashing methods, and methods for manufacturing semiconductor devices |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6417080B1 (en) | 1999-01-28 | 2002-07-09 | Canon Kabushiki Kaisha | Method of processing residue of ion implanted photoresist, and method of producing semiconductor device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62208636A (en) * | 1986-02-14 | 1987-09-12 | Fujitsu Ltd | Resist stripping method |
JPS63276225A (en) * | 1987-05-08 | 1988-11-14 | Tokyo Electron Ltd | Ashing system |
-
1989
- 1989-01-10 JP JP1002043A patent/JP2785027B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62208636A (en) * | 1986-02-14 | 1987-09-12 | Fujitsu Ltd | Resist stripping method |
JPS63276225A (en) * | 1987-05-08 | 1988-11-14 | Tokyo Electron Ltd | Ashing system |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04192319A (en) * | 1990-07-23 | 1992-07-10 | Matsushita Electron Corp | Resist removing method |
US6043004A (en) * | 1997-09-19 | 2000-03-28 | Fujitsu Limited | Ashing method |
US6726800B2 (en) | 2001-06-27 | 2004-04-27 | Seiko Epson Corporation | Ashing apparatus, ashing methods, and methods for manufacturing semiconductor devices |
Also Published As
Publication number | Publication date |
---|---|
JP2785027B2 (en) | 1998-08-13 |
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