JPH02183492A - Memory circuit - Google Patents

Abstract

PURPOSE:To prevent the unbalance between right and left process parameters or data inversion caused by a noise by inserting a p-channel transistor between a charge circuit pulling up transistor and a power supply source and turning off the transistor at reading out time. CONSTITUTION:While a CMOS static memory is ordinarily composed of MOS transistors P1-P7 and N1-N11, circuit blocks 1-4, an inverter 5, and signal lines A-G, in this invention, a p-channel MOS transistor P8 and a control signal line H for the transistor P8 are added to the CMOS static memory. According to the above-mentioned composition, at the reading out time, the signal line H is a low level in a precharge period from T4 to T5, and when a precharge signal A is made into a high level at T5, the signal line H is also made into the high level simultaneously. Further, a word line is also made into the high level, and data are outputted to a bit line. Since P8 is under an OFF state at this time, it never occurs that the bit line is inversely driven.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor memories, and particularly to CMO3 type static memory circuits.

BACKGROUND OF THE INVENTION FIG. 2 shows a conventional CMO8 type static memory. P1 to P7 are P-channel type MOS transistors, Nl'''=NII is an N-channel type MOS transistor, l is a precharge section, 2 is a memory cell, 3 is a sense amplifier, 4 is a write control section, and 5 is an inverter. A is a precharge signal line, B is a bit line, C is a word line, D is a sense amplifier output line, E is a bias line,
F is a write control signal line, and G is a write data line. There are usually multiple memory cells, but to simplify the explanation,
It has one memory cell. FIG. 3 is a timing chart showing the operation of the static memory shown in FIG.
A, C, F, B, and B correspond to the symbols in FIG. 2, respectively.

Regarding the static memory configured as above,
The operation will be explained below.

In the write operation, first, at TI in FIG. 3, the precharge signal A is set to a low level to turn on the transistor P3, so that the bit lines B and B are at the same potential. Moreover, the transistor Pl.

The bit lines B and B change from the power supply voltage V0° to P due to Pa.
+, the potential is raised to a potential obtained by subtracting the threshold voltage of P2. Next, at T2, when the precharge signal A is set to high level and the write control signal F is set to high level, one of the bit lines B and B becomes low level depending on the level of write data signal G. If B becomes low level, transistor P2 is turned on and B is pulled up to high level. In this way, B and B have opposite polarities.

Next, when the word line C is set to high level at Ts, the transistor N1. N2 is turned on and transistors P4. P
a, N3. Data is written to the flip-flop composed of N4. In the read operation, first, at T4, the precharge signal A is set to low level, and the bit lines B and B are brought to the same potential again. Next, at Ts, the precharge signal A is set to high level, and the word line C is set to high level. Due to the data in this memory cell, one of the bit lines B and B is pulled to a high level and the other to a low level. The potential difference between the bit lines is amplified by a sense amplifier 3 using a current mirror and outputted to D.

Problems to be Solved by the Invention However, in the above conventional configuration, when the precharge signal A becomes high level at Ts in FIG.
A potential difference may occur between bit lines B and B due to causes such as an imbalance between left and right process parameters or noise. If the potential of B decreases, transistor P2 becomes more conductive and the potential of B increases, causing a further potential difference (tendency). Memory cell transistors usually have smaller driving ability than Pl and P2, so the memory cell The bit line level may move in the opposite direction to the data.

The present invention solves the above-mentioned conventional problems and aims to provide a static memory that can prevent malfunctions when reading data.

Means for Solving the Problems To achieve this object, the memory circuit of the present invention includes a P-channel transistor for disconnecting the precharge section from the power supply line.

Operation: With this configuration, by cutting off the precharge section from the power supply during data reading, it is possible to prevent the bit line from being driven in the direction opposite to the data in the memory cell.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 shows a CMO8 in an embodiment of the present invention.
FIG. 3 is a type static memory diagram. P1~P)+
N1 to N1 are MOS transistors, 1 to 4 are circuit blocks, 5 is an inverter, and A to G are signal lines, which are the same as the conventional example. Pa is P channel type MO
5) Transistor H is a control signal line of Pa. FIG. 4 is a timing chart of the control signal line H. A, C,
F.

The timings of B and B are the same as in the conventional example shown in FIG. Next, the operation of this embodiment will be explained.

During writing, the control signal line H remains at low level,
Since the transistor P8 is on, the operation is similar to the conventional example. During reading, the control signal line H is at a low level during the precharge period from T4 to Ts;
When the precharge signal A is set to high level, the control signal line H is also set to high level. Furthermore, since the word line is set to high level, the data of the memory cell is output to the bit line. At this time, since the transistor ps is off, there is no possibility of driving the bit line in the direction opposite to the data of the memory cell in the precharge section.

Effects of the Invention According to the present invention, by inserting a P-channel transistor between the pull-up transistor of the charge circuit and the power supply line, and controlling the transistor to turn off during reading, it is possible to unbalance the left and right process parameters. Data inversion due to balance or noise can be prevented, thereby providing an excellent CMO8 type static memory.

[Brief explanation of the drawing]

FIG. 1 is a diagram of a CMO8 type static memory according to an embodiment of the present invention, FIG. 2 is a diagram of a conventional CMO8 type static memory, and FIGS. 3 and 4 are timing charts. P1 to P8...P channel type MOS transistor, N1 to N11...N channel type MO3 transistor, l...Precharge section, 2...
・Memory cell, 3...Sense amplifier, 4...
...Write control unit, 5...Inverter, A.
...Precharge signal line, B, B...Bit line, C...Word line, D...Sense amplifier output line, E...・Bias wire 1. F...
...Write control signal line, G...Write data line, H...Control signal line. Name of agent: Patent attorney Shigetaka Awano

Claims (1)

[Claims] first and second bit lines having opposite polarities;
second and third P-channel type MOS transistors (hereinafter referred to as T_r_p), and the first T_r_p
a drain of the first T_r_p is connected to the first bit line, a gate of the first T_r_p is connected to the second bit line, a drain of the second T_r_p is connected to the second bit line, and a drain of the second T_r_p is connected to the second bit line; The gate of the second T_r_p is connected to the first bit line, the source of the first T_r_p and the source of the second T_r_p are connected to the drain of the third T_r_p, and the third T_r_p 1. A memory circuit having a configuration in which a source of the T_r_p is connected to a power supply line, and has a function of preventing malfunction by making the third T_r_p non-conductive when reading data.