JPH02181662A - Sampling circuit for pulse amplitude data - Google Patents

Abstract

PURPOSE:To eliminate the need of decision whether data is effective or ineffective by synchronizing pulse rising differential pulse with amplitude data and changing the sampling time of the data. CONSTITUTION:As to an input signal 1, analog quantity is converted n-bits of digital value by an A/D conversion circuit 2 every time a clock pulse is given. Based on the digital value, a comparator 5 decides whether or not the amplitude is larger than a threshold level 4, and a signal detection signal 6 is generated. The rising differential pulses of the signal 6 are generated in a DFF71 and an AND gate 81 and the output time thereof is changed by delaying them in the DFF71-73. After ANDing the 2nd or the 3rd differential rising pulse 102 or 103 with the signal 6, a sampling pulse is outputted to corresponding AND gate 82 or 83. Furthermore, an OR gate 15 in n-bits generates a 1st delay rising signal and a data sampling enabled signal. In such a sampling circuit, the decision whether the data is effective or ineffective and the storage of it are not needed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to a pulse signal specification measuring device, particularly a radar,
ESM(Electronic 5uppor)
t Measure) and E CM (Electron
The present invention relates to a pulse amplitude data sampling circuit used in a pulse signal specification measuring device in the field of ic counter measurement and the like.

[Conventional technology]

Conventionally, there has been a device of this type as shown in FIG.

In the figure, 1 is an input pulse signal, 2 is an A/D conversion circuit that outputs an n-bit digital value 3 every time a clock pulse 19 is applied, and 5 is an n-via) digital value 3 is compared with a threshold level 4. , a comparator 7° which outputs the signal detection signal 6 delays the signal detection signal 6 by one clock. The first D flip-flop 8I is a first AN which takes the AND of the signal detection signal 6 and the output of the first D flip-flop 71 and outputs a rising differential pulse 9.
The D gates 78 to 74 input the rising differential pulse 9 and the first to third delayed rising differential pulses l, respectively.
second to fourth D flip-flops outputting OI~103; 20. ~2os are first to third n focus registers with enable/output control that store n-bit digital values 3; 21. .

218 is the second. Third n-bit register with enable/output control 20! , 203, which stores the validity/invalidity of the data. ``2nd J- is a flip-flop, 8*, 8s are 2nd and 3rd AND gates that take the AND of the 2nd and 3rd delayed rising differential pulses 10m and 10s and the signal detection signal 6, 22...22 wealth is the AND of the outputs of the flip-flops in the 1st #2nd J-, and the 1st and 2nd enable
The first one controls the output of the n-bit register with output control. The second NAND gate, 23 is a reset pulse for resetting the control circuit, and 18 is pulse amplitude sampling data.

Next, the operation will be explained using FIG. 3.

When the input pulse signal 1 is input to the A/D conversion circuit 2, an n-bit digital value 3 is obtained every time a clock pulse 19 is applied. The comparator 5 compares whether the digital value 3 of the n-focus exceeds the threshold level 4, distinguishes between noise and signal, and outputs a signal detection signal 6. The first D flipflop 71 delays the signal detection signal 6 by one clock, and the AND gate 8. A rising differential pulse 9 is generated by performing an AND with the signal detection signal 6. When the rising differential pulse 9 is output to the enable terminal of the first enable/output control n-focus register 20°, the n-bit digital value 3 when it exceeds the threshold level 4 for the first time becomes the first n-bit enable/output control register. Register 20. is stored in Also, the rising differential pulse 9 is applied for one clock, and the second for two clocks.
It is delayed by the third 0797170717m, 7a, and its output is the first . 2nd delayed rising differential pulse 1G+,
2nd 10m each. When outputting to the enable terminals of the third n-bit register with enable/output control 20g, 20s, the second n-bit register with enable/output control 20! The second and third clocks from the rising edge of the pulse
The n-bit register with enable/output control 203 has 3
The digital value of the clock is stored. The second delayed rising differential pulse 10, which is the output of the third D flip-flop 7, and the signal detection signal 6 are connected to the second AND gate 8. If we take the logical product with
This shows that the above is true.

Similarly, the second delayed rising differential pulse 10□ is
The third delayed rising differential pulse 10s delayed by one clock in the flip-flop 74 and the signal detection signal 6 are applied to the third AND gate 8. When the AND is taken, the output is the second ., which indicates that the pulse width is -4 or more. Third AND gate 8□, 8. If the pulse width is -3 or more, the flip-flop 21) is applied to the first J-, and if the pulse width is 4 or more, the first . Flip-flop 21. ．． 21 wealth will be given cents each. If the flip-flop 21g is set in the second J-, the data of the third n-bit register with enable/output control 20° is output as pulse amplitude sampling data 18, and the flip-flop 21g is set in the first J-. is set, and if the flip-flop 21 in the second J- is in the reset state, the first NAND
Gate 221 is enabled and first n-bit register with enable/output control 20. data is output as pulse amplitude sampling data 18.

In summary, when the pulse width is -1 or 2, the 1st clock data, when the pulse width is -3, the 2nd clock data When the pulse width is -4 or more, the 3rd clock data is output as pulse amplitude sampling data 18. . 1st. The second J- flip-flops 21i and 21□ are reset by the reset pulse 23 and become ready to process the next input pulse signal 1.

[Problem to be solved by the invention]

Since the conventional pulse amplitude data sampling circuit is configured as described above, it requires two n-bit registers with enable/output control, and two flip-flops for storing valid/invalid data, which reduces the circuit size. The problem was that it became large.

This invention was made in order to solve the problems of the conventional ones as mentioned above.

It is an object of the present invention to provide a pulse amplitude data sampling circuit that eliminates the need for invalidity determination and can be constructed at low cost and in a small size.

[Means to solve the problem]

The pulse amplitude data sampling circuit according to the present invention includes:
The data is sampled by delaying the pulse amplitude data by one clock and synchronizing with the pulse rising differential pulse.

[Effect]

In this invention, since the circuit is configured to sample data by synchronizing the pulse rising differential pulse and the pulse amplitude data, it is possible to determine whether the data is valid or invalid and to store the three data. no longer necessary.

(Example〕 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a pulse amplitude data sampling circuit according to an embodiment of the present invention. In FIG. 1, the same reference numerals as in FIG. 3 indicate the same or corresponding parts. In FIG. 1, 1 is an input pulse signal, 2 is a clock pulse 19
A that outputs n-bit digital value 3 every time
/D conversion circuit; 5, a comparator that compares the n-bit digital RAY direct 3 with the threshold level 51, and outputs a signal detection signal 6; 7. 8. is a first D flip-flop that delays the signal detection signal 6 by one clock; 7 is a first AND gate which takes the logical product of the signal detection signal 6 and the output of the first D flip-flop 7 and outputs a rising differential pulse 9; 7□ to 74 input the rising differential pulse 9, and 1st to 3rd delayed rising differential pulses 10. ~1
0. The second to fourth D flip-flops output 8g
, 8* are the signal detection signal 6 and the second . The third delayed rising differential pulse is ANDed with the second delayed rising differential pulse, respectively. The second .
A third AND gate 13 is an n-bit D flip-flop that delays the n-bit digital value by one clock and outputs a delayed digital value 14; 15 is the first delayed rising differential pulse 101 and the second . An OR gate 17 which takes the logical sum of the third data sampling pulse 1)1゜1)□ and creates the data sampling enable pulse 16.
is an n-bit register with an enable that samples the delayed digital value 14 by a data sampling enable pulse 16, and 18 is its output, pulse amplitude sampling data.

Next, the operation will be explained using FIG.

When the input pulse signal 1 is input to the A/D conversion circuit 2, an n-bit digital value 3 is obtained every time a clock pulse 19 is applied. The comparator 5 compares whether the n-bit digital value 3 exceeds the threshold level 4, distinguishes between noise and signal, and outputs a signal detection signal 6. The first D flip-flop 71 delays the signal detection signal 6 by one clock, and the AND gate 81 performs a logical product with the signal detection signal 6 to generate a rising differential pulse 9.
can be created. This rising differential pulse 9 is
When the D flip-flops 72 to 74 delay by 1 to 3 clocks, the first to third delayed rising differential pulses 10+
~103 can be done. When the second rising differential pulse 102 and the signal detection signal 6 are ANDed by the AND gate 82, the output is the second data sampling pulse 1).
1 becomes valid when the pulse width of the input pulse is 3 or more. Similarly, when the third rising differential pulse 103 and the signal detection signal 6 are ANDed by the AND gate 83, the output is the third data sampling pulse 1) The pulse width of the input pulse is 4 or more. It becomes effective at the time.

The A/D converted n-bit digital value 3 is delayed by one clock by the n-bit D flip-flop 13 and becomes a delayed digital value 14. First, the first delayed rising differential pulse 10. passes through the OR gate 15, becomes the data sampling enable pulse 16, and becomes the data sampling enable pulse 16.
The delayed digital value 14 is output to the bit register 17.
is stored in the n-bit register 17 with enable. The delay digital value 14 is 1 from the n-bit digital value 3.
Since the clock is delayed, the digital signal stored at this time is input pulse signal 1, which reaches threshold level 4 for the first time.
It matches the data when exceeding .

Further, when the pulse width of the input pulse signal 1 is 3 or more, the second data sampling pulse 1) becomes valid and is outputted to the n-bit register with enable 17 through the OR gate 15, and the delayed digital value 14 is stored in the n-bit register 17 with enable again. At this time, the stored data matches the data of the second clock from the rising edge of the pulse. Similarly, when the pulse width is 4 or more, the data at the third clock from the pulse rise is the enable length.
It is stored in the bit register 17.

The data stored in the enable register 17 is output as pulse amplitude sampling data 18. Therefore, when the pulse width is -1 or 2, the first clock data pulse width is -3, and when the second clock data pulse width is -4 or more, it is 3.
The clock data is pulse amplitude sampling data 1
It becomes 8.

In the above embodiment, the rising differential pulse 9 is created by performing a logical AND operation on a signal obtained by delaying the signal detection signal 6 by one clock, the signal detection signal 6, and the AND gate 81.
The second to fourth D flip-flops 7t to 74 delay the first to third delayed rising differential pulses IL to 10. However, as another example, as shown in FIG. The second D flip-flops delay each clock by 1.2 clocks, and their outputs are connected to an AND gate 8. A logical AND is performed with , a rising differential pulse 10I corresponding to the first delayed rising differential pulse is created, and a third . Fourth
The second flip-flop 7z, 74. Third delayed rising differential pulse 10t.

10 may be created.The other operations are exactly the same as in the previous embodiment. In addition, in this Figure 2, 1
-8.10-19 are the same as the embodiment shown in FIG.

〔Effect of the invention〕

As described above, according to the pulse amplitude data sampling circuit according to the present invention, the digital value after A/D conversion is
By configuring the circuit so that it can be synchronized with the rising differential pulse by delaying the clock, there is no need to judge whether data is valid or invalid, which has the effect of making the device cheaper and more compact. There is.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a pulse amplitude data sampling circuit according to one embodiment of the present invention, FIG. 2 is a circuit diagram showing another embodiment of the present invention, and FIG. 3 is a circuit diagram showing a conventional pulse amplitude data sampling circuit. be. In the figure, 1 is an input pulse signal, 2 is an A/D conversion circuit, 3 is an n-bit digital value, 4 is a threshold level, 5 is a comparator, 6 is a signal detection signal, 7 is a D flip-flop, and 8 is an AND gate, 9 is a rising differential pulse, 10 is a delayed rising differential pulse, 1) is a data sampling pulse, 13 is an n-bit D flip-flop, 1
4 is a delay digital value, 15 is an OR gate, 16 is a data sampling enable pulse, 17 is an n-bit register with enable, 18 is pulse amplitude sampling data, 19 is a clock pulse, 20 is an n-bit register with enable output control, 21 is a Flip-flop on J-,
22 is a NAND gate, and 23 is a reset pulse. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A circuit that samples pulse amplitude data by changing the sampling time from the pulse rise depending on the length of the input pulse signal, and converts the input pulse signal from an analog value to an n-bit digital value every time a clock pulse is applied. Based on the converted A/D conversion circuit and the converted digital value, it is determined whether the amplitude value is larger than the threshold level,
A comparator that creates a signal detection signal, a first D flip-flop and a first AND gate that create a rising differential pulse of the signal detection signal, and a first to third delayed rising differential pulse that delays the rising differential pulse. A three-stage D flip-flop that creates a pulse, a second AND gate that performs an AND operation between the second delayed rising differential pulse and the signal detection signal and outputs a second data sampling pulse, and a third delayed rising differential pulse. A third AND gate that performs the logical product of the differential pulse and the signal detection signal and outputs the third data sampling pulse, and a third AND gate that delays the A/D converted n-bit digital value by one clock and outputs the delayed digital value. pulse amplitude data, comprising: an n-bit D flip-flop for generating pulse amplitude data; an OR gate for generating a first delayed rising differential pulse and a data sampling enable signal; and an n-bit register with enable for storing pulse amplitude data. sampling circuit.