JPH02181457A - Testing method of integrated circuit device with bump electrode - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides an integrated circuit device formed as a so-called flip chip equipped with bump electrodes for connection with the outside, which is fabricated in a wafer. This article relates to a method for efficiently conducting tests using automatic test equipment and the like.

[Conventional technology]

As the degree of integration of integrated circuit devices improves, the number of elements built into a single chip has increased significantly, or the chip size has decreased, but the area and structure when mounting it on a wiring board etc. It is not always easy to rationalize in accordance with such advances.For example, in a conventional structure in which an integrated circuit device is housed in a plastic package and then mounted on a wiring board, etc., the chip size is extremely large compared to the chip size. If a large mounting area is required, or if the integrated circuit device is attached to a wiring board as a chip, such as in a so-called hybrid integrated circuit device, bonding is used to connect the chip of the integrated circuit device and the wiring conductor of the wiring board. An area is required for the connection, and in either case, it takes considerable effort and cost to complete the implementation.

As is well known, the above-mentioned flip-chip integrated circuit device solves this problem by creating many small bump electrodes made of metal such as gold, Si, or solder on the chip of the integrated circuit device. By directly press-fitting or soldering the bump electrodes to the wiring conductors of the wiring board, the integrated circuit device can be mounted and connected to the wiring board, etc. at the same time, and the mounting can be completed within the chip size. The required area can be kept to a minimum, and the effort and cost required for implementation can be significantly reduced.

Conventionally, flip chips of such integrated circuit devices include:
Usually, about several tens to hundreds of rectangular or circular bump electrodes each having a size of about 100 nm are provided along the periphery of the chip at an arrangement pitch of about 200 nm, which is twice that size.

At the time of mounting, each bump electrode and the corresponding wiring conductor may be brought into contact with each other and bonded together under heat and pressure.

[Problem to be solved by the invention]

However, as the number of circuit elements that can be incorporated into each integrated circuit device increases, the number of connection points with the outside must also increase accordingly, and recently, hundreds of bump electrodes are installed on a single flip chip. In some cases, bump electrodes cannot be arranged around the periphery of a small chip, resulting in a problem.

For this reason, it is necessary to reduce the size of each bump electrode and the arrangement pitch thereof, but there are restrictions on this from testing equipment for integrated circuit devices. Testing of integrated circuit devices is usually performed using automatic test equipment on wafers that have not yet been separated into chips. integrated circuit devices must be connected to the test equipment in sequence by moving the test probe precisely over the integrated circuit devices in the wafer one after the other and ensuring that the contactors are in contact with the bump electrodes of the integrated circuit devices each time. In order to achieve this, the size of the bump electrodes usually needs to be at least about 50n, and the arrangement pitch needs to be at least about 90n, so testing becomes a bottleneck and it is not possible to make the bump electrodes very small.

Of course, it is possible to increase the number of these minimum bump electrodes by arranging them in double or triple layers along the periphery of the chip, but this would require increasing the chip size accordingly, making it difficult to achieve high integration. As a result of this change, there is almost no point in making the chip smaller.

In addition, the number and arrangement of bump electrodes differ depending on the circuit content to be integrated, so it is necessary to replace the test probes of the automatic test equipment and adjust the test equipment accordingly depending on the type of flip chip. In practice, this task is not only quite troublesome, but also has the problem of being prone to unexpected mistakes.

SUMMARY OF THE INVENTION An object of the present invention is to solve such problems and to enable the size and arrangement pitch of bump electrodes to be reduced without being restricted by testing, and to allow testing to proceed efficiently.

[Means to solve the problem]

According to the method of the present invention, this purpose is achieved by first depositing a base film for bump electrodes on the entire surface of the protective film covering the wafer in which the integrated circuit device to be tested is fabricated, as usual, and After growing bump electrodes as electrodes on the periphery of each integrated circuit device by electrolytic plating, temporary connection pads connected to the bump electrodes are formed by photoetching from the base film on the protective film. A test pad group is formed by arranging these temporary connection pads in a predetermined pattern in the center, and the test is performed while sequentially connecting each integrated circuit device in the wafer to the test equipment via the test pad group. This is accomplished by removing the temporary connection pads from the protective film after completion and then isolating each integrated circuit device from the wafer.

The arrangement pitch of the above temporary connection pads is matched to the contact of the test probe, but if the number and arrangement pattern are uniform regardless of the type of flip chip, it will be possible to test any integrated circuit device. The same test probes are available.

[Effect]

In the present invention, the bumps are grown by electrolytic plating,
A base film is required for the plating electrodes at that time, so if this base film is used effectively, it is possible to form temporary connection pads for testing, and the center part of each flip chip can be effectively used at the location where this is to be provided. This focuses on what is possible.

Based on this idea, in the method of the present invention, a base film for bump electrodes is first deposited on the entire surface of a protective film covering a wafer on which integrated circuit devices are fabricated, and then the bump electrodes are formed using this as an electrode. After growing on the periphery of each integrated circuit device by electrolytic plating, a plurality of temporary connection pads are formed in the center of each integrated circuit device by photo-etching the base film as in the above structure. It is formed by a pattern arrangement.

These temporary connection pads are formed within a wide area at the center of the integrated circuit device, so even if small bump electrodes are arranged at a narrow pitch on the periphery, the size and arrangement pitch of the temporary connection pads are such that it is convenient for testing. By increasing the number slightly, it is possible to obtain a standardized pattern arrangement that is the same for all integrated circuit devices. Tests on each integrated circuit device are performed via a test pad group formed from a plurality of such temporary connection pads, and if the arrangement of the temporary connection pads is standardized, any integrated circuit device can be tested. The same test probe can also be used.

After completing this test, first hold the temporary connection pad! The method of the present invention, in which each integrated circuit device can be removed from the film by etching and then isolated from the wafer by scribing as usual, can be made smaller than the conventional method, although the form is not particularly different from the conventional one. It is possible to obtain a flip chip in which a large number of bump electrodes are arranged at a narrow pitch on the periphery.

In the case of the present invention, the size of the bump electrodes can be reduced to a minimum of about 10 μm, and the pitch of the arrangement can be reduced to a minimum of about 20 μm. On the other hand, it is advantageous for the size of each temporary connection pad in the test pad group to be 100 to 150 n square and the arrangement pitch to be 250 to 500 p* in order to facilitate and ensure testing.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings. 1st
The figure is a cross-sectional view of the main parts of an integrated circuit device in which the test method according to the present invention was carried out, showing the state of each main process, and FIG. 2 is a plan view of this integrated circuit device during testing.

FIG. 1(a) shows the vicinity of the wafer 10 where the bump electrodes are provided before the bump electrodes are provided.
As usual, an n-type epitaxial layer 1a and a p-type junction isolation layer 1b are grown on a semiconductor substrate (not shown).
The bump electrode is usually provided on the upper side of the junction separation layer 1b. A connection film 3 made of aluminum or the like is provided on an oxide film 2 covering the surface of the base 1, and the left end of the connection film 3 is fabricated into an epitaxial layer la through a window opened in the oxide film 2. p-type layer 1 which is part of the element constituting the
in conductive contact with c. Wafer 1o including the top of connection film 3
The entire surface is covered with an adhesive 111114 made of silicon nitride or the like, and a window 4a is cut out at the right end of the connection film 3 where a bump electrode is to be provided.

Figure 3) shows the step of depositing the base film 5 for the bump electrode, in which the base film 5 is deposited over the entire surface of the wafer by sputtering or the like so as to make conductive contact with the connection film 3 within the window 4a. Ru. Normally, this base film 5 consists of a film such as titanium, which is a so-called barrier metal, on the side of the aluminum connecting film 3, a highly conductive film such as copper or valadinium, and a very thin gold plating film above it. It is constructed as a three-layer film consisting of and has a total thickness of about 1 nm. Figure (C) shows the growth process of the bump electrode 6. First, a photoresist film 30 is applied on the entire surface of the base film 5, a window is cut out at the location where the bump electrode is to be provided, and then the base film 5 is grown. 5 as the electrode for the negative plating voltage V shown in the figure, the photoresist wI! Bump electrodes 6 made of metal such as gold, copper, or solder are selectively grown in the window portions 30 by electrolytic plating to a thickness of usually about several tens of nanometers. In addition, the base is ll! 5 is originally an electrode for plating and for connecting the bump electrode 6 to the connection film 3, but in the method of the present invention, this is used to form a temporary connection pad.

In the step shown in FIG. 1(b), temporary connection pads 7 are formed from the base film 5 by photoetching using aqua regia or the like using a photoresist film (not shown) as a mask. The pattern of bump electrodes 6 and temporary connection pads 7 after photoetching is illustrated on the left side of FIG. Equivalent to one 5-kaku chip. Bump electrodes 6 are arranged along the periphery of each chip, and the bump electrodes 6 are formed, for example, in a rectangular shape of about 40n square;
For example, a total of about 200 coatings, 50 on each side of the chip, can be placed at a pitch of about 200 mL. The temporary connection pads 7 are provided at the center of the chip of each integrated circuit device 20, and for example, 256 temporary connection pads 7 are arranged in total, 16 of which are arranged in the vertical and horizontal directions of the figure. Except for the extra portion provided, each connection pad 7 is connected to the corresponding bump electrode 6 via a connection line 7a patterned continuously from the base film 5. This connection line 7
Please note that only one a is shown.

The test pad group 8 is thus composed of temporary connection pads 7 that are slightly larger than the number of bump electrodes 6, and is always arranged in a certain arrangement pattern in which a certain number of temporary connection pads 7 are arranged in a square shape as shown in the figure. It is desirable to connect a plurality of extra temporary connection pads 7 in parallel to the bump electrodes 6 as appropriate to improve the reliability of contact of the probe contactor to the temporary connection pad 7 during testing. be able to.

On the right side of FIG. 2, a state in which the test probe 40 is connected to the test pad group 8 is schematically shown. In this test probe 40, thin flexible metal contacts 41 with tips of about 20 pm are arranged in the same pattern as the temporary connection pads 7 in the test pad group 8. By standardizing the array pattern within the test pad group 8 as described above, the same test probe 40 can be used for testing any integrated circuit device. The automatic test equipment places this test probe 40 on the wafer lO as usual.
The integrated circuit device 20 is sequentially tested while being moved in both the X and Y directions of the figure within the plane of (.

FIG. 1(e) shows the final step, in which the used temporary connection pads 7 are first removed from the wafer 10 by means such as photo-etching. At this time, there is no problem even if a part of the connection line 7a on the bump electrode 6 side is not removed as shown in the figure.
By dividing along sL, the chips of each integrated circuit device 20 are then isolated.

The integrated circuit device 20 provided with the bump electrodes 6 and whose surface is covered with the protective film 4 can of course be mounted on a wiring board or the like in the same manner as the conventional flip chip.

The method of the present invention is not limited to the embodiments described above, and can be carried out in appropriately modified forms.For example, in the embodiments, the base film 5 is deposited directly on the surface of the protective film 4. In the step shown in FIG. 1 (b), the top of the protective film 4 is once covered with a photoresist film, and then a base film is placed on top of it! I5 can be deposited, and in the step shown in FIG. 2(e), the temporary connection passid 7 can be removed together with the underlying photoresist film by a so-called lift-off method.

〔Effect of the invention〕

As can be seen from the above description, in the method of the present invention, when manufacturing an integrated circuit device equipped with bump electrodes, first, as usual, bump electrodes are placed on the surface of a protective film covering a wafer on which an integrated circuit device is fabricated. A base film is deposited on the entire surface, and a bump electrode is grown on the peripheral edge of each integrated circuit device by electrolytic plating using this base film as an electrode. After that, the bump electrode is connected to the base film by photoetching from the base film on the protective film. Temporary connection pads are formed in the center of each integrated circuit device, and these temporary connection pads are arranged in a predetermined pattern to form a test pad group, which is indispensable as a plating electrode when providing bump electrodes. By effectively utilizing the base film,
Moreover, while making effective use of the large central area of the chip of each integrated circuit device, temporary connection pads can be formed with the same number of steps as before, with a size and arrangement pitch convenient for testing, and the size and arrangement of bump electrodes can be easily formed. The pitch can be reduced without being constrained by test conditions, and a large number of integrated circuit devices can be fabricated at the periphery of each integrated circuit device.

In addition, by standardizing or unifying the arrangement pattern of temporary connection pads within such a test pad group, the same test probe can be used for testing any integrated circuit device, reducing unnecessary preparation work, etc. The test can be carried out efficiently without much effort, and the possibility of unexpected mistakes being made can be reduced. moreover,
If the number of temporary connection pads in the test pad group is slightly larger than the number of bump electrodes and the extra temporary connection pads are connected in parallel with the bump electrodes, it is possible to Test accuracy can be improved by increasing the contact accuracy between the connection pad and the contactor of the test probe.

Since the bump electrodes reduced by the method of the present invention can be arranged in a line on the periphery of an integrated circuit device even if the required number is quite large, the chip area required for connecting the integrated circuit device to the outside can be reduced by the method of the present invention. By reducing the chip size of integrated circuit devices to a minimum,
Its economic efficiency can be improved.

[Brief explanation of the drawing]

The figures all relate to the present invention; Figure 1 is a cross-sectional view of the main parts of an integrated circuit device in which the test method according to the present invention was implemented, illustrating the state of each main step, and Figure 2 is a cross-sectional view of the integrated circuit device in this embodiment. In Figure 0, which is a plan view during the test, 1: semiconductor substrate, 1m+epitaxial layer, lb: junction separation layer, 1c: p-type layer, 2: oxide film, 3: connection film, 4:
Protective film, 4a=window, 5: base film, 6: bump electrode, 7:
Temporary connection pad, 7a: connection line for temporary connection pad, 8: test pad group, 10: wafer, 20: integrated circuit device or flip chip, 30: photoresist film, 40: test probe, 41: contactor, SL: wafer scribe line, V: electrolytic plating voltage.

Claims (1)

[Claims] A method for testing an integrated circuit device equipped with bump electrodes in the state of a wafer on which the integrated circuit device is fabricated, the method comprising completely applying a base film for the bump electrodes on a protective film covering the wafer on which the integrated circuit devices are fabricated. Using this base film as an electrode, bump electrodes are grown on the periphery of each integrated circuit device by electrolytic plating, and temporary connection pads connected to the bump electrodes are formed by photo-etching from the base film on the protective film. Then, a test pad group is formed by arranging these temporary connection pads in a predetermined pattern in the center of each integrated circuit device, and each integrated circuit device in the wafer is sequentially connected to the test equipment via the test pad group. 1. A method for testing an integrated circuit device having bump electrodes, characterized in that each integrated circuit device is isolated from a wafer after the temporary connection pads are removed from the protective film.