JPH0217823B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a multiprocessor system in which a plurality of processors share a common area.

[Prior art]

FIG. 1 is a block diagram showing a conventional multiprocessor system disclosed in, for example, Japanese Patent Publication No. 58-53382. In the figure, 1A to 1N are P ₀ to
Multiple processors indicated by Pn, 2A to 2N are CA ₀
A plurality of common areas are indicated by ~CAn, and 3 is a common area management device, which shows a general configuration.

By the way, if we consider the output data in the common area in a multiprocessor system, generally the output data in the multiprocessor system is
There is a specific processor for each output. For example, if another processor mistakenly writes to the area that processor A is outputting due to a S/W error or a malfunction during debugging, this will cause a serious system failure. ,
For this purpose, various means for preventing erroneous output of the common area have been considered.

As a means for preventing this erroneous output, the one shown in FIG. 2 has been considered. In the figure, 10A and 10B are processors CPUa and CPUb, 30A to 30D are common areas CA ₀ to _{CA 3} , 3 is a common area management device, and 40
A and 40B are output request signals REQa and 40B from processor CPUa10A and processor CPUb10B, respectively.
REQb, 41 is a bus contention control unit, 42 is a comparator,
43 is a table composed of RAM, 44 is a gate, and 45 is a common bus. Figure 3 shows the format of table 43 composed of RAM.
0 is an occupancy flag, and 51 is a processor number. In Figure 2, for example, processor CPUa1
When 0A wants to output data to the common area CA ₁ 30B, the CPUa 10A sends an output request signal REQa 40A, and sends the address and output data of CA ₁ 30B to the common bus 45 in accordance with the common area access permission signal. The common area management device 3 receives the address i of the CA ₁ 30B and refers to the contents of the address i in the table 43. If the occupancy flag 50 of address i is not set, CA ₁ 30B is in a free state where it is not occupied by any processor, so the occupancy flag 50 of the area of address i is set,
After writing the processor number of the CPUa 10A to the processor number 51, the gate 44 is opened to allow the CPUa 10A to output to the CA ₁ 30B. If the occupancy flag 50 has already been set, the comparator 42 compares the processor obtained by the bus contention control unit 41 with the contents of the processor number 51 in the table 43, and if they match, CA ₁ 3
Since 0B is an area managed by CPUa 10A, it is permitted to output data to CA ₁ 30B. If they do not match, it is an erroneous output, so the gate 44 is closed and output to CA ₁ 30B is prohibited. Furthermore, if this table 43 is all cleared at the time of initialization, there is no need to set the processor corresponding to the common area in advance, and the common area management device 3 manages the common area and at the same time sets the processor corresponding to the common area. is also executed automatically.

However, in conventional multiprocessor systems, when at least one processor fails, the failed processor is either left as failed or disconnected from the system. However, in systems that require real-time processing and systems that perform online processing,
It is desirable that another healthy processor handle the failure immediately after the failure occurs. The failure handling here refers to () abnormally terminating the job being processed by the failed processor or handing it over to a healthy processor, and () freeing the memory area used by the failed processor. (2) Processing to release the input/output device that was being used by the faulty processor.

As such conventional technology,
As shown in the above publication, in a multiprocessor system configured by combining a plurality of processors, a fault control device accessible from each processor sends a fault signal when a fault occurs in at least one of the processors. There is a processor that receives a message and instructs other healthy processors to handle the failure.

However, for small outputs of information units such as digital outputs for processes such as plant control, there is a lot of extra H/W required to apply the above functions, resulting in poor efficiency.

In response to this, the following methods have been taken as a countermeasure for the output of the process.

In the first method, as shown in FIG. 4, for example, when the processor CPUa 10A goes down, the processor CPUa 10A sends a signal DWNa 21A to notify the processor CPUb 10B that it is down. Upon receiving this signal, the CPUb 10B activates the backup S/W and performs fail-safe processing such as output reset on the common area output by the processor CPUa 10A.

As the second method, as shown in Fig. 5, the down signal of processors CPUa10A and CPUb10B is
A method was used in which DWNa21A and DWNb21B were passed directly to the process output using wire logic. A summary of this is shown below.

3, 10A, 10B, 20A, 20B, 21
A and 21B are similar to those in Fig. 4, and 30
A, 30B, 30C, and 30D are common areas.
The processors CPUa 10A and CPUb 10B have internal processor status determination units JUDGa 20A and JUDGb 20B that determine the status of their own processors, and when their own processors are started normally, the common areas CA ₀ 30A and CA ₁ occupied by their own processors are 3
Processor down signals DWNa21A and DWNb21B are not sent to 0B, CA ₂ 30C, and CA ₃ 30D. In FIG. 5, CA ₀ 30A, CA ₁ 30B are processor CPUa 10A, CA ₂ 30C, CA ₃ 30
D is occupied by processor CPUb10B. This processor down signal DWNa21A, DWNb
When 21B is not present, common area CA ₀ 30A, CA ₁ 30
It is possible to output to B, CA ₂ 30C, and CA ₃ 30D.
For example, in CA ₁ 30B, processor CPUa 10A is normal, and output can be made only from processor CPUa 10A. When the processor CPUa 10A goes down, the processor down signal DWNa 21A is sent from the processor CPUa 10A, and the CA ₀ 30A, CA ₁ occupied by the processor CPUa 10A is
30B is turned off and failsafe processing can be performed.

In the first method of conventional fail-safe processing,
It is necessary to prepare a backup S/W for each processor that is necessary when other processors go down, and a common area corresponding to each processor must be set in the backup S/W, which is a cumbersome procedure. Therefore, in order to change the common area, it was necessary to modify the backup S/W of each processor, which was extremely difficult.

In addition, in the second method, there is a H/W that sends a signal to the common area corresponding to each processor to indicate that its own processor is normal, and an H/W that sends a signal to each common area and performs fail-safe processing. There was a drawback that /W had to be provided. Furthermore, it is therefore extremely difficult to change the common area corresponding to each processor.

[Summary of the invention]

This invention was made to eliminate the drawbacks of the above-mentioned devices, and when the processor is down,
By providing a means for detecting a down processor through the table of the common area management device and performing fail-safe processing for the common area corresponding to the down processor, backup S/W or special H/W is not required for fail-safe processing. The purpose of this project is to provide a multiprocessor system that can be easily implemented without having to do this.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

In Fig. 6, 30A to 30D, 10A, 1
0B, 40A, 40B, 3, 41-45 are the same as those in FIG. 60 is a fail-safe processing device, 61A and 61B are processor down signals
DWNa, DWNb, 62 are switching signals, 63 is a fail-safe processing signal, and 64 is a selector that receives the switching signal 62 and switches between fail-safe processing and common area output.

Now, if the processor CPUa 10A is down, a processor down signal DWNa 61 is sent from the processor CPUa 10A to the failsafe processing device 60 indicating that the processor CPUa 10A is down.
A is sent, the fail-safe processing device 60 detects the address of the common area occupied by the processor CPUa 10A through the table 43 of the common area management device 3, and sends a switching signal 62 to selector 6.
4, sends the fail-safe processing signal 63 to the common bus 45 through the selector 64, and resets the output for the common area occupied by the processor CPUa 10A or transitions to a necessary state, for example, transitions the system to the safe side, etc. We are trying to perform fail-safe processing. Furthermore, processor settings and changes for common areas can be easily performed.

In the above embodiment, the table 43 is composed of occupied bits 50 and processor numbers 51.
However, if a bit pattern format indicating a free state that is not occupied by any processor is determined, the occupied bit 50 may not be provided.

Further, in the above embodiment, the common area 3 and the table 43 have a one-to-one address correspondence, but by adding a device that maps the common area 3 to the table 43, it is not necessary to have a one-to-one correspondence. .

Furthermore, in the above embodiment, when a processor goes down, the fail-safe processing device 60 refers to the table 43 and performs fail-safe processing on the common area corresponding to the down processor. However, in a multiprocessor system, the system status is monitored. If you have a device that does this, you can provide it with a fail-safe processing function in the event of a downtime.

Further, in the above embodiment, a case has been described in which the means for registering the output request processor number is automatically registered, but any means that can store the occupied processor number corresponding to the output data may be used. It is also possible to set it manually.

〔Effect of the invention〕

As described above, according to the present invention, when a processor goes down, the down processor is detected through the table of the common area management device, and the backup S/W and the special A multiprocessor system that can perform operations reliably without requiring extensive H/W can be obtained.

[Brief explanation of drawings]

1 and 2 are block diagrams showing conventional multiprocessor systems, FIG. 3 is a table format diagram of the common area management device shown in FIG. 2, and FIGS. 4 and 5 are block diagrams showing conventional multiprocessor systems, respectively. FIG. 6 is a block diagram showing a multiprocessor system according to an embodiment of the present invention. In the figure, 3 is a common area management device, 10A,
10B is a processor, 30A, 30B, 30C,
30D is a common area, 43 is a table, 60 is a fail-safe processing device, 61A and 61B are processor down signals, and 63 is a fail-safe processing signal. In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] 1. In a multiprocessor system configured with a plurality of processors, a common area management device shared by the plurality of processors, and one or more common areas accessible via the common area management device, the above-mentioned A means for registering an output request processor number in a table corresponding to addresses of the common area in the common area management device, and comparing the registered processor number with a processor number permitted to output in the common area management device to determine whether they match. and means for detecting the down processor through the table when the processor goes down, and causing fail-safe processing of the common area corresponding to the down processor. Features a multiprocessor system.