JPH02177737A - Multi-channel multi-frame receiving circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial application field (Figure 8) Prior art (Figures 6 and 7) Means for solving the problem to be solved by the invention (Figure 1) ) Effect (Fig. 1) Embodiment (Figs. 2 to 5) Effects of the invention [Summary] Regarding a multi-channel multi-frame receiving circuit that can independently synchronize multi-frames for multi-channels, control data storage is provided. By making the memory for multi-frame detection also serve as a shift register function.

The purpose is to prevent the circuit scale from increasing even when the circuit is converted to an LSI.

A memory capable of storing multiple sets of data from the serial/parallel converter, a register for reading the data stored in this memory, and a multi-frame frame included in the output of the serial/parallel converter provided on the writing side of the memory. It is equipped with a 1-bit shift circuit that can shift the detection data 1 bit at a time, and when detecting a multi-frame, the multi-frame detection data that is shifted 1 bit at a time and output from the 1-bit shift circuit is sequentially transferred to a specific address in the memory. By being configured to write
The memory is configured so that it also serves as a shift register for multi-frame detection.

[Industrial Application Field] The present invention relates to a multi-channel multi-frame receiving circuit that can independently synchronize multi-frames for multiple channels.

Generally, in data transmission, etc., multiple channels are multiplexed and transmitted, but the control data of the data to be transmitted needs to be synchronized at a slower rate than the data part such as information, so it is transmitted in a multi-frame configuration. This method is often adopted. For example, in the case of 12 multi-frames, as shown in Figure 8, one frame consists of 16 time slots, and each time slot of this frame contains information about odd or even channels. It will be done. Furthermore, each time slot is made up of 8 bits, 7 bits of these 8 bits contain control data, and the remaining 1 bit contains a synchronization bit Mx (x=a-ffi) of 1 or 0. Then, this synchronization pit becomes meaningful for 12 frames M a '' M 1 from the 1st frame (k is a natural number) to the 11th frame.By the way, in this case,
It is necessary to independently synchronize multiframes of multiple channels.

[Prior Art] Fig. 6 is a block diagram of a conventional multi-channel multi-frame receiving circuit. In Fig. 6, 1 is a serial/parallel converter; This converts serial data in which minute control data and multi-frame detection data are multiplexed into parallel data.

2'A, 2'B, 2'C are 2→1 selectors, and these selectors 2'A, 2'B, 2'C are connected in parallel to the serial/parallel converter 1, 1 at the A input terminal of each selector 2'A, 2'B, 2'C.
Parallel data for channels (in this case, for example, 1
Parallel data for each channel (consisting of 8 bits per time slot) is input. In addition, the B input terminal of each selector 2'A, 2'B, and 2'C has a read register (24-bit register) described later.
The output from 4 is input in 8-bit units. and,
Each selector 2'A, 2'B, 2'C is a state control circuit 9.
According to the instruction of the selector control signal from the selector control signal, when updating data, the data at the A input terminal is selected, and when data is to be retained, the data at the B input terminal is selected.

3 is a RAM (memory) for writing information bits, and this RAM 3 is used for each selector 2'A, 2'B.

A total of 24 bits of data from 2'C can be stored in N (plural numbers, for example, 16) sets.

4 is a read register, and this read register 4 is R
This is to read data stored in AM3, and this read data is sent to three selectors 2'A, 2'B, 2'
The data is input to the B input terminal of C as held data.

5 is a shift register for multi-frame detection, and this shift register 5 has shift register sections 51 for the number of time slots, and each shift register section 51 has 12 shift register sections.
It has a tiered structure. In addition, this shift register section 51
Select and output only one output of 16→】Selector 5
2 is provided on the output side of the shift register section 51.

6 is a 12 multi-frame detection section, and this 12 multi-frame detection section 6 is a shift register 5 for multi-frame detection.
This is to detect whether the synchronization bit string detected in is the required synchronization pattern.

7 is a synchronization/protection circuit, and this synchronization/protection circuit 7 is connected to 12
Even if the multi-frame detection unit 6 determines that the synchronization bit string is the required synchronization pattern, if it is not detected the required number of times, it will not be considered that synchronization has been achieved, thereby protecting synchronization detection. Enable circuit 7]
, , a counter 72, 16 consisting of 16 counter parts →
1 selector 73. Here, the enable circuit 71 has 16 time slots. The counter 7 corresponds to data for any one of the time slots.
The 16→1 selector 73 is for inputting to 2 parts.
One output is selected from among the outputs from the counter section 6.

8 is a time slot counter, and the signal from this time slot counter 8 is sent to the multi-frame detection shift register 5. Enable circuit 71 of synchronization/protection circuit 7
．． The signal is input to the selector 73, so that these circuits operate synchronously.

Further, 9 is a state control circuit, and this state control circuit 9 sends and receives various signals to and from the above-mentioned circuits. For example, from this state control circuit 9, selectors 2'A, 2'B, 2'
A selector control signal is supplied to C, and RA is supplied to RAM3.
The M address signal and the write control signal are supplied, the read control signal is input to the read register 4, and the 12 multi-frame counter increment signal is input to the enable circuit 71 of the synchronization/protection circuit 7. From the selector 7:3 of the 5 synchronization/protection circuit 7, the synchronous state flag, 12 multiphrase L norm counter value information, etc. are input to the state control circuit 9.

With this configuration, detection of whether or not synchronization is achieved from 12 multiframes is performed as follows. First, the multi-frame detection shift register 5 detects a synchronization bit string, and then the 12 multi-frame detection unit 6 determines whether this detected value is a desired synchronization pattern, and the synchronization/protection circuit 7 , if this is detected the required number of times, it is considered that synchronization has been achieved. Detection of such synchronization is performed independently for each channel.

Note that the control data is the selectors 2'A and 2'B.

It is stored in RAM3 via 2'C, but in this case,
The control data is for 3 frames (2 frames) as shown in Figure 7.
4 bits) are stored in RAMa in such a way that they can be associated with one memory address.

[Problems to be Solved by the Invention] However, in such a conventional multi-channel multi-frame receiving circuit, the RAM for storing control data is
In addition to 3, a shift register for multi-frame detection is required to store multi-framing pits for each channel. Therefore, when this receiving circuit is implemented as an LSI, there is a problem that the circuit scale increases.

The present invention has been made in view of these problems, and by making the memory for storing control data also serve as a shift register function for multi-frame detection, it is possible to prevent the circuit scale from increasing even when the circuit is integrated into an LSI. I made it. The purpose is to provide a multi-channel multi-frame receiving circuit.

[Means to solve the problem] FIG. 1 is a block diagram of the principle of the present invention.

In FIG. 1, 1 is a serial/parallel converter, and this serial/parallel converter 1 converts serial data in which control data for multiple channels and data for multi-frame detection are multiplexed into parallel data. be.

2 is a 1-bit shift circuit, and this 1-bit shift circuit 2
is provided on the write side of the memory 3 and can shift the multi-frame detection data included in the output of the serial/parallel converter 1 bit by bit.

Reference numeral 3 denotes a memory, which can store multiple sets of parallel data from the serial/parallel converter 1. When detecting a multi-frame, this memory 3 is used to shift data one bit at a time from the one-bit shift circuit 2. By being configured to sequentially write the outputted multi-frame detection data into specific addresses of the memory 3, it also serves as a shift register for multi-frame detection.

4 is a read register, and this read register 4 is for reading data stored in the memory 3.

Reference numeral 11 denotes a multi-frame detection section, and this multi-frame detection section 11 detects whether the synchronization bit group read out from the memory 3 via the read register 4 is a required synchronization pattern.

[Operation] With the above configuration, during multi-frame detection,
The multi-frame detection data that is shifted one bit at a time and output from the one-bit shift circuit 2 is stored in the memory 3. By sequentially writing to specific addresses of memory 3
functions as a shift register and stores the required number of frames of multi-frame detection data stored in a plurality of frames in the memory 3. This stored data is read out by the read register 4, and then sent to the multi-frame detection section. In step 11, this read data and the reference pattern are compared, and if they match, it is determined that a synchronized state has been reached.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention, and the multi-channel multi-frame receiving circuit shown in FIG. 2 includes serial/parallel converters 1. Selector 2A, 2B, 2C
, RAM (memory) for writing information bits3. Read register 41 synchronization/protection circuit 7. Time slot counter8. State control circuit 9. It is comprised of a register section 10.12 for synchronization bit detection, and a multi-frame detection section 11.12.

Here, serial/parallel converter 1. Read register 4. Synchronization/protection circuit 7. The time slot counter 8 is almost the same as the conventional one, so a description thereof will be omitted.

By the way, the selectors 2A, 2B, and 2C are connected in parallel to the serial/parallel converter 1, as shown in FIG. The selector 2C is configured as a 2→1 selector with A, 82 input terminals, and each selector 2A, 2
One channel's worth of parallel data (in this case, for example, one channel's worth of parallel data is composed of 8 bits per time slot) is input to the A input terminals of B and 2C, and each selector 2A.

Eight bits of output from a read register (24-bit register) 4, which will be described later, is input to the C input terminals of 2B and 2C, respectively.

In addition, the B input terminal of the selector 2A has a synchronization bit Mx (
x=a-1) is input, and 0 to 6 bit data from the read register 4 is input for the remaining 7 bits.

The 7 to 10 bit data from the read register 4 is input to the B input terminal of the selector 2B in the first four bits, and the remaining four bits are at the 0 level. As a result, input lines for a total of 12 bits exist at each B input terminal of the selectors 2A and 2B. Therefore, when the B inputs of selectors 2A and 2B are selected, the output from read register 4 can be shifted by 1 bit and written to the desired address of RAM3, and this allows these selectors 2A and 2B to select the write side of RAM3. A 1-bit shift circuit is provided in which the multi-frame detection data M included in the output of the serial/parallel converter 1 can be shifted one bit at a time.

Note that each selector 2A, 2B, 2C is connected to a state control circuit 9.
To update the data, select the data at the C input terminal according to the instructions of the selector control signal from the C input terminal, to retain the data, select the data at the C input terminal, and to detect multi-frame detection data. selects the data at the B input terminal.

In addition, the RAM 3 stores a total of 24 bits of data from each selector 2A, 2B, and 2C to a required address (N (plural,
For example, 16) sets can be stored.

Furthermore, the read register 4 reads out data stored in the RAM 3, and this read data is input to the B and C input terminals of the three selectors 2A, 2B, and 2C as described above. .

The register unit 10 for synchronization bit detection consists of three 3-bit registers 101, 102, and 103, and each of the 3-bit registers 101, 102, and 103 has a RAM3.
The 612 multi-frame detection unit 11 receives the output of the 7, 15, and 23rd bits (respectively synchronous bit information output) and detects the synchronous bit in the RAM 3 via the read register 4. The 12 multi-frame detection unit 12 detects whether the synchronization bit string detected is a required synchronization pattern.
This is to detect whether the composite pattern of the nine synchronization bit strings detected at 0 and the three synchronization bit strings from the read register 4 is a desired synchronization pattern.

Further, the state control circuit 9 sends and receives various signals to and from the above-mentioned circuits.1 For example, selector control signals are supplied from the state control circuit 9 to the selectors 2A, 2B, and 2G, and the RAM 3 is supplied with a selector control signal. Address signals and write control signals are provided.

A read control signal is input to the read register 4,
The 12 multi-frame counter increment signal is input to the enable circuit 71 of the synchronization/protection circuit 7, and the synchronization state flag, 12 multi-frame counter value information, etc. are input from the selector 73 of the synchronization/protection circuit 7. A register write signal is input to the state control circuit 9, and a register write signal is input to the register unit 10 for detecting a synchronization bit.

With the above configuration, detection of whether synchronization is achieved from 12 multiframes is performed as follows. First, during multi-frame punting (out of synchronization), the B inputs of selectors 2A, 2B, and 2C are selected for each received data, and by combining it with the old data stored in the read register 4, the result is Shift the synchronization bit by one bit. As a result, RAMa contains 12 synchronization bits Ma to M1, as shown in FIG.
is stored at a specific memory address. This is grinning, R
AM3 when detecting multi-frames.

The multi-frame detection data that is shifted one bit at a time and outputted from the selectors 2A and 2B that constitute the one-bit shift circuit is configured to be sequentially written to a specific address of the RAM 3, and as a result, this RAM
M3 has a shift register function for multi-frame detection.

Thereafter, this synchronous bit string is sent to the 12 multi-frame detection unit 11 via the read register 4, and the 12
The multi-frame detection unit 11 determines whether this detected value is a required synchronization pattern, and the synchronization/protection circuit 7
When this is detected the required number of times, synchronization is considered to be completed. Note that such synchronization detection is performed independently for each channel.

When synchronization is achieved in this way, the synchronization flag is turned on and the operation of the 12 multi-frame counter is started. Thereafter, synchronization is established based on the counter value of this counter. Furthermore, in this synchronous mode, the selector stops selecting the B input and selects the A input or C input.

As a result, the control data is transmitted to the selectors 2A and 2B.

In this case, the control data is stored in the RAM 3 via the 2C, so that three frames (24 bits) can be associated with one memory address, as shown in FIG. It is stored in RAMa.

Also, at this time, the register section 1o for detecting synchronizing bits always detects the synchronizing bits from the output of the RAM 3, and the nine synchronizing bit strings detected by the register section 10 for detecting synchronizing bits are read out from the read register 4. 12 multi-frame detectors 12
It is detected whether this detected synchronization bit pattern is the desired synchronization pattern. If the synchronization is out of order the required number of times, the synchronization state flag is turned off in the synchronization/protection circuit 7, and the state control circuit 9 then sends a signal to the selectors 2A and 2B to select the B input, and starts multi-frame hunting again. Return to mode. This allows R.A.
M3 once again performs the multi-frame detection shift register function, and the synchronous bit string is detected.

In this multi-channel multi-frame receiving circuit, since the RAM 3 also serves as a shift register for multi-frame detection, there is no need for a conventional large-capacity shift register for multi-frame detection. Even if it is made into an LSI, the circuit scale can be small.

Note that, as a multi-frame detection method, in addition to performing synchronization detection using 12 frames as 1ffi, it is also possible to perform synchronization detection using 5 or any other number of frames as a set.

[Effects of the Invention] As described in detail above, according to the multi-channel multi-frame receiving circuit of the present invention, the memory capable of storing a plurality of sets of parallel data from the serial/parallel converter receives one bit when detecting a multi-frame. The multi-frame detection data is shifted bit by bit from the shift circuit and output.
By sequentially writing data to specific addresses in this memory, it also serves as a shift register for multi-frame detection, eliminating the need for a conventional large-capacity shift register for multi-frame detection. ,
This has the advantage that even when this receiving circuit is implemented as an LSI, the scale of the five circuits can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention. FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a block diagram showing the configuration around the RAM. Figure 4 is a diagram explaining the RAM storage format in normal mode, Figure 5 is a diagram explaining the RAM storage format in multi-frame hunting mode.
6 is a block diagram illustrating a conventional example; FIG. 7 is a diagram illustrating a RAM storage format in the conventional example; and FIG. 8 is a diagram illustrating 12 multi-frames. In the figure, 1 is a serial/parallel converter, 2 is a 1-bit shift circuit, 2A, 2B, 2. C is a selector, 3 is RAM (memory), 4 is a read register, 7 is a synchronization/protection circuit, 8 is a time slot counter, 9 is a state control circuit, 10 is a register section for detecting synchronization bits, 11.12 is 1
2 multi-frame detection sections, 71 is an enable circuit, 72 is a counter, 73 is a selector, and 101 to 103 are 3-bit registers. Block diagram of Tsuki Uri of the cursed moon Figure 1 Figure 12 Maruna frame begging diagram Figure 8

Claims (1)

[Claims] A serial/parallel converter (1) that converts serial data in which multi-channel control data and multi-frame detection data are multiplexed into parallel data; and from the serial/parallel converter (1). a memory (3) capable of storing multiple sets of parallel data;
A read register (4) is provided for reading data stored in the memory (3), and one bit of multi-frame detection data included in the output of the serial/parallel converter (1) is provided on the writing side of the memory (3). A 1-bit shift circuit (2; 2A, 2B) capable of shifting the 1-bit shift circuit (2; 2A, 2B) is provided.
The multi-frame detection data that is shifted bit by bit and output is sequentially written to a specific address of the memory (3).
) doubles as a shift register for multi-frame detection.