JPH02177360A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To decrease the difference in the sensing rate between sense amplifiers without enlarging the chip size by a method wherein sense amplifiers are driven by power supplying and GND wiring through the intermediary of multiple drivers while driving wirings are arranged on cell arrays. CONSTITUTION:The P channel transistor side terminals of sense amplifiers S1-Sn connected to one another are further connected to multiple P channel drivers P1-Px through the intermediary of wirings L1-Lk passing through memory cells (b). Likewise, the N channel transistor side terminals are connected to multiple N channel drivers N1-Nk. When a signal in a cell is given to a bit wire, sense signals phiSE and phiSE are displayed respectively at high and low levels so as to actuate respective drivers. At this time, the amplifiers S1-Sn are supplied with current through the wirings L1-Lk and M1-Mk so that the terminal potentials of the same amplifiers S1-Sn may be equalized by shortening the intervals between wirings. Through these procedures, the sensing rate can be equalized to make the optimum setting up of the sense amplifiers feasible.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory, and in particular to a dynamic RAM.
Regarding the wiring layout.

[Conventional technology] Conventional dynamic RA? As an example of 'v'I, the circuit diagram of the IDRAM sense amplifier and its surroundings is shown in 1.
It is shown in the figure and will be explained using this figure. In IMDRAM, 2048 bits of cells must be refreshed at a time, so 2048 sense amplifiers are lined up along one word line. Terminals A1 to A of the sense amplifier array arranged along one side of the memory cell array
2048 and terminals 1 to B2048 are connected to a P-channel driver and an N-channel driver, respectively, at one end of the cell array by driver wiring.

After the signal appears in the sense amplifier, the sense signal φSE becomes high level and φ becomes low level, and the sense amplifier starts operating. At this time, since 2048 sense amplifiers operate simultaneously, a large amount of current flows through the driver wiring, and the potential difference between Al-B1 open, which is far from the drive transistor, becomes smaller than the potential difference between A2048 and B2048, which is close to the drive transistor. . The width of the driver wiring is 20μ, the length is 16mm, and the layer resistance of A'2 is 0. 0
If it is 25Ω/mouth, the wiring resistance will be 20Ω and 50nI.
The peak current of A is 1V at a time, a total of 2V difference between the far end and the near end, and the sensing speed of sense amplifier S1 is the same as sense amplifier 3.
This will be considerably delayed compared to 2048.

[Problems to be Solved by the Invention] In the conventional dynamic RAM described above, as the capacity increases, the number of cells connected to one word line increases.
The resistance from the driver to the far end of the sense amplifier array cannot be ignored. When the sense amplifier is driven in this state, a large current flows through the driver wiring, and the electric current at the drive terminal of the sense amplifier differs greatly at both ends of the sense amplifier array.
As the sensing speed increases, the sensing sensitivity deteriorates, and the sensing speed decreases in the sense amplifier at the far end of the driver.
This will delay overall access. For this reason, it has been difficult to create an optimal design for all sense amplifiers.

If you try to lower the resistance by increasing the width of the driver wiring inside the sense amplifier, the sense amplifier itself will become larger than necessary to secure the wiring area, and the parasitic resistance of the wiring inside the sense amplifier that is perpendicular to the driver wiring will increase. However, if the diffusion layer of the sense amplifier is made larger, the capacitance of the diffusion layer connected to the bit lines Z and l will increase and the CB/C9
This has the disadvantage that it worsens. If you try to shorten the wiring length, increase the division of the cell array, and reduce the resistance between the sense amplifier and the driver, the chip size will increase.

[Differences between the invention and the prior art] In contrast to the above-mentioned conventional dynamic RAM, the present invention drives a sense amplifier from the power supply stage UGND via a plurality of drivers, and arranges the drive wiring above the cell array. There is.

[Means for solving the problem] The semiconductor memory of the present invention includes memory cells divided into a plurality of groups, a plurality of sense amplifiers connectable to each of the plurality of groups of memory cells, and a plurality of sense amplifiers connected to the plurality of sense amplifiers. In a semiconductor memory including a common drive signal line for supplying current, a plurality of drive transistors are connected in parallel to the common drive signal line, and the drive transistors are connected to a power supply wiring.

Therefore, in the semiconductor memory of the present invention, the wiring connecting the sense amplifier from the power supply and GND via the driver is connected by a sufficiently thick wiring around the chip and a plurality of wirings from the chip periphery passing over the cell array to the sense amplifier. Therefore, the resistance between the power supply and GND and the sense amplifiers is almost constant within the sense amplifier array, and the difference in sensing speed between the sense amplifiers is extremely small.

[Embodiment] FIG. 1(a) is a circuit diagram of a first embodiment of the present invention. Further, FIG. 1(b) is a circuit diagram of a sense amplifier used in the present invention. The P-channel transistor side terminals of each sense amplifier 51-Sn are connected to each other and connected to a plurality of P-channel drivers P1-Pk on the opposite side of the memory cell array via wiring lines L1-L1< passing over the memory cells. has been done.

Similarly, the terminals on the N-channel transistor side of each sense amplifier S1 to Sn are connected to the plurality of N-channel drivers N1 on the opposite side of the memory cell array via wiring N1 to N1.
~N Connected to R.

After the signal in the cell appears on the bit line, the sense signal φSE goes high and φSE goes low, and each driver enters the operating state. At this time, sense amplifier 81~S rl
Since the current is supplied through the wirings L] to LJ(and M1 to M1.
The sense amplifier has almost the same potential, and there is almost no difference in sensing speed.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

81 to Sn are sense amplifiers shown in FIG. 1(b). 2 in dynamic RAM where the bit line is multi-divided.
In a sense amplifier array sandwiched between two memory cell arrays, a plurality of P-channel drivers P1 to P are connected to mutually connected terminals on the P-channel transistor side and terminals on the mutually connected N-channel transistor side, respectively.
k and N channel drivers N1 to Nlkc are connected.

A plurality of power supply wirings and GND wirings pass over a plurality of cell arrays in a direction along the bit lines, and these wirings are connected to P channel drivers P1 to Pk and N channel drivers N1 to Nk, respectively. .

[Effects of the Invention] As explained above, the present invention allows all or part of the wiring between the power supply, GND and sense amplifier to be placed on the array.
2 reduces the difference in sensing speed between the sense amplifiers without increasing the chip size, making it possible to optimally design the sense operation for all sense amplifiers.

[Brief explanation of the drawing]

FIG. 1(a) is a circuit diagram of the first embodiment of the present invention, FIG.
b) is a circuit diagram of a sense amplifier used in an embodiment of the present invention;
FIG. 2 is a circuit diagram of a second embodiment of the present invention, and FIG. 3 is a circuit diagram of a sense amplifier and its surroundings of a conventional IM DRAM. S1~Sn......Sense amplifier, P1~
P 1 (...P channel driver N1~N
R...N channel driver L]~L1(
. M1~Mk...Driver wiring.

Claims (1)

[Claims] A semiconductor memory including memory cells divided into a plurality of groups, a plurality of sense amplifiers connectable to each of the plurality of groups of memory cells, and a common drive signal line that supplies current to the plurality of sense amplifiers, A semiconductor memory characterized in that a plurality of drive transistors are connected in parallel to the common drive signal line, and the drive transistors are connected to a power supply wiring.