JPH02176570A - Probe card - Google Patents
Probe cardInfo
- Publication number
- JPH02176570A JPH02176570A JP33113188A JP33113188A JPH02176570A JP H02176570 A JPH02176570 A JP H02176570A JP 33113188 A JP33113188 A JP 33113188A JP 33113188 A JP33113188 A JP 33113188A JP H02176570 A JPH02176570 A JP H02176570A
- Authority
- JP
- Japan
- Prior art keywords
- probe card
- bumps
- electrode
- semiconductor wafer
- probe
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000523 sample Substances 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 238000012360 testing method Methods 0.000 claims abstract description 12
- 230000002093 peripheral effect Effects 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 14
- 238000000034 method Methods 0.000 description 6
- 239000011111 cardboard Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Measuring Leads Or Probes (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はプローブカードに関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a probe card.
半導体装置の製造工程中には、いわゆるウェーハ処理工
程を完成した後、シリコンウェーハ上の個々のチップが
所期の電気的特性を有するか否かを測定する工程があシ
、チップと測定器との接続はチップの電極へプローブカ
ードのグローブを接触することによシ得ている。During the manufacturing process of semiconductor devices, after completing the so-called wafer processing process, there is a process to measure whether each chip on the silicon wafer has the desired electrical characteristics. Connections are obtained by contacting the probe card's globe to the chip's electrodes.
第2図は従来のプローブカードの一例と被試験半導体ウ
ェーハの断面図である。FIG. 2 is a cross-sectional view of an example of a conventional probe card and a semiconductor wafer under test.
プローブカードは、プローブカード基板lにプローブ支
持板2を介してグローブ3A及び3Bをそれぞれ保持し
ている。The probe card holds gloves 3A and 3B on a probe card board 1 via a probe support plate 2, respectively.
グローブ3人及び3Bはそれぞれの先端に凸部4人及び
4Bを有し、被試験半導体ウェーハ5上の所定の電極バ
ラ)6a及び6bの表面の中央部に凸部4人及び4Bを
接触させて電気特性を試験している。The gloves 3 and 3B have convex portions 4 and 4B at their respective tips, and the convex portions 4 and 4B are brought into contact with the central portions of the surfaces of predetermined electrodes 6a and 6b on the semiconductor wafer under test 5. The electrical characteristics are tested using
上述した従来のプローブカードでは、プローブの先端部
が棒状になっており、近年、半導体装置のアセンブリ一
方式として多く用いられるTAB方式において、チップ
上のバンプ構造の突起状の電極に接着する際、電極の中
央部を圧力によシへこませて損傷してしまうという欠点
を有していた。In the conventional probe card described above, the tip of the probe is rod-shaped, and in the TAB method, which is often used in recent years as a one-way assembly method for semiconductor devices, when bonding to the protruding electrode of the bump structure on the chip, This method has the disadvantage that the central part of the electrode is dented and damaged by pressure.
すなわち第2図に示すように、プローブ3Aの凸部4A
が電極6aに接着する際、圧力のために電極6aの表面
にめシ込む形となシ、電極6aに凹みの損傷を発生させ
てしまうことがある。That is, as shown in FIG. 2, the protrusion 4A of the probe 3A
When bonding to the electrode 6a, the pressure may cause the electrode to be indented into the surface of the electrode 6a, causing damage to the electrode 6a.
この損傷した電極は、後工程のアセンブリー工程でTA
BIJ−ドと接着する際に接着面積の低下に関連し、半
導体装置の製造工程歩留シや出荷後の信頼度の低下の原
因となることがある。This damaged electrode will be removed by TA in the subsequent assembly process.
When adhering to the BIJ-board, the adhesion area is reduced, which may cause a reduction in the manufacturing process yield of the semiconductor device and the reliability after shipment.
本発明の目的は、半導体ウェーノ・の電極の損傷させな
いプローブカードを提供することにある。An object of the present invention is to provide a probe card that does not damage the electrodes of a semiconductor wafer.
本発明のグローブカードは、先端部を被試験半導体ウェ
ーハ上の電極パッドに接触させるプローブを用いて前記
被試験半導体ウェーハの電気的特性を試験するプローブ
カードにおいて、前記先端部が前記電極部を挿入する凹
部を有して構成されている。The globe card of the present invention is a probe card for testing the electrical characteristics of a semiconductor wafer under test using a probe whose tip is brought into contact with an electrode pad on the semiconductor wafer under test, wherein the tip is inserted into the electrode pad of the semiconductor wafer under test. It is configured to have a recessed portion.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例と被試験半導体ウェーハの断
面図である。FIG. 1 is a sectional view of an embodiment of the present invention and a semiconductor wafer to be tested.
プローブカードは、グローブ3a及び3bのそれぞれの
先端が第2図の凸部4A及び4Bの代りに凹部4a及び
4bを有することが異る点板外は従来のプローブカード
と同一である。The probe card is the same as the conventional probe card except for the point plate, except that the respective tips of the globes 3a and 3b have concave portions 4a and 4b instead of the convex portions 4A and 4B in FIG. 2.
J
プローブ3a及び3bの先端lバンプ6aの周縁よυも
一回9大きい筒状の凹部4a及び4bを有している。J The tips of the probes 3a and 3b have cylindrical recesses 4a and 4b that are 9 times larger than the circumferential edge of the bump 6a.
試験をするためにプローブカード基板lを半導体ウェー
ハ5に近づけると、グローブ3a+3bの凹部4aはバ
ンプ6a+6bに被参雲た状態となる。When the probe card board 1 is brought close to the semiconductor wafer 5 for testing, the recesses 4a of the globes 3a+3b are brought into contact with the bumps 6a+6b.
更に凹部4a+4bの内側はテーバが設けられているの
で、プローブ3a+3bとバング6a6bが圧着される
に従い、バンプba s 6b ノ周縁部が凹部内部と
良好な導通を得ることができる。Furthermore, since a taper is provided on the inside of the recess 4a+4b, as the probe 3a+3b and the bang 6a6b are crimped together, the peripheral edge of the bump ba s 6b can obtain good electrical conduction with the inside of the recess.
従ってバンプ表面の中央に損傷を与えることはない。Therefore, no damage is caused to the center of the bump surface.
上述の実施例で、グローブ3a及び3bは先端部のみを
筒状の凹部としたが、プローブの全体を筒状、即ち中空
部にしてもよい。In the above-described embodiment, only the tips of the globes 3a and 3b have a cylindrical recess, but the entire probe may be cylindrical, that is, hollow.
その場合はグローブ支持板2の方向から真空に引き、こ
の真空による吸引力によってプローブとバンブとの接着
力を高めてよシ導辿を得やすいという利点がある。In this case, a vacuum is drawn from the direction of the glove support plate 2, and the suction force generated by the vacuum increases the adhesive force between the probe and the bump, making it easier to obtain a better guide.
以上説明したように本発明は、プローブの先浴部が被試
験半導体ウェーハの電極を挿入して内部接触する四部を
有するので、良好な導通を得ると共に、電極中央部がプ
ローブにより損傷されないという効果がある。As explained above, the present invention has the advantage that the pre-bath part of the probe has four parts into which the electrode of the semiconductor wafer under test is inserted and makes internal contact, so that good conduction is obtained and the central part of the electrode is not damaged by the probe. There is.
5伝試験半青休つJ−ハ 粛 1 品5th Den Exam Half Blue Rest J-Ha 1 item
第1図は本発明の一実施例と被試験半導体ウェーハの断
面図、第2図は従来のグローブカードの一例と被試験半
導体ウェーハの断面図である。
l・・・・・・グローブカード基板、3Bm3b”“′
°°プローブ、4a+4b・・・・・・凹部、5・・・
・・・被試験半導体ウェーハ 6a 、6b・・・・・
・バンブ。
弔 z 品
代理人 弁理士 内 原 晋FIG. 1 is a sectional view of an embodiment of the present invention and a semiconductor wafer to be tested, and FIG. 2 is a sectional view of an example of a conventional glove card and a semiconductor wafer to be tested. l...Glove card board, 3Bm3b""'
°°probe, 4a+4b... recess, 5...
...Semiconductor wafers under test 6a, 6b...
・Bambbu. Condolences Representative Patent Attorney Susumu Uchihara
Claims (1)
ローブを用いて前記被試験半導体ウェーハの電気的特性
を試験するプローブカードにおいて、前記先端部が前記
電極を挿入する凹部を有することを特徴とするプローブ
カード。A probe card for testing the electrical characteristics of a semiconductor wafer to be tested using a probe whose tip portion contacts an electrode on the semiconductor wafer under test, characterized in that the tip portion has a recess into which the electrode is inserted. probe card.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33113188A JPH02176570A (en) | 1988-12-28 | 1988-12-28 | Probe card |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33113188A JPH02176570A (en) | 1988-12-28 | 1988-12-28 | Probe card |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02176570A true JPH02176570A (en) | 1990-07-09 |
Family
ID=18240215
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP33113188A Pending JPH02176570A (en) | 1988-12-28 | 1988-12-28 | Probe card |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02176570A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06203926A (en) * | 1992-12-25 | 1994-07-22 | Yamaichi Electron Co Ltd | Ic socket |
US6680536B2 (en) | 2001-03-28 | 2004-01-20 | Yamaha Corporation | Probe unit having resilient metal leads |
-
1988
- 1988-12-28 JP JP33113188A patent/JPH02176570A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06203926A (en) * | 1992-12-25 | 1994-07-22 | Yamaichi Electron Co Ltd | Ic socket |
JPH0677467B2 (en) * | 1992-12-25 | 1994-09-28 | 山一電機株式会社 | IC socket |
US6680536B2 (en) | 2001-03-28 | 2004-01-20 | Yamaha Corporation | Probe unit having resilient metal leads |
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