JPH0217551A - Memory access processing device - Google Patents

Abstract

PURPOSE:To initialize the cache memory of an arithmetic unit with a small amount of hardware by providing a memory access processing device with an initialization request generating means. CONSTITUTION:An initializing signal and an address to the cache memory of an arithmetic processing device 201 are generated in an initializing request generating means 35 repeatedly in accordance with a required number of blocks and are selected by selecting circuits 36 and 37 and pass a bus 38 of cache coincidence processing request and are inputted to the arithmetic processing device 201. They are selected by a selecting circuit 221 in the arithmetic processing device 201 and are sent to an address array 241 to perform initialization by the same operation as cache coincidence processing. The initializing request signal is sent repeatedly until all of effective bits of the address array which hold address information and effective states of a corresponding data array are invalidated, thus initializing the cache memory.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data array that holds a copy of a portion of a storage device, and the address information and valid state of the corresponding data array on the main storage device. connected to an arithmetic processing device having a cache memory having an address array to hold, an input/output processing device, and a main storage device, and performs memory access processing in response to memory access requests from the arithmetic processing device and the input/output processing device; The present invention relates to a memory access processing device having a cache matching processing stage for rows f and i for the cache matching processing of the arithmetic processing device.

[Prior Art] A cache memory is composed of a pair of address array and data array, and the address array and data array are connected to RA.
Since it is composed of M, it is necessary to initialize it.

This initialization can be done by invalidating all the address information of the corresponding data array and the valid bits of the address array that hold the valid state.

Conventionally, this cache memory has been initialized by an initialization signal generated by initialization request generation means arranged one in each arithmetic unit.

FIG. 2 is a block diagram of a conventional example of an information processing system including an arithmetic processing unit, a memory access processing unit, a main storage device, and an input/output processing unit.

This information processing system includes input/output processing devices 10, . 10
2, and an arithmetic processing device 50. ．． 50□, a memory access processing device 60, and a main storage device 40.

Arithmetic processing unit 50. (502) includes an input circuit 211 (212) that accepts memory access requests from an instruction fetching circuit or an arithmetic processing circuit (not shown), and an initialization request generating means 25. (252) and data array 23, (23□)
, address array 241 (242), and input circuit 21
．． (212), the initialization request generation means 25, the valid bit invalidation signal from (252), and the cache matching processing result from the cache matching processing circuit 33 (34), which will be described later, are selected and output to the address array 241 (242). The selection circuit 221 (222) is entered. The memory access processing device 60 includes a memory access processing circuit 32 that processes memory access requests to the main storage device 40, and an arithmetic processing device 50. A cache memory matching processing circuit 33 having a copy of the address array 241 of the cache memory of the arithmetic processing unit 501 and a cache memory having a copy of the address array 242 of the cache memory of the arithmetic processing unit 50 A coincidence processing circuit 34 and an input/output processing device 10. , 10□ and an arithmetic processing unit 50. ．． The selection circuit 31 selects a request from 50□. Each arithmetic processing unit 501 (50
□) Initialization of the cache memory is performed by each arithmetic processing unit 5.
0. Initialization request generation means 251 (25) located at (50□)
2) The address array 24 of the cache memory is generated by the initialization signal which is generated by the select circuit 221 (222)
+ (242) by invalidating all valid bits. In addition, the cache memory matching process of the arithmetic processing unit 50 + (502) first involves the cache matching process of the memory access processing unit 60, since when writing is performed to the main storage device 40, the copy of that memory loses its latestness. In the circuit 33 (34), the arithmetic processing unit 501 (5
02) determines whether or not the address exists in the cache memory, and if the address exists, the arithmetic processing unit 50
．． Address array 24 to cache memory of (50□)
+ (242) by sending a signal to clear the valid bit and clearing the corresponding cache block.

[Lesson 2 that the invention attempts to solve! ! ] The conventional cache memory initialization method of the arithmetic processing unit described above is performed by a signal generated by the initialization request generation means in each arithmetic processing unit, so initialization request generation means for the number of arithmetic processing units are required. The amount of hardware increases,
The disadvantage is that the cost also increases.

[Means for Solving the Problems] A memory access processing device of the present invention includes an initialization request generation unit that generates address information and an initialization request for initializing a cache in an arithmetic processing unit, and It has selection means for selecting either the initialization request from the request generating means or the cache matching processing request from the cache matching processing means and sending the selected one to the arithmetic processing unit.

[Operation] By providing the initialization request generation means in the memory access processing device, the amount of hardware is reduced.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an information processing system including an embodiment of the memory access processing device of the present invention.

This information processing system has input/output devices 101.10□,
Arithmetic processing unit 20. ．． 202, a memory access processing device 30, and a main storage device 40.

The arithmetic processing unit 20r (202) receives an initialization request from the conventional arithmetic processing unit 501 (502) at the T stage 25. (2
52) is excluded. The memory access processing device 30 includes initialization request generation means for generating initialization signals and addresses for the number of blocks required to initialize the cache memories of the arithmetic processing units 20+ and 202 in the conventional memory access processing device 60. 35, and selection circuits 36 and 37 for selecting signals from cache coincidence processing circuits 33 and 34 are added.

Next, the operation of this embodiment will be explained.

Arithmetic processing unit 20. The initialization signal and address to the cache memory (202) are repeatedly generated in the initialization request generation means 35 for the required number of blocks, and the selection circuit 36.
Path 3B (3
9) and the arithmetic processing unit 20. It is input to (20□). Then, it is selected by the selection circuit 22.1 (222) in the arithmetic processing unit 20 (202), and the address array 2
41 (242), and initialization is performed in the same manner as the cache matching process. The difference between cache initialization and cache matching processing within the processing unit is that the 01 method invalidates all blocks, while the latter only invalidates blocks that have lost their currency, and the hardware They are essentially the same. The initialization request signal is repeatedly sent until the address information of the corresponding data array and the valid bits of the address array holding the valid state are all invalidated, and the cache memory is initialized.

[Effects of the Invention] As explained above, the present invention provides the initialization request generation means in the memory access processing device and uses the cache memory matching processing path, thereby reducing the hardware Mt and thus the cost. It has a decreasing effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an information processing system including an embodiment of the memory access processing device of the present invention, and FIG. 2 is a block diagram of an information processing system including a conventional example of the memory access processing device. 10,. 10□...I/O processing device, 20, . 202
...Arithmetic processing device, 21,. 212...input circuit, 22,. 222...Selection circuit, 231.232...Data array, 24I, 242...Address array, 30-...Memory access processing device, 31.36.37...Selection circuit, 32...Memory Access processing circuit, 33.34...Cache matching processing circuit, 35-...
Initialization request generation means, 38.39--path of cache matching processing request, 40
...Main memory.

Claims (1)

[Claims] 1. An arithmetic processing unit having a cache memory having a data array that holds a copy of a part of the main memory and an address array that holds the address information and valid state of the corresponding data array on the main memory. Cache matching processing means connected to the output processing device and the main storage device, for performing memory access processing in response to memory access requests from the processing processing device and the input/output processing device, and for performing cache matching processing for the processing processing device. In a memory access processing device having: an initialization request generation means for generating address information and an initialization request for initializing a cache in the arithmetic processing device; and an initialization request from the initialization request generation means; A memory access processing device characterized by comprising: selection means for selecting one of the cache matching processing requests from the cache matching processing means and sending the selected one to an arithmetic processing unit.