JPH02172221A - Manufacture of semiconductor substrate - Google Patents

Abstract

PURPOSE:To reduce the number of processes for forming a metal bump by a method wherein the wiring layer and diffused layer of a device are formed on a semiconductor substrate and an insulating film is formed on the wiring layer or diffused layer and, after a through-hole reaching the surface of the wiring layer is formed in the insulating film, the through-hole is selectively filled with metal and then the insulating film is selectively etched. CONSTITUTION:A device layer 12 is formed on a silicon substrate 11 and, after the device layer 12 is covered with a passivation film 13, a contact hole 15 is formed and, further, a wiring layer 14 is formed. After an SiO2 film 16 is formed, a through-hole 17 is formed in the SiO2 film 16 and filled with metal 18 by a metal CVD method. After that, a part of or the whole SiO2 film 16 is selectively removed by dry etching in a reactive gas atmosphere to form a tungsten bump 19 on the wiring. With this constitution, as a planting electrode forming process and an electrode removing process after planting are not included, the number of processes necessary for forming the metal bump 19 can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor substrate, and more particularly to a method for manufacturing metal bumps on a semiconductor substrate.

(Prior art) As a method for manufacturing metal bumps, a conventional electrolytic plating method is widely known (for example, Japanese Patent Laid-Open No. 58-19
Publication No. 7857). FIG. 3 is a process sectional view outlining the method for manufacturing metal bumps by the electrolytic plating method.

In order to simplify the explanation, a description of the process of forming a device such as a MOSFET on a semiconductor substrate will be omitted here. In FIG. 3, 41 is a silicon substrate;
2 is a device layer formed on the surface of this silicon substrate 41. 43 is a passivation film, 44 is a wiring layer, and 45 is a first contact hole formed between the device layer 42 and the wiring layer 44. 46 is an electrode layer for electrolytic plating, and 47 is a resist formed on the electrode layer 46. 48 is a through hole formed in the resist 47, 49 is a buried metal formed by electrolytic plating, and 50 is a metal bump. 51
is a SiO□ film formed on the wiring layer 44, and 52
is the second contact hole formed in the 5i02 film. First, a device layer 42 is formed on a semiconductor substrate 41 using a normal LSI manufacturing process. (Figure 3(a)
). After that, a passivation film 43 is formed on the device layer 42.
After forming the contact hole 45, the wiring layer 44 is covered with
After forming the 5i02 film 51, the 5i02 film 51 is formed.
A second contact hole 52 is formed in the i02 film 51 (FIG. 3(b)). Thereafter, an electrode metal 46 for electrolytic plating, such as Cu, is formed on the entire surface of the substrate by vapor deposition or sputtering, and then a resist 47 is applied.
Furthermore, a through hole 48 is formed (FIG. 3(C)).

Thereafter, the entire board is immersed in a plating solution, and electrolytic plating is performed using the plating electrode 46 as a cathode.
A metal 49, for example, Ni, is embedded in the (Fig. 3(d)
). Next, the resist 48 is removed by 02 plasma treatment or the like, and the plating electrode 46 is further removed using a selective etching solution, thereby forming a metal bump 50 (FIG. 3(e)).

(Problems to be Solved by the Invention) However, the method for manufacturing metal bumps using the electrolytic plating method described above includes the step of (1) immersing the semiconductor substrate in the plating solution. The semiconductor substrate is contaminated by alkali metal ions such as Na and K and anions such as SO. This has the disadvantage of requiring a large number of steps.

(Means for Solving the Problems) The present invention has been made in view of the above points, and includes a step of forming an insulating film on a wiring layer or a diffusion layer of a device formed on a semiconductor substrate, and a step of forming an insulating film on a wiring layer or a diffusion layer of a device formed on a semiconductor substrate. A step of forming a through hole in the film leading to the surface of the wiring layer, a step of selectively filling the through hole with metal by metal CVD, and a step of selectively etching the insulating film to form a through hole on the wiring layer or the surface of the wiring layer. It is characterized by forming metal bumps on the diffusion layer.

(Function) Since the method for manufacturing metal bumps according to the present invention described above does not include an electrolytic plating process, there is no concern that the semiconductor substrate will be contaminated by metal ions and the like present in the plating solution, which has been a problem in the past. Furthermore, since the method does not include a step of forming electrodes for plating and a step of removing electrodes after completion of plating, it is possible to reduce the number of manufacturing steps required for forming metal bumps.

(Example) Embodiments of the present invention will be described in detail below with reference to the drawings.

(Example 1) FIGS. 1(a) to 1(d) are process cross-sectional views for explaining an example of the manufacturing method according to the present invention. Here, a case where tungsten bumps are formed on an aluminum wiring layer is shown. shows.

In FIG. 1, 11 is a silicon substrate, 12 is a device layer, and 13 is a passivation film.

14 is an aluminum wiring layer, and 15 is a contact hole for electrically connecting the device layer 12 and the aluminum wiring layer 14. Although 16 is a SiO□ film, other insulating films such as Si3N4 may be used. 17 is the above 5i
This is a through hole formed in the 02 film, and 18 is tungsten embedded in the through hole.

19 is a tungsten bump formed on the aluminum wiring layer.

Here, a case in which a tungsten bump having such a structure is formed will be specifically explained. First, silicon substrate 1
A device layer 12 made of a MOSFET or the like is formed on the substrate 1 by a normal LSI manufacturing process. Furthermore, after covering the device layer 12 with a passivation film 13, a contact hole 15 is formed, and an AI wiring layer 14 is further formed (FIG. 1(a)). Next, a 5i02 film 16 is formed on the AI wiring layer 14 by a CVD method or a sputtering method, and then a through hole 17 is formed in the 5i02 film 16 by a normal ring graph and subsequent dry etching (FIG. 1(b)). Furthermore, tungsten 18 is selectively embedded in the through hole 17 by a selective tungsten CVD method utilizing a reduction reaction of tungsten hexafluoride (WFs) with silane gas (FIG. 1(C)).

Thereafter, dry etching is performed in a reactive gas such as (CF4+CHF5) in which the composition and gas pressure of the mixed gas are controlled to make the etching rate of 5i02 sufficiently higher than that of tungsten, thereby removing part or all of the 5i02 film 16. selectively removed (FIG. 1(d)). Through the series of steps described above, the tungsten bump 19 can be formed on the aluminum wiring.

In the above-mentioned example, a case was shown in which tungsten bumps were formed on aluminum wiring, but metal CVD was used as the wiring layer.
Materials in which selective growth of tungsten occurs by the method, such as tungsten and titanium nitride (Hiroshi Ikeda et al., Proceedings of the 49th Annual Conference of the Japan Society of Applied Physics, 4p-A-15)
It is obvious that tungsten bumps can also be formed using polysilicon, polysilicon, or multilayer films made of these materials, such as W/Al or TiN/AI.

Furthermore, although the above example shows the case of forming tungsten bumps, it is also possible to form metal bumps other than tungsten by selectively filling the through hole 17 with a metal other than tungsten, such as A1, etc., by metal CVD. This is also self-evident.

(Example 2) Example 1 showed a case in which tungsten bumps were formed on a wiring layer formed on a device layer, but in the present invention, tungsten bumps were formed directly on a diffusion layer formed on a silicon substrate. is also possible. Figure 2 (a) to (d)
) is an n diffusion layer 23 formed on a p-type silicon semiconductor substrate.
FIG. 4 is a process cross-sectional view for explaining a case where a tungsten bump 52 is formed thereon. Figure 2 (a) is a normal MO8
It shows an n-channel MO8FET 28 made on a p-type silicon substrate 21 by an FET formation process. Here, 2
1 is a p-type silicon substrate, 22 is a LOGO8 oxide film, 23
is an n-diffusion layer (source and drain), 24 is a gate oxide film, 25 is a gate, 26 is a passivation film, 27
is an aluminum wiring layer. In order to form a tungsten bump on the n-diffusion layer 23 shown in FIG.
The i○2 film 29 is completely etched, and a through hole 30 film is formed in the 5i02 film 29 by lithography and dry etching (FIG. 2(b)). Next, metal CV
The through hole 30 is filled with tungsten 31 by the D method (FIG. 2(C)). After that, the SiO2 film 29
A tungsten bump 32 was formed on the n-diffusion layer 23 by removing part or all of it by dry etching.

Although the formation of tungsten bumps on the n diffusion layer 23 has been described here, it is obvious that tungsten bumps can also be formed on the p+ diffusion layer.

(Effects of the Invention) As detailed above, according to the present invention, metal bumps can be formed on a wiring layer formed on a silicon substrate or on a diffusion layer formed on a silicon substrate without including an electrolytic plating process. becomes possible. Therefore, there is no fear of contamination of the semiconductor substrate by alkali metal ions present in the plating solution, which has been a problem in the past. Furthermore, since the method for manufacturing metal bumps according to the present invention does not require the step of forming electrodes for electrolytic plating and the step of removing the plating electrodes after electrolytic plating, it is possible to reduce the number of steps required for forming metal bumps. This also has the effect of improving the manufacturing yield of metal bumps.

[Brief explanation of the drawing]

FIG. 1 is a process sectional view for explaining an embodiment of the manufacturing method according to the present invention, and shows a process of forming tungsten bumps on aluminum wiring. FIG. 2 is a cross-sectional view showing a process of forming a tungsten bump on a diffusion layer formed on a silicon substrate using the manufacturing method according to the present invention. FIG. 3 is a process sectional view for explaining the process of forming metal bumps by electrolytic plating as a conventional example. 11.41...Silicon substrate, 12.420.・Device layer, 13°43... Passivation film, 14,
27,44...Aluminum wiring, 15.Near tact hole, 16.29.51.5i02 film, 17.30°48...Through hole, 18.31...Tungsten, 19.32... Tungsten bump, 21...
P-type silicon substrate, 22...LOCO8 oxide film, 23
...n diffusion layer, 24...gate oxide film, 25...
Gate electrode, 26... Passivation film, 28...
・n-channel MO8FET, 45...first contact hole, 46...electrode for plating, 47...rujist, 49...buried metal (for example, Ni), 50...
Metal bump, 52...second contact hole. (d) Figure (a) 28n channel MO3FET Figure

Claims (1)

[Claims] (1) A step of forming an insulating film on a wiring layer or a diffusion layer of a device formed on a semiconductor substrate, a step of forming a through hole in the insulating film leading to the surface of the wiring layer, and a step of forming a through hole in the through hole. A semiconductor substrate comprising a step of selectively embedding metal by a metal CVD method and a step of selectively etching the insulating film to form metal bumps on the wiring layer or the diffusion layer. Production method.