JPH02172193A - Load control device - Google Patents

Abstract

PURPOSE:To enlarge the control range for supplied power in the DC period by simple configuration of circuit by using two types of control signals being changed over, in case supplies of the DC power and high frequency power are controlled alternately. CONSTITUTION:Signal to change over from No.1 mode for supplying DC current to No.2 made for supplying high frequency current, or vice versa, is given through a mode changeover signal generator circuit D. A control signal generator circuit A emits two types of signals with varying logical value simultaneously in the No.1 mode, and at the same time in the No.2 mode, through an oscillator circuit 3, NOT circuit 11, flipflop 12, NAND circuits 13, 14, AND circuits 15, 16, and NOT circuits 17, 18. Signals for No.1, No.2 modes are fed to either or both of transistors Q1, Q2 of a load control circuit B via a mode changeover circuit C. Duty factor control for the oscillator circuit 3 controls the on-duty in the DC operating period over a wide range.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a load control device that alternately supplies direct current power and high frequency power to a load, and is particularly suitable for stably lighting a high pressure discharge lamp. It is something.

[Prior Art] A discharge lamp lighting device that uses a commercial power source has a low operating frequency, so the dimensions and weight of components such as a choke, a transformer, and a capacitor that constitute the lighting device are large. Therefore, a high-frequency lighting system has been proposed as a means to reduce the size and weight of lighting devices. For example, high-frequency lighting devices using switching transistors, etc. have already been put into practical use in lighting devices for fluorescent lamps. . On the other hand, if the lighting frequency of a high-pressure discharge lamp lighting device is set to a high frequency, the lighting device can be made smaller and lighter in the same way as in the case of fluorescent lamps, but when a high-pressure discharge lamp is lit at a high frequency, so-called acoustic resonance phenomenon It has been known that arc instability occurs due to Therefore, in order to take advantage of the advantages obtained by lighting a high-pressure discharge lamp at a high frequency, the power in a frequency band where no acoustic resonance phenomenon occurs and the power in a high frequency frequency band where an acoustic resonance phenomenon can occur are determined. A lighting device has been proposed that alternately supplies light to a high-pressure discharge lamp at a cycle of (Japanese Patent Application No. 62-271237).

This conventional example is shown in FIG. The lighting device shown in Fig. 9 consists of a control signal generation circuit A, a load control circuit B, a mode switching circuit C, and a mode switching signal generation circuit, and generates a DC voltage as a power source in a frequency band where no acoustic resonance phenomenon occurs. It operates so as to alternately switch between a DC operation mode in which a high-frequency voltage is generated as a power source in a frequency band in which an acoustic resonance phenomenon can occur.

The circuit configuration shown in FIG. 9 will be explained below. DC power supply V
A series circuit of transistors Q, Q2 and a series circuit of capacitors C+ and C2 are connected in parallel to both ends of DC. Each transistor Q4. Diodes D, D2 are connected in antiparallel to both ends of Q2. Connection point of transistors Q, Q2 and capacitor C+,
A parallel circuit of a capacitor C3 and a high pressure discharge lamp 1a is connected to the connection point of C2 via an inductor. The output of the drive circuit 1.2 is connected between the base and emitter of each transistor Q, Q2.

The control signal generation circuit A includes an oscillation circuit 3 for determining the switching frequencies of the transistors Q and Q2, and the output of the oscillation circuit 3 (see FIG. 10(a)) is divided by a frequency dividing circuit 4. The frequency dividing circuit 4 includes a D flip-flop 5. The inverted output q of the D flip-flop 5 is connected to the data input, and the output of the oscillation circuit 3 is connected to the clock input C. is also connected to one input of the NAND circuit 6.7, and the NAND circuits 6, 7
The output Q and the inverted output q of the D flip-flop 5 are connected to the other input of the D flip-flop 5, respectively. NAND circuit 6,
The outputs of 7 are each inverted by NOT circuits 8.9 to produce the first and second divided outputs (Fig. 10(b), (c
), the first frequency-divided output is supplied as is to the drive circuit 2 of the transistor Q2, and the second frequency-divided output is supplied to one input of the AND circuit 1o. AN
The other input of the D circuit 1o is supplied with the mode switching signal (see FIG. 10(e)) output from the mode switching signal generating circuit Rigara, and the output of the AND circuit 10 (see FIG. 10(d) ) is supplied to the drive circuit 1 of the transistor Q.

The operation of the circuit shown in FIG. 9 will be explained below. 1st
In Figure 10, TDc is a DC operation period, and during this period, the mode switching signal (see Figure 10(e)) output from the mode switching signal generation circuit is "Low".
level, the output of frequency divider circuit 4 (Fig. 10(c)
(see FIG. 10(tl)), the output of the mode switching circuit C (see FIG. 10 (tl)) is always at the "'Low" level, and the transistor Q1 is always off.

On the other hand, the transistor Q2 outputs the output (10th
(see figure (b)), it is turned on for a certain period of time Ton every period T. When the transistor Q2 is turned on, a current flows from the capacitor C2 through the inductor L, the high pressure discharge lamp la, the capacitor C5, and the transistor Q2.

Next, when the transistor Q2 is turned off, the residual energy in the inductor causes a current to flow from the inductor through the high-pressure discharge lamp la, capacitor C7, diode D1, and capacitor C1. By repeating this operation every cycle T, current flows in one direction through the high pressure discharge lamp 1a. Note that the ripple component due to the switching of period T is bypassed by capacitor C1.

Next, during the high frequency operation period THE, since the mode switching signal (see FIG. 10(e)) output from the mode switching signal generation circuit is at "High" level, the output of the mode switching circuit C (the 10(d)) is set to ``Highb'' depending on the output of the frequency dividing circuit 4 (see FIG. 10(c)).
"level" and ""Loud" level. Therefore, the transistor Q1 operates on and off. On the other hand, the transistor Q2 is turned on and off by the output (see FIG. 10(b)) obtained by dividing the output of the oscillation circuit 3 (see FIG. 10(a)) by the frequency dividing circuit 4. Transistor Q2
The timing t1 to t2 when the transistor Q is turned on is the timing when the transistor Q is turned on.
This is different from the timing tp to t when 1 is turned on. When the transistor Q2 is turned on at timing E1, the voltage from the capacitor C2 to the inductor L1 to the high pressure discharge lamp Za is
Current flows through the capacitor C1 and the transistor Q2, and when the transistor Q2 is turned off at timing t2, the residual energy of the inductor L1 causes the high-pressure discharge lamp 1a, the capacitor C1, the diode D3, and the capacitor CI to flow from the inductor L1. Current flows through 0
Next, when the transistor Q is turned on at timing t, a current flows from the capacitor C1 through the transistor Q5, the high-pressure discharge lamp 1a, the capacitor C5, and the inductor, and the transistor Q is turned on at timing Ls.

When the inductor is turned off, a current flows from the inductor L1 through the capacitor C2, the diode D2, the high pressure discharge lamp 1a, and the capacitor C due to the residual energy of the inductor. In this way, a high frequency current flows through the high pressure discharge lamp 1a.

FIG. 11 shows the waveform of the voltage 1a applied to both ends of the high pressure discharge lamp 1a in the above circuit. During the high frequency operation period T, a high frequency voltage is applied to the high pressure discharge lamp 1'a, and during the DC operation period T'oc, a DC voltage is applied to the high pressure discharge lamp 1a.

[Problems to be Solved by the Invention] However, when the transistor QQ2 is controlled with the above-described configuration, the transistor Q2 receives the first frequency divided output of the frequency dividing circuit 4 (see FIG. 10) during the DC operation period T''oc. b)
However, since this frequency-divided output is obtained by dividing the oscillation output of the oscillation circuit 3 (see FIG. 10(a)), the on-duty (T
ON/T) becomes smaller.

Therefore, in order to supply sufficient power to the high-pressure discharge lamp fa, it is necessary to increase the current when the transistor is turned on, which causes a problem that the stress applied to the transistor Q2 increases. This poses a problem in that switching loss increases and temperature rise increases. Furthermore, there is a problem in that the current withstand capacity of the transistor Q2 increases and the cost increases. Furthermore, since the rest period of the current flowing into the inductor L1 is long, the high frequency ripple component superimposed on the DC component becomes large during the DC operation period T'oc of the voltage waveform shown in FIG. Arc instability is likely to occur. As a countermeasure to this problem, there is a method of increasing the capacitance of the capacitor C1 and increasing the difference between the impedance of the high-pressure discharge lamp/a and making it easier to bypass the high frequency component, but there is a problem that the capacitor C5 becomes larger. .

On the other hand, it is conceivable to provide an oscillation circuit used for the DC operation period T'oc separately from an oscillation circuit used for the high frequency operation period THE to widen the control range of the on-duty during the DC operation period T''oc, but the circuit configuration There is also a problem that the oscillation output of the oscillation circuit 3 has a “Low” level period (tz~t,,L,~ts).
Even if T'o is shortened, this output is frequency divided to reduce the DC operation period T'o
Since the drive signal c is obtained, there is a problem in that it is difficult to sufficiently expand the on-duty control range.

The present invention has been made in view of the above points, and an object of the present invention is to provide a load control device that alternately supplies DC power and high-frequency power to a load, with a simple circuit configuration that controls the supply during the DC operation period. The goal is to expand the range of power control.

[Means for Solving the Problems] In order to solve the above problems, the load control device according to the present invention includes a DC power supply and a first and second power source that switches the DC power supply and supplies power to the load. the second switching element, and only one switching element is turned on.
The first one supplies DC power to the load by turning off.
mode, and a second mode that supplies high-frequency power to the load by alternately turning on and off both switching elements.
In a load control device that alternately switches between
As shown in FIG. 1, there is a mode switching signal generator circuit that generates a switching signal between the first mode and the second mode, and a logical value changes simultaneously in the first mode in response to the mode switching signal. a control signal generating circuit A that generates first and second control signals whose logical values alternately change in the second mode; In the first mode, the first and second control signals from the control signal generation circuit A are supplied to the first and second switching elements, respectively, and in the second mode, the first and second control signals from the control signal generation circuit A are supplied to the first and second switching elements. The present invention is characterized in that it includes a mode switching circuit C that supplies two control signals only to the first or second switching element.

[Operation 1] In the present invention, as described above, the first and second control signals output from the control signal generation circuit A are changed according to the mode switching signal output from the mode switching signal generation circuit. In the first mode, DC power is supplied to the load by turning on and off only one switching element, in which first and second control signals whose logical values change simultaneously are generated, and both switching elements In the second mode, which supplies high-frequency power to the load by alternately turning on and off, the first and second control signals whose logical values change alternately are generated, so that DC power is In the first mode of supplying, the duty ratio of the control signal is
Since it is possible to control factors over a wide range and only one control signal generating circuit A is required, the circuit configuration does not become complicated.

[Example] FIG. 2 is a circuit diagram of a first embodiment of the present invention.

This embodiment differs from the conventional example shown in FIG. 9 in that the output of the mode switching signal generation circuit is transmitted to the rtl1m signal generation circuit A, and in the configuration of the control signal generation circuit A. The configuration of the control signal generation circuit A will be explained below. The oscillation output of the oscillation circuit 3 is transmitted to T via the NOT circuit 11.
It is connected to the trigger power of the flip-flop 12. The output Q and the inverted output q of the T flip-flop 12 are:
Each is connected to one input of a NAND circuit 13 and 14. The other input of the NAND circuit 13.14 has
The output of the mode switching signal generation circuit is connected. N
The outputs of AND circuits 13 and 14 are respectively output from AND circuit 1.
5.16. AND circuit 1
The oscillation output of the oscillation circuit 3 is connected to the other input of 5.16. The output of AND circuits 15 and 16 is transistor Q.

It is considered as the base input of Q. Each transistor Q,...
The emitters of Q, are both grounded, and the collectors are pulled up to the power supply voltage Vcc via resistors R, , R, and are connected to the inputs of NOT circuits 17 and 18, respectively.

FIG. 3 is an operational waveform diagram of this embodiment. The operation of this embodiment will be described below with reference to the same figure. first,
During the DC operation period 'T'oc, the output of the mode switching signal generating circuit (see FIG. 3(e)) is at the 'LO' level, so the output of the AND circuit 10 is always at the 'Low' level. Transistor Q is always off. Also, N
The outputs of ANDlliil paths 13 and 14 are always “High”.
''' level, so the output of the AND circuits 15 and 16 becomes the same as the oscillation output of the oscillation circuit 3 (see FIG. 3(a)), regardless of the output of the T flip-flop 12.

Therefore, the transistor Q and the NOT circuit 17 operate at the same cycle as the oscillation circuit 3, and the output of the NOT circuit 17 (see FIG. 3(b)) is the same as the oscillation output of the oscillation circuit 3. Therefore, the transistor Q2 is driven on and off by the oscillation output of the oscillation circuit 3, and by controlling the duty factor of the oscillation output of the oscillation circuit 3, the on-duty during the DC operation period T'oc can be varied over a wide range. can be controlled.

Next, during the high frequency operation period THF, since the output of the mode switching signal generation circuit is at the "High" level,
The output of the AND circuit 10 is the same as the output of the NOT circuit 18. Further, the outputs of the NAND circuits 13 and 14 are inverted versions of the output Q and the inverted output q of the T flip-flop 12, respectively. The output Q and the inverted output q of the T flip-flop 12 become "H" every cycle of the oscillation output of the oscillation circuit 3.
Since it switches between 'high' level and 'Loud' level,
As a result, the AND circuits 15 and 16 alternately output the oscillation output of the oscillation circuit 3. Therefore, the transistors Q, , Q2 are alternately driven on and off by the oscillation output of the oscillation circuit 3. This high frequency operation period TH
The switching frequency at F is the DC operating period T'o
It becomes 1/2 of the switching frequency at c.

In addition, in the operation waveform diagram of FIG. 3, for convenience of illustration,
The number of pulses in each operation period T DC, T Hf: is less than the actual number. The same applies to the following examples.

[Example 2] FIG. 4 is a circuit diagram of a second embodiment of the present invention.

The operating waveforms at points a to e in FIG. 4 are shown in FIG. 3(a) to
In this example, the waveform is the same as that shown in (e).
4) is used to configure the control signal generation circuit A. As is well known, this IC20 has a power supply terminal (bin 12)
The control power supply voltage Vcc is applied between the capacitor terminal (pin No. 5) and the ground terminal (pin 7), and the capacitor C4 is connected between the capacitor terminal (pin no.
It has a built-in oscillator 22 that oscillates at a frequency corresponding to the time constant of a resistor R5 connected between the 6th bin) and the ground terminal. The first oscillation output of IC20 is connected to the first oven collector terminal (bin 8) and the first oven emitter terminal (bin 8).
The second oscillation output is obtained by alternating between short-circuited and open states between the second oven collector terminal (pin 11) and the second oven emitter terminal (pin 11). This is obtained by alternating between a short-circuited state and an open-circuited state between the 10th and 10th bins. Here, when the output control terminal (bin 13) is dropped to the ground level, single-end operation for one stone is performed, and the first oscillation output matches the second oscillation output, and the output When the control terminal is set to "High" level, push-pull operation for two stones is performed, and the first oscillation output and the second oscillation output are output after a predetermined de-end off time.
Take the opposite state. This dead-off time can be set by dividing the reference voltage REF obtained at the reference voltage output terminal (bin No. 14) and inputting it to the dead-off time control terminal (pin No. 4).

Next, in FIG. 0, which describes the internal configuration of this IC 20, the oscillator 22, its time constant setting capacitor C1, and resistor R5 correspond to the oscillation circuit 3 shown in FIG. Further, the configuration of the pulse generation circuit 19 is similar to the single pulse generation circuit shown in FIG. The comparator 21 is a voltage comparator for pulse width control, and is a reference voltage VREF.
Resistor R.

If the voltage of capacitor C1 is higher than the voltage divided by R1, the output becomes "High"level; otherwise, the output becomes °'Low" level. Therefore,
In this embodiment, by changing the voltage division ratio of the resistors Ri and R-, the on-time width of the transistors Q, Q2 can be controlled, and the output of the load control device can be freely adjusted. .

In this embodiment, using the mode switching signal sent from the mode switching signal generation circuit to the control signal generation circuit A,
By changing the resistance value of the resistor R7 that determines the oscillation frequency of the oscillator 22, the switching frequency in the DC operation period T'oc and the high frequency operation period THE may be freely set. The on-time width in the DC operation period T"oc and the high-frequency operation period THF may be switched by changing the discharge lamp 1a.
The state of the lamp may be detected using the lamp voltage or lamp current, and a control signal may be sent to the control signal generation circuit A to control the pulse width and oscillation frequency. At this time, the DC operation period Toc
Since the maximum value of the on-duty can be increased, fine control over a wide range is possible.

[Embodiment 3] FIG. 5 is a circuit diagram of a third embodiment of the present invention, and FIG. 6 is an operation waveform diagram of the same. In this embodiment, the configurations of the control signal generation circuit A and the load control circuit B are the same as in the second embodiment, and the configurations of the mode switching circuit C and the mode switching signal generation circuit are different. First, in the mode switching circuit C, AND circuits 25 and 26 are provided so that the drive signals for any of the transistors Q, Q2 can be stopped individually. In addition, in the mode switching signal generation circuit, the oscillation output of the oscillation circuit 24 (see FIG. 6(a))
is frequency-divided by the flip-flop circuit 23, and the result shown in FIG.
), mode switching signals as shown in (c) are obtained. These signals are each supplied to one input of AND circuits 25 and 26. Further, the oscillation output of the oscillation circuit 24 is inverted by the NOT circuit 27, and the oscillation output of the oscillation circuit 24 is inverted by the control signal generation circuit A.
is supplied to the output control terminal (bin 13). Therefore, in this embodiment, from timing t1 to t2, transistor Q2 is always off, and transistor Q
Only transistor Q1 operates on and off, and at timings t, ~t, transistor Q1 is always off, and transistor Q
2 only operates on and off at timings t2 to t.

At t, to Ls(t+), transistors Q, , Q alternately turn on and off. Therefore, the operation during the high frequency operation period THF is similar to that in the second embodiment, but during the DC operation period TDc, as shown in FIG. 7, the polarity of the DC voltage applied to the discharge lamp 1a is alternately reversed. This is a preferred embodiment for extending the lamp life of the discharge lamp 1a.

[Example 4] FIG. 8 is a circuit diagram of a fourth embodiment of the present invention.

In this embodiment, the load control circuit B is operated by an inverter!
8B1 and a chopper 11ii7-way B2. First, the configuration of inverter circuit B will be explained. A capacitor C, is connected across the DC power supply VDC,
, C2, and an l transistor Q.

The series circuits Q, are connected in parallel. Each transistor Q4. Q and each have a diode D.

D, are connected in antiparallel. Capacitor C+, C
The primary winding of a high frequency transformer T is connected between the connection point of transistors Q and Q5 and the connection point of transistors Q and Q5. The secondary winding of the high frequency transformer T is connected to both ends of the high pressure discharge lamp ρa via a series circuit of an inductor and a capacitor C1. During the operation of the inverter circuit B, the transistors Q1 and Q2 are alternately turned on and off at high frequency after a predetermined dead time to supply high frequency power to the high pressure discharge lamp 1a via the high frequency transformer T.

Next, the configuration of the chopper circuit B2 will be explained. A parallel circuit of a high-pressure discharge lamp 1a and a capacitor C1 is connected to the DC power supply Dc2 between the collector and emitter of a transistor Q6 and via an inductor L2. A diode D for conducting flywheel current is connected in parallel to the series circuit of the inductor L2 and the capacitor C1. When the transistor Q6 is turned on, current flows from the DC power supply VDC2 to the high-pressure discharge lamp 1a via the transistor Q6 and the inductor L2. When the transistor Q6 is turned off, the high voltage flows from the inductor L2 due to the energy stored in the inductor L2. A current flows through the discharge lamp fa and the diode D. The ripple component due to switching of transistor Q6 is bypassed to capacitor C4, so
DC power is supplied to the high pressure discharge lamp 1a.

In this embodiment, since the load control circuit B is composed of the inverter circuit B and the chopper circuit B2, the inverter circuit B1 is stopped during the DC operation period T'oc and the chopper circuit B2 is switched on. In the high-frequency operation period THF, only the inverter circuit B1 operates and the chopper circuit B2 is stopped.For this purpose, the mode switching circuit C is controlled by the AND circuits 28 to 3.
0, the mode switching signal output from the mode switching signal generation circuit is supplied to one input of the AND circuit 29 and 30, and the NOT circuit 31 supplies an inverted signal of the mode switching signal to one input of the AND circuit 28. feeding the input. The first control signal output from the control signal generation circuit A is input to the other input of the AND circuit 28, and
The other inputs of the circuits 29 and 30 are connected to the control signal generation circuit A.
The first and second control signals outputted from the first and second control signals are respectively inputted. If the mode switching signal outputted from the mode switching signal generation circuit A is at a high level, the first and second control signals outputted from the control signal generation circuit A are passed through the AND circuit 29 and 30 to the inverter. If the mode switching signal is supplied to the driving circuits 1 and 2 of the transistors Q, , Q in the circuit B1 and is at the "'Lou+ level," only the first control signal output from the control signal generating circuit A is output from the chopper. Transistor Q6 in circuit B2
is supplied to the drive circuit 32 of.

Also in this embodiment, the control signal generation circuit A is
Since the configuration is the same as that, the mode switching signal is “I”.
When the signal is at the L0w11 level, the logic values of the first and second control signals change simultaneously, and when they are at the "High" level, the logic values of the first and second control signals change alternately. Therefore, the on-state during the DC operation period TD0
The duty can be controlled over a wide range, and the supplied power can be precisely controlled according to the state of the high pressure discharge lamp Ila.

[Effects of the Invention] As described above, the present invention provides a load control device that alternately supplies direct current power and high frequency power to a load. In the mode in which the logical values of the first and second control signals from the control signal generation circuit are alternately changed in the mode in which high-frequency power is supplied by simultaneously changing the logical values of the control signals, the DC power In the mode in which the control signal is supplied, the on-duty of the control signal can be controlled over a wide range, and the control signal generation circuit can be shared in both modes, which simplifies the circuit configuration. There is.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the basic configuration of the present invention, Fig. 2 is a circuit diagram of a first embodiment of the invention, Fig. 3 is an operation waveform diagram of the same as above, and Fig. 4 is a second embodiment of the invention. 5 is a circuit diagram of the third embodiment of the present invention, FIGS. 6 and 7 are operation waveform diagrams of the same as above, FIG. 8 is a circuit diagram of the fourth embodiment of the present invention, and FIG. 9 is a circuit diagram of the third embodiment of the present invention. The figure is a circuit diagram of a conventional example, and FIGS. 10 and 11 are operation waveform diagrams of the same. A is a control signal generation circuit, B is a load control circuit, C is a mode switching circuit, and D is a mode switching signal generation circuit.

Claims (1)

[Claims] (1) Equipped with a DC power supply and first and second switching elements that switch the DC power supply and supply power to the load, and only one switching element turns on and off to supply DC power to the load. A load control device that alternately switches between a first mode of supplying high-frequency power and a second mode of supplying high-frequency power to a load by alternately turning on and off both switching elements. a mode switching signal generation circuit that generates a mode switching signal; and a mode switching signal generation circuit that generates first and second control signals whose logical values change simultaneously in a first mode in response to the mode switching signal; A control signal generation circuit generates first and second control signals whose logic values alternately change, and a control signal generation circuit that generates first and second control signals whose logic values change alternately, and a control signal generation circuit that generates first and second control signals from the control signal generation circuit in the first mode in response to a mode switching signal. A mode switching circuit that supplies signals to the first and second switching elements, respectively, and supplies the first or second control signal from the control signal generation circuit only to the first or second switching element in the second mode. A load control device comprising: