JPH02161851A - ATM switch - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figures 3 and 4) Means for solving the problem to be solved by the invention (Figure 1) Effect (Figure 1) Figure) Embodiment (Figure 2) Effects of the invention [Summary] ATM [Asynch] suitable for so-called broadcasting type communication
ronous Transfer Mode; ATM (
Regarding asynchronous transfer mode), the purpose of this system is to distribute cells from an input line to multiple output lines to enable broadcast-style communication, with one output line connected to and corresponding to all input lines. The number of output corresponding parts connected to the output lines is provided in parallel, and each output corresponding part is connected to each corresponding input line, and the output corresponding parts are connected to the output line based on the identifier in the ladder of the cell entering from the input line. Determine whether or not to output the cell, and when outputting the cell to the output line, pass the cell and change the cell identifier to one for the output line,
In other cases, the number of gate sections for blocking the passage of cells is provided as many as the number of input lines, the buffer sections for temporarily storing a plurality of cells from each gate section are provided corresponding to the gate sections, and the cells are stored in each buffer section. It is equipped with an output control section that outputs cells to an output line, and distributes cells from the input line to multiple output lines.
The distribution cells are configured to each have a different identifier.

[Industrial Application Field] The present invention relates to an ATM switching system suitable for so-called broadcasting type communication.

In recent years, CCITT has agreed on an ATM switching technology that combines the bandwidth flexibility of packet switching and the time transparency of circuit switching as a method for realizing broadband I5DN, and various institutions are actively conducting research on this technology. I'm exhausted.

[Prior Art] As such an ATM switching system, for example, a configuration using a self-routing channel as shown in FIG. 3 has been proposed. In the circuit shown in FIG. 3, for example, 3×3
A unit self-routing switch (hereinafter, a unit self-routing switch may be referred to as a unit switch) is connected to the incoming line side (S□□).

Si,, S engineering, reference), intermediate (Sa□y 522t S
23), outgoing line side (S, 1. S, □, see S33)
There are 3 of each in the primary link L construction 1. L1□, L construction, connects the three output ends of the incoming switch Sii to the intermediate switch 82.
1-S2. to each first input end of the primary link L
2□~L23g L31~L32 also conform to this. ,2
The next links M 11 to M 13 are intermediate switches S 21
The three output terminals of the three switches 831 to S on the output side
33 to each first input end of the secondary link M 21
""" M 21 r M 71 to M 32 also apply to this.

In this self-routing call path, first S1□.

S2□～S231 If S31 is installed, S1□
and S, 2°Sol and S 23 can be installed simply by installing Lm to Lz3. without making any changes to the existing parts. L, □~L1.
This can be done simply by connecting the wires as shown.

Also, for example, the path that leads incoming line #9 to outgoing line #3 is S engineering, S2□, S 31+ 5lff, S2□, So, S□,
There are 3 passes, S23 and S31, S Yu, and S31.
The traffic between 82□ and S2. Furthermore, if traffic is concentrated on S2□ and there is a delay, you can change the path to pass via S22 or S23, and the delay can be reduced as much as possible. .

FIG. 4 shows an example of the configuration of the 3×3 unit self-switch shown in FIG. ■, ~E, is a control information detection circuit, D□ ~ D is an information delay circuit, DM ~ DM3 is a demultiplexer, DE
C-DEC, control information decoding circuit, F11-F,
3 is FIFO memory (first-in first-out memory), S
L□~SL3 are selectors, DS, ~DS, are FIFO memories F1□~F1. F2□~F 231 F31~F
, 11 to 13 degrees to the request signal of 3 K21 to K2
．． , K31~ receives 33, selector SL□~SL,
This is a circuit that controls the

The signals entering the input terminals #1 to #3 are the information child control information (
It has the shape of a cell), and the detection circuit I□~.

extracts this control information and then outputs the corresponding decoding circuit D.
Send to EC1-DEC3. If the self-routing channel 4 has a three-stage configuration, there are three types of control information: RH for the first stage, RH for the second stage, and RH for the third stage. The self-routing switcher extracts the corresponding control information +RH depending on the stage.

If the input control information indicates output terminal 1 (i-3), the decoding circuits DEC1-DEC operate the demultiplexer and send the information to the FIFO memory Fi,I. For example, if the control information of input #1 indicates output terminal #2, the decoding circuit DEC operates the demultiplexer DM to input input #1 to F21.

When information is entered into the FIFO memories F11 to F13, the control circuit DS1 operates the selector SL1 to send the cell to the output #J. The same applies to others.

The control circuit DS constantly scans the request signals Ki, j from the FIFO memories Fi, , i, for example, and operates to output the contents of the FIFO memory through the selector SLi when the request signal Kij is detected. Alternatively, the request signal Kij is input as an interrupt to the control circuit DS, and when the interrupt occurs, the control circuit DS outputs the contents of the FIFO memory through the selector.

[Problem to be solved by the invention] However, in such a conventional ATM switching system,
No consideration is given to so-called broadcast-style communication in which cells from an input line are distributed to a plurality of output lines.

The present invention aims to solve these problems by providing an ATM switching system that enables so-called broadcast-type communication in which cells from an input line are distributed to a plurality of output lines. With the goal.

[Means to solve the problem] FIG. 1 is a block diagram of the principle of the present invention.

In FIG. 1, reference numerals 1-1.1-2.1-m are output correspondence units, and each output correspondence unit 1. -1.1-2. . . 1-m is connected to all input lines #1 to #n, and one corresponding output line #1. #2. ... is connected to m. Therefore, the output corresponding section 1-1゜1--2. ..., 1-m
are provided in parallel by the number of meters of output lines.

In addition, each output corresponding section 1-1.1-2. ..., 1-m
is the gate part CD,~CD,n,CD,1~CI)z
n+ ”p CDms~CDIlIn+buffer part F
11-wF,n, Fzx~Fzn+' ”t
Flu~FllIn and output control units CNTi, CNT
2. --, CNT, A.

Here, the gate part CDz, ~CD+, n + CDy,
□~CDzn+ '' + CD1111~CDIn are provided by the number n of input lines, and each gate part CDi, 1
(i = 1~m.

j = 1 to n) are connected to each corresponding input line #j, and are connected to this output corresponding part 1-j based on the identifier in the ladder of the cell entering from this connected human power line #, j. Determine whether or not output line #i should be output, and if output line #i is to be output, the cell is passed through and the cell identifier is changed to that for the output line; otherwise, the cell is 5 These goo l are some CDs that prevent the passage of
1j are provided for the number n of input lines.

Buffer sections Fj and J temporarily store a plurality of cells from gate sections CD and J, and these buffer sections FIJ
is provided for several meters of the gate portion cDIJ.

The output control unit CN14 transfers the cells stored in each buffer unit Fij to an output line #i connected to this output corresponding unit 1-j.
Each output control unit CNTl outputs to the control circuit D.
It is equipped with a control circuit DS, a selector SL, and a control circuit DS.
, i, when a cell enters the buffer section Fjj, the selector SL is operated and the cell is sent to the corresponding output line #i.

[Production use] For example, a cell that enters from input line #1 is output line #].

Consider the case where you want to send each to #2.

First, cells from each input line #1 correspond to each output]--i
The corresponding Goo 1 portions are input to CD and J, respectively.

In this case, only the gate section CD of the output correspondence section 1-1 and the gate section CD,1 of the output correspondence section 1-2 allow the cell to pass through, and the other gate sections block the passage of the cell.

Thereafter, the cells that have passed through the gate section CD are temporarily stored in the buffer section F, and then transferred to the output control section CNT.
The cells that have passed through the gate section CD2□ are output to the output line #1 through the selector SLi of the buffer section F.
After being temporarily stored in 2□, it is output to output line #2 through selector SL2 of output control unit CNT. At this time, the cell identifier has been changed to one for each output line.

Note that even when it is desired to output a cell entering from an arbitrary input line to an arbitrary output line, routing control is performed in substantially the same manner as in the above case.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

Now, in this embodiment as well, for example, a 3×3 unit switch 5lj (i=1.2°3+J=
1+2+3) are placed on the incoming line side, three in the middle, and three on the outgoing line side, and each unit switch Sij is connected by a link, but the configuration of each unit switch is different from the conventional one as shown in Fig. 4. different from.

That is, each unit switch Sij has three output corresponding parts 1-1.1-2.1-3, as shown in FIG. Here, each output corresponding section 1-1, 1-2, 1-3 is connected to all input lines #1 to #3, and one corresponding output line #1. Connected to #2 and #3. That is, each output corresponding section 1-1.1-2.1-3 is provided in parallel.

Further, each output corresponding section 1-1.1-2.1-3 is a cell dropper CD□, to CD□, as a gate section.

CD21-CD23. CD, ,~CD,, ,FIFO memory F□1~F 13P F21 as a buffer section
~F2. .

F, □ to F33 and output control unit CNT1. Equipped with CNT2°CNT2.

Here, cell droppers 〇D11 to CD □, CD, □ to CD2 . ．． CD, 1-C
Each cell dropper CD1j (i=1 to 3.j=1 to 3) is connected to each corresponding input line #j, and the connected input lines Information INF (information field) of the cell entering from line #j
Based on the information identifier VCI added to the output corresponding section 1-i, it is determined whether the cell should be output to the output line #i connected to the output corresponding section 1-i, and if the cell is to be output to the output line #i, It allows the cell to pass through and changes the cell identifier VCI to that for the output line, and otherwise prevents the cell from passing.

In this example, 8 bits are transmitted in parallel on the transmission path.

Furthermore, in order to perform the above function, each cell dropper 〇Dij connected in multiple ways as described above is connected to a separation circuit D.
MXij, delay circuit DLij, VCI conversion table VC
Tij and a multiplexing circuit MXij.

Here, the separation circuit DMXij separates the information INF of the cell input from the input line #j and the information identifier VCI, and the VCI conversion table VCTij converts the enable bit (hereinafter referred to as , E.N.
It stores information identifiers (referred to as bits) and information identifiers VCI' for output lines.

Further, the delay circuit DLij keeps the information INF separated by the separation circuit DMXij waiting for a time corresponding to the search in the VCI conversion table VCTij, and the multiplexing circuit MXi
j is the information INF from the delay circuit DLij and the information identifier VCI' for the output line from the VCI conversion table vCTij.
This multiplexing circuit MXij
is activated when the EN bit corresponding to the input line information identifier VCI is set (in the case of "1").

Therefore, the information INF and the information identifier VCI are separated from the cell input from the input line #j by the separation circuit DMXij, and using this information identifier VCI as an address, the VCI
The conversion table VCTij is searched and the corresponding EN bit and new information identifier vC1' are read out. After the child,
The read output line information identifier VCT' and the information INF delayed by the delay circuit DLij are multiplexed by a multiplexing circuit M.
Multiplexing is performed with X, ij. At this time, if the ENN bit is [], the multiplexing circuit MXij sends it to the FIFO memory Fjj, and if the I'IN bit is rOJ, it does not send it to the FffFO memory Fjj.

As a result, each cell dropper CDi, j determines whether or not to output the cell to the output line #i connected to the output corresponding section ]--i, and when outputting the cell to the output line #i, the cell is set to 31L. It is possible to change the cell identifier VCI to that for the output line, and otherwise prevent the cell from passing.

The FIFO memories Fjj temporarily store cells from the cell droppers CJj in the order in which they are sent, and these FIFO memories F1j are provided as many times as there are cell droppers C0 (3).

The output control unit CNTi sequentially outputs the stored information of each FIFO memory Fij to the output line #j connected to this output corresponding unit 1-1 in the order in which it is stored in the FIFO memory Fj, and controls each output control unit. The section CNTi includes a control circuit DSi and a selector SLj, and when a cell is entered into the FIFO memory Fij by the control circuit DSi, the selector S
Li is manipulated so that the cell is sent to the corresponding output #i.

In addition, such control circuit]) S J and selector S L
, i are the same as shown in FIG.

” Due to the double configuration, for example, the first stage unit switch S□
If we consider the case where we want to output a cell that enters from input line #1 in input line #1 to one output line #2 and #3, first, each input line #1
The cells from ~#3 are sent to the corresponding cell droppers CD, 1~CDi, CD21~ of each output corresponding section 1-1~1-3.
CD2], CD, , ~CD, , respectively.

In this case, output handling section 1. -2 cell dropper CD
2□ and cell dropper of output corresponding part 1-3 D31
．． Only the cell dropper allows the cell to pass through and changes the information identifier MCI; other cell droppers prevent the cell from passing.

That is, Cell Dropper CD7. Now input line #]-
The separation circuit DM Read out. In this case, since EN pin 1- is "1", a new information identifier VCI' is added to the cell in the multiplexing circuit MX2□, and the FIFO memory F2. sent to.

This operation is the same for the cell dropper Dlli.

Note that in other cell droppers, since the EN bit read from the 70-cell conversion table is "0", the cell is not sent to the FIFO memory, thereby preventing the cell from passing through.

After that, the cell that passed through the cell dropper〇D21 is F
After being temporarily stored in the IFO memory F21, the output line #2 is output through the selector 5r=2 of the output control unit CNT.
The cells that have passed through the cell dropper CD31 are temporarily stored in the FIFO memory F,1, and then output to the output line #3 through the selector SL3 of the output control unit CNTl.

In addition, if you want to output a cell that enters from any input line in this unit switch s1i to any plurality of output lines, or if you want to output a cell that enters from any input line in this unit switch s1i, or use other 1st stage unit switches S12+5il, 12th stage unit switches Szx to S23, 3rd stage It goes without saying that even when it is desired to output a cell that enters from any input line in the second unit switches 331 to Sff3 to any plurality of output lines, it can be implemented in substantially the same manner as in the above case.

In addition, the nxm of the 3x3 unit switch as shown above
It goes without saying that the present invention can also be applied to the unit switch.

[Effects of the Invention] As detailed above, according to the ATM switching system of the present invention, the gate section is connected to the five output lines and corresponds to all the input lines.

Output correspondence sections each having a buffer section and an output control section are provided in parallel as many as the number of output lines, and each output correspondence section can convert cell identifiers, allowing 1-to-N (multiple) connections. This has the advantage that communication in the form of broadcasting can be realized in the ATM switching system.

DSi is a control circuit.

Fij is a FIFO memory (buffer section), MXij is a multiplexing circuit, SL is a selector, and VCTij is a VCI conversion table.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram showing an embodiment of the present invention, Fig. 3 is a block diagram showing a conventional example, and Fig. 4 is a block diagram showing the configuration of a conventional unit switch. It is a diagram. In the figure, 1-i is an output corresponding section, cDlj is a cell dropper (gate section), and CNTI is an output control section. DI4j is a delay circuit, DMXij is a separation circuit. -N ＋ 廿绿-・ ko 4 dimension 0 ψ CD's S ij-11 single unit independent tomoe loosing suituna unit Sui Sochi's a formation T block diagram compilation 4 diagram

Claims (1)

[Claims] It has a plurality of cell-multiplexed input lines and a plurality of output lines,
Outputting a cell consisting of an information field input from an input line and a header including an identifier to an output line determined in the call setup phase, and changing the identifier to one for the output line.
In the TM switching system, each one is connected to and corresponds to all input lines.
Output corresponding parts (1-i) connected to one output line are provided in parallel in the same number as the output lines, and each output corresponding part (1-i) is connected to each corresponding input line, and this connection Based on the identifier in the header of the cell that enters from the input line, it is determined whether the cell should be output to the output line connected to this output corresponding section (1-i), and the cell is sent to the output line. When outputting, the cell passes through and the identifier of the cell is changed to that for the output line, and otherwise the number of gate parts (CD_i_j) that prevents the cell from passing are provided as many as the number of input lines, and Buffer sections (F_i_j) for temporarily storing a plurality of cells from each of the gate sections (CD_i_j) are provided corresponding to the gate sections (CD_i_j), and the cells stored in each of the buffer sections (F_i_j) It is configured with an output control unit (CNT_i) that outputs cells to an output line connected to this output corresponding unit (1-i), and distributes cells from an input line to a plurality of output lines, and An ATM switching system, characterized in that the cells are arranged so that each cell can have a different identifier.