JPH02149036A - Phase locked clock generating system in network system - Google Patents

Abstract

PURPOSE:To adequately generate a clock for the LAN of the other side which is phase locked with the clock of the LAN of one side by determining the frequency division numbers of a first and a second frequency dividers on the basis of the frequency of the clock of the first LAN and the frequency of the clock of the second LAN to be generated. CONSTITUTION:A system to which two LANs 10, 70 of different transmission speeds are connected mutually is provided with a phasing clock generator 40. The device 40 is provided with the frequency dividers 44, 45, a phase comparator 46, a filter circuit 47 and a voltage controlled oscillator 49 whose frequency varies according to the output of the filter circuit 47, and it inputs the clock CLK1 applied to the LAN 10, and detects its frequency f1, and values (m), (n) to satisfy a condition that f1/m=f2/n and besides, the value of f1/m becomes the greatest common divisor of f1 and f2 are obtained on the basis of f1 and the frequency f2 of the clock CLK2 to be applied in the LAN 70, and the values (m), (n) are designated as the frequency division numbers of the frequency dividers 44, 45, and the clock CLK2 which is phase locked with the clock CLK1 and in addition, has the frequency f2 optimum to the transmission speed of the LAN 70 is generated from the voltage controlled oscillator 49.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) This invention provides two local area networks (hereinafter referred to as LANs) with different transmission speeds, particularly a packet-switched LAN (hereinafter referred to as a packet-switched LAN). The present invention relates to a phase-synchronized clock generation method in a network system suitable for interconnecting a network LAN) and a line-switched LAN (hereinafter referred to as a line-switched LAN) to perform transmission between networks.

(Prior Art) It has conventionally been common for a line-based LAN and a packet-based LAN to form completely separate LANs. The reason is,
In a four-wire LAN, the transmission and reception speed is constant and moves in phase synchronization, whereas in a packet LAN, signals are sent and received in packets, making effective use of free space on the transmission path. .

However, in recent years, attention has been paid to the fact that packet-based LANs are suitable for high-speed, large-capacity transmission, and methods have been considered to add line-based signals to packet-based LANs for transmission. This method stores line signals in temporary memory,
It is multiplexed in phase synchronization with a high-speed master clock of a packet-based LAN and performs transmission and reception.

However, there are multiple types of clock frequencies for packet-based LANs (IMHz, IOM7, 100M11z, etc.), and there are also multiple types of clock frequencies for line-based LANs (64K).
Hz, 192K)lz, 384KHz.

1,544 MHz). Therefore, line-based LAN
In order to phase-synchronize the clock of the packet-based LAN with the clock of the packet-based LAN as described above, it is necessary to design a phase synchronization circuit for each difference in frequency.

(Problem to be Solved by the Invention) As described above, conventionally, two LANs with different transmission speeds are connected, and the clock of one LAN is used to generate a clock for the other LAN that is phase-synchronized with the same clock. However, since there are multiple types of clock frequencies for each LAN, there is a problem in that a phase synchronization circuit must be developed and designed for each different frequency (that is, different transmission speed).

Therefore, the problem to be solved by the present invention is that in a system in which two LANs having different transmission speeds are interconnected, the clock of the other LAN is synchronized in phase with the clock of one LAN.
To enable a clock for an AN to be appropriately generated based on the difference in transmission speed between both LANs, regardless of the combination of LANs having any transmission speed.

[Configuration of the Invention (Means for Solving the Problems) This invention provides a system in which two LANs (first and second LANs) having different transmission speeds are interconnected.
A phase synchronized circuit receives a first clock applied in the AN and generates a clock for a second LAN having a frequency f2 that is phase-synchronized with the first clock;
．． The first clock divides the second clock by the number of externally specified values m and n. the second frequency divider, this first frequency divider; A phase comparator that compares the phase difference between the output signals of the second frequency divider, a filter circuit that smoothes the output of this phase comparator, and the second clock whose frequency changes according to the output of this filter circuit. A phase synchronized circuit having a voltage controlled oscillator for output is provided, and the first clock is inputted to set the frequency f1 of the same clock.
is detected, and this detection frequency f1 and the second 'L A
Based on the frequency f2 of the second clock to be applied at N, m that satisfies the following formula % and the value of fl/m (-f2/n) is the greatest common divisor of fl and f2, Find the value of n, and calculate this m,
Set the value of n to 1st. The present invention is characterized in that a means for specifying the frequency division number of the second frequency divider is provided, and the second clock generated by the phase synchronized circuit is used as the clock of the second LAN.

(Operation) According to the above configuration, no matter what the combination of transmission speeds of the first and second LANs, the ml LAN
(second clock) and its frequency f1
is detected, and the detected frequency f1 and the second frequency to be generated are
By determining the frequency division numbers m and n of the 1st and 2nd frequency dividers based on the frequency f2 of the LAN clock (second clock), the first L.A.
It is possible to generate a second clock that is phase-synchronized with the N first clocks and has a frequency (f2) that is optimal for the transmission speed of the second LAN.

(Embodiment) Fig. 1 is a block diagram showing an embodiment of the peripheral structure of a phase synchronized clock generator that is directly related to this invention, and Fig. 2 shows an embodiment of a network system to which this invention is applied. FIG. 2 is a block configuration diagram.

In FIG. 2, 10 is a packet-based LAN such as a ring-type LAN, and 20 is a LAN control unit for controlling the packet-based LAN l0. LAN control unit 2
0 is the LAN basic control section 3 which forms the basic part of the unit.
0 and the same wave number fl of packet system L A N 10 (
fl is IMHz, 5M1h, 10MHz, etc.)
It has a phase-synchronized clock generator 40 that generates a clock (line-based clock) CLK2 for the line-based LAN 70 (described later) that is phase-synchronized with the clock (packet-based clock) CLKI of the system, and a line interface 50. The line interface 50 converts the line system signal into a line system clock CLK2 generated by the phase synchronized clock generator 40.
The data is stored in a temporary memory (not shown) according to the data, and is multiplexed in phase synchronization with the packet system clock CLK1.
It is configured to temporarily store packet-based signals in a memory and output them to the line-based LAN 70 in response to the line-based clock CLK2. The LAN control unit 20 further includes several LAN interfaces 60 for connecting packet-based LANs other than the packet-based LAN 10. 70 is a line system L such as a telephone network connected to the packet system L A N 10 via the line interface 50.
The AN 80 is a packet-based LAN (separate from the packet-based LAN 10) such as a bus-based LAN connected to the packet-based LAN to via the LAN interface 60.

The phase synchronized clock generator 40 shown in FIG. 2 is configured as shown in FIG. In FIG. 1, 41 inputs the packet system clock CLKI and inputs the packet system clock CLKI.
Frequency f2 phase synchronized with I (f2 is, for example, 64KH2
, 192KHz, 384Kk, 1.544MHz, etc.)
A PLL (phase locked loop) circuit (phase synchronized circuit) 42 that generates a line system clock CLK2 and outputs it to the line interface 50 is a packet system clock CLK.
A counter 43 for counting the number of clocks of the clock CLKI in order to detect the frequency of the LKI is a microprocessor. The microprocessor 43 controls the counter 42 to detect the frequency fl of the packet system clock CLKI, and based on this detection result and the frequency f2 of the clock CLK2 to be applied to the line system LAN 70, P
Frequency division number m of a frequency divider 44, 45, which will be described later, in the LL circuit 41
, n.

The PLL circuit 41 has frequency dividers 44 and 45 whose frequency division numbers can be set externally. The frequency divider 44 divides the packet system clock CLK1 by the number m set by the microprocessor 43, and the frequency divider 45 divides the frequency of the packet system clock CLK1 by the number m set by the microprocessor 43.
The line system clock CLK2 generated by itself is divided by the number of values n set by the microprocessor 43.

The PLL circuit 41 further includes a phase comparator 46 that compares the phase difference between output signals (divided clocks) of the frequency dividers 45 and 45, and a low-pass filter (LPF) 47 that smoothes the output of the phase comparator 46. and a voltage controlled oscillator (VCO) 48 that outputs a clock (clock CLK2) with a frequency that is an integral multiple of 64 KHz (maximum frequency is 1.544MEiz) as the output of the PLL circuit 41. The voltage controlled oscillator 48 has an oscillation function that changes the internal oscillation frequency fC of the internally generated clock based on, for example, 1.544 MHz according to the output of the low-pass filter 47, and the clock oscillated by this oscillation function It has a built-in frequency divider 49 that divides the frequency by, for example, a value p set by a switch and outputs the line system clock CLK2.

Next, the operation of one embodiment of the present invention will be explained.

The packet system clock CLKI used in the packet system LAN 10 is the LA of the LAN control unit 20.
N2! The control section 30 leads to the phase synchronized clock generator 40 of the unit 20, and the counter 42 in the device 40
is input. When detecting the frequency (fl) of the packet clock CLKI, the microprocessor 43 in the phase synchronized clock generator 40 first detects the frequency (fl) of the packet system clock CLKI.
A reset signal is output to the counter to clear the count value to, for example, "0". Next, the microprocessor 43 operates the counter 42 to output the packet system clock CLK.
The number of clocks of I is counted, and the count value of the counter 42 is read after the specified time has elapsed. The microprocessor 43 then detects the frequency f1 of the packet system clock CLKI based on the read count value and time t. The microprocessor 43 uses a packet system clock C
When the frequency f1 of LKI is detected, this detected frequency f1
and the packet system LA via the LAN control unit 20.
The frequency division number m specified for the frequency divider 44.45 in the PLL circuit 41 is determined from the frequency f2 of the line system clock CLK2 to be applied to the line system LAN 70 connected to N10.
, find n. These m and n satisfy the following formula % formula % (2), and the frequency f shown in the above formula (2) is fl
This is the value that is the greatest common divisor of and f2.

The above m and n are determined as follows, for example, according to flowchart 1 in FIG. First, a parameter l+J indicating a temporary frequency division number of the frequency divider 4445 is set to an initial value of 1 (steps SL, S2). Next, assuming that 1+J is the frequency division number of the frequency divider 44.45, the frequency divider 44.45
The frequency of the output signal (divided frequency) fl/l, f
It is checked whether 2/j are equal (step S3), and if they are not equal, it is checked whether the value of f2/j has become less than 1 (that is, whether the processing up to the maximum value of j has been completed). (Step S4). If the value of f2/j exceeds 1, it means that j has not reached its maximum value, and the value of j is +
1 (step S5), and then the determination in step S3 is made regarding the previous i and j, which has been increased by +1. On the other hand, if the value of f2 /j is less than 1, the value of i is +
1 (step S8), and L.

After that, the process returns to step S2 where j is set to the initial value.

As described above, for each combination of ilJ, i−
The determination in step S3 is repeated in order from 1 and j-1, and when the values of fl /i and f2 /j become equal, the values of i and j at that time are adopted as the required m and n (step S7).

The microprocessor 43 inputs these m and n to the PLL circuit 41.
This is set as the frequency division number of the frequency dividers 44 and 45 within (step S8).

Now, in the PLL circuit 41, the voltage controlled oscillator 48 generates a clock based on the frequency fc (-1,544 MHz). This clock of frequency fc is divided by a frequency division number p by a frequency divider 49 built into the voltage controlled oscillator 48. As a result, frequency f2(-fc/p)
The line system clock CLK2 is transmitted from the voltage controlled oscillator 48 (frequency divider 49 therein) to the frequency divider 45 and the line system LAN 70.
is output to. Note that the value of p is the oscillation frequency fc inside the voltage controlled oscillator 48, and the required line system clock CLK.
2 divided by the frequency f2, and this value p
is set as a frequency division number in the frequency divider 49 built into the voltage controlled oscillator 48 by switch operation. It is also possible to perform this setting from the microprocessor 43.

A packet clock CLK2 of frequency f2 from the frequency divider 49 of the voltage controlled oscillator 48 is input to the frequency divider 45.

In addition, a packet clock CL of frequency f1 is guided from the LAN basic control unit 30 to the phase synchronized clock generator 40.
KI is input to a frequency divider 44. The frequency divider 44.45 is
Input clock CLKI.

CLK2 is divided by the frequency division numbers m and n set by the microprocessor 43 to obtain frequencies fL/m and f, respectively.
A 2/n frequency divided clock is output to the phase comparator 4B. The phase comparator 46 compares the phases of both the divided clocks from the frequency dividers 44 and 45, and applies a voltage to the low-pass filter 47 according to the phase shift.

The low-pass filter 47 smoothes the output voltage from the phase comparator 46 and outputs it to the voltage controlled oscillator 48 . The voltage controlled oscillator 48 responds to the output voltage of the low pass filter 47,
An internal clock that is phase-synchronized with the packet system clock CLKI is generated, and this internal clock is divided by a frequency p by a frequency divider 49.
A line system clock CLKI having a frequency f2 which is phase-synchronized with the packet system clock CLKI is output. This clock CLKI is input to the frequency divider 45 as described above, and is also input to the line interface 50.

The line interface 50 packetizes the line signal from the line LAN 70 and transfers it to the packet LAN 10.
In the case of transmitting the line signal from the line L A N 70 to the line clock CLK2 generated by the voltage controlled oscillator 48 (of the phase synchronized clock generator 40),
The information is sequentially stored in the memory inside the line interface 50 according to the information. Line signals stored in the memory inside the line interface 50 are multiplexed in phase synchronization with the packet clock CLKI, and are provided for high-speed, large-capacity transmission in the packet LAN 10. In addition, if the line interface 50 disassembles the packet-based signal from the packet-based LAN 10 into line-based signals and sends them to the line-based LAN 70, the line interface 50 decomposes the packet-based signal from the packet-based LAN 10 into line-based signals and sends them to the line-based LAN 70. 10 is temporarily stored in the memory, and then the contents of the memory are transferred to the line system L in units of line system signals according to the line system clock CLK2.
Send to AN70.

The above describes how to connect a packet LAN and a line LAN,
Based on the packet LAN clock (CLKI), the line LAN clock (CLKI) is synchronized in phase with the packet LAN clock (CLKI).
K2) has been described, but two types of line-based LANs with different transmission speeds are connected, and for example, the clock of the lower-speed line-based LAN is generated based on the clock of the higher-speed line-based LAN. is also possible.

[Effects of the Invention] As detailed above, according to the present invention, in a system in which two LANs having different transmission speeds are interconnected, the clock of one LAN can be phase synchronized with the clock of the other LAN.
The clock for N can be generated appropriately based on the difference in the transmission speeds of both LANs, regardless of the combination of LANs with any transmission speed. There is no need to develop and design a phase-locked circuit for each combination of transmission speeds.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing an example of the peripheral configuration of a phase synchronized clock generator directly related to the present invention, and FIG.
The diagram shows a LAN with the phase synchronized clock generator shown in Figure 1.
A block configuration diagram showing an example of a network system in which a plurality of LANs are interconnected by a control unit,
FIG. 3 is a flowchart for explaining the operation. lO...Packet-based LAN (first local area network), 20...LAN control unit, 40.
...Phase synchronized clock generator, 41... PLL circuit (phase synchronized circuit), 42... Counter, 43... Microprocessor, 44.45.49... Frequency divider, 4
6... Phase comparator, 47... Low pass filter (L
PF), 48...voltage controlled oscillator (VCO), 50...
...Line interface, 70...Line system LAN (
second local area network). Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Scope of Claims] A network system in which first and second local area networks having different transmission speeds are interconnected via a local area network control unit, wherein the local area network control unit is configured to include a first local area network in the first local area network. A phase synchronized circuit receives an applied first clock and generates a second clock having a frequency f2 to be applied as a clock of the second local area network that is phase-synchronized with the first clock, A first frequency divider that divides the first clock by the number of specified values m and outputs the first divided clock, and divides the second clock by the number of specified values n and outputs the second divided clock. a second frequency divider, said first and second frequency divider;
A phase comparator that compares the phase difference between the first and second divided clocks output from the frequency divider, a filter circuit that smoothes the output of this phase comparator, and a frequency that varies according to the output of this filter circuit. a phase synchronized circuit having a voltage controlled oscillator that outputs the second clock that changes; a frequency detection means that receives the first clock and detects the frequency f1 of the clock; Based on the frequency f1 of the first clock and the frequency f2 of the second clock to be applied in the second local area network,
The following equation (1) f_1/m=f2/n...(1) is satisfied, and the frequency shown by the above equation (1) is the above f_1/m=f2/n...(1)
dividing number determining means for determining the values of m and n that are the greatest common divisor of 1 and f2, and specifying the determined values of m and n as the dividing numbers of the first and second frequency dividers; A method for generating a phase synchronized clock in a network system, characterized in that the second clock generated by the phase synchronization circuit is used as a clock for the second local area network.