JPH02148901A - Integrated circuit device and its mounting method - Google Patents

Abstract

PURPOSE:To cope with fast speed tendency of devices by providing a line for a signal input and output comprising a coplaner transmission line, a low impedance power line having a large static capacitance between ground and a ground line with a low inductance. CONSTITUTION:A wiring board 9 is put in a package 1 and a chip 5 and a wiring board 9 and the wiring board 9 and the package 1 are connected respec tively by a bonding wire 10. The wiring board 9 is made of a signal line part 12 of multi-layer structure formed by laminating a metallic layer and a ceramic layer in multiple on a metallic board 11, a signal line 14 on the wiring board 9 is matched with impedance and a coaxial line or a coplaner line is employed to improve the isolation between the lines. The ground is connected to the metallic board 11 through a via hole to be connected just close to the chip and low impedance processing is attained. Thus, high speed operation is attained in a logic integrated circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit or hybrid integrated circuit device in a frequency range of 10 GHz or higher, and a method for mounting the same.

[Conventional technology]

Conventionally, integrated circuit devices have used ceramic packages or metal packages and connection techniques using wire bonding. FIG. 6 shows a conventional implementation example.

In this figure, 1 is a package such as a multilayer ceramic or metal package, 2 is an input/output signal terminal, 3 is a power supply terminal or a ground terminal, and 4 is a chip mounting section. FIG. 7 shows a partially enlarged cross-sectional view of a state in which a semiconductor IC chip is mounted on the chip mounting portion 4 of this package 1 and bonded.

In FIG. 7, 5 is a semiconductor IC chip (hereinafter simply referred to as a chip), 6 is a bonding wire ◆, and a chip capacitor 7 is used to lower the impedance of the power supply line.
In some cases, a chip resistor (not shown) for terminating the line or line is placed in the immediate vicinity of the chip 5 and bonded to it. When mounting the chip 5, chip capacitor 7, etc. on the package 1 in FIG. 7, a dimensional margin was required due to mechanical conditions and the spread of the adhesive material. Furthermore, it was difficult to align the heights of the terminals to be bonded.

With such a structure, the bonding wire 6 becomes long, so that a parasitic inductance 8 is generated as shown in FIG. Because of this inductance, a resonance phenomenon occurs due to signals in the power supply line and ground line due to the inductance 8 of the bonding wire.

■ Signal line impedance mismatch occurs due to bonding wire inductance 8, etc.

■ As bonding wires become longer, signal leakage occurs due to capacitive coupling between signal input and output lines.

(Problems to be Solved by the Invention) When looking at these phenomena from the viewpoint of IC characteristics, characteristic deterioration due to the resonance phenomenon (2) causes the frequency characteristics of the amplifier to become uneven, and gain peaks and valleys occur. As a result, the operation becomes unstable and the phase characteristics deteriorate. In logic circuits, the waveform is distorted and the rise and fall are delayed. In extreme cases, this will lead to oscillation and the circuit will no longer function.

FIG. 9 shows an example in which a valley occurs in the transmission characteristic 521 (gain) due to resonance. The frequency fd of this valley is 1/(2πF) where the inductance of the bonding wire is C and the parasitic capacitance of the pad of the L1 chip is C. As described above, the conventional technology tends to cause resonance at about 2 to 5 GHz.

Characteristic deterioration due to impedance mismatch (2) increases the rise and fall times of waveforms in the logic circuit, increases distortion in the amplifier, and decreases the S/N ratio due to reflection noise.

Deterioration due to signal leakage (2) feeds back from the input to the output, making the operation unstable and even causing oscillation. FIG. 10 shows an example of the isolation characteristics of the prior art. 5GHz
It has deteriorated by about 20 dB.

As described above, the conventional technology has many drawbacks when it comes to implementing ultra-high frequency, ultra-wideband, and ultra-high speed integrated circuits.

The purpose of this invention is to provide a mounting technology that can handle higher speeds and higher frequencies of devices, and eliminates the conventional problem of deterioration in the performance of integrated circuits due to the parasitic effects of mounting bonding wires. and its implementation method.

(Means for Solving the Problems) An integrated circuit device according to the present invention is formed with a multilayer structure of a metal layer and a ceramic layer, or a ceramic layer or an organic insulating layer laminated on a metal plate. A signal input/output line consisting of a coplanar transmission line, coaxial line, or microstrip line formed of a multilayer structure, and a low impedance power line with a large capacitance between it and the ground. , a wiring board having a low inductance ground line and an opening for arranging a semiconductor IC chip, and this wiring board and a semiconductor I
It consists of a package with a C-chip glued inside.

In addition, the method for mounting an integrated circuit device of the present invention includes bonding a semiconductor IC chip to a wiring board, inserting and bonding the wiring board and chip into a package at the same time, and then connecting terminals of wiring on the wiring board with a conductor. Furthermore, each terminal of the semiconductor IC chip and the terminal of the wiring board are connected by a conductor.

(Function) The integrated circuit device of the present invention has low impedance because the power supply line has a large capacitance, and is easy to assemble because it can be composed of three parts: a wiring board, a semiconductor IC chip, and a package.

Further, according to the integrated circuit device mounting method of the present invention, alignment is easy and dimensional margins may be small.

〔Example〕

A first embodiment of the present invention is shown in FIGS. 1(a), (b), and (c). FIG. 1(a) is a plan view of the wiring board 9, FIG.
b), (C) are lines AA' and B- in Figure 1 (a).
FIG. 3 is a diagram showing the relationship between a cross section taken along line B' and a package. Note that the connecting conductor 10 shown in FIGS. 1(b) and 1(C) is omitted from FIG. 1(a). A wiring board 9, which is the main part of the present invention, is placed in a prior art package 1 having signal input/output terminals 2 and power supply terminals 3, and the chip 5 is connected to the chip 5 using bonding wires, ribbons, or an alternative connecting member 10. and wiring board 9, and between wiring board 9 and package 1. The wiring board 9 is formed of a multilayer signal line part 12 formed by laminating a metal layer and a ceramic layer or a metal layer and a polyimide layer in multiple layers on a metal substrate 11, and has a signal line part 12 with a multilayer structure formed by laminating a metal layer and a ceramic layer or a metal layer and a polyimide layer, etc., on a metal substrate 11. A slightly larger opening 13 is provided, and the structure and dimensions are such that the bonding wire can be made as short as possible. The signal lines 14 on the wiring board 9 are coaxial lines or coplanar lines so that impedance matching can be achieved and isolation between the lines is improved. A structure with a ground layer at the bottom or a triplate structure with a ground layer (omitted in Figure 1 (a)) at the top can be applied to the coplanar line, and these lines are made of multilayer ceramic, multilayer polyimide, etc. It can be formed using this technology. For coaxial lines, a pseudo-coaxial structure can be realized using via hole technology, and when an organic insulating film such as polyimide is used, a complete coaxial structure can be realized using photo processing and etching techniques.

A large capacity bypass capacitor 15 can be formed by forming the power supply line using a ceramic or organic insulating film and by forming it into a multilayer structure. In organic insulating films, 1
Since it can be applied up to a thickness of about 0 μm, and up to about 50 μm in the case of ceramic, it is possible to achieve a value of 2 to 3 pF per square mm. By connecting the ground to the metal substrate 11 through a via hole, it can be connected close to the chip, and impedance can be reduced. When designing the wiring board 9, the bonding wires can be shortened by aligning the height of the bonding terminal of the signal line section 12 and the height of the upper connection terminal of the capacitor of the power supply line section with the height of the bonding pad of the chip. be able to.

The thickness of the semiconductor IC chip 5 is 0.3 to 0.4 mm, and the thickness of the bypass capacitor 15 made of a high dielectric constant substrate is 0.3 to 0.4 mm.
2mm, so the metal substrate 11 is made with a thickness of 0.2mm,
The thickness of the multilayer structure wiring 12 in the wiring portion may be set to 0.1 to 0.2 mm.

Various mounting orders are possible for mounting the chip 5 on the wiring board 9 and the package 1.

(1) A method of bonding the chip 5 to the wiring board 9, then inserting and bonding the wiring board 9 and the chip 5 into the package 1 at the same time, and then bonding each terminal 2.3 of the wiring board 9 and the package 1; (2) In this method, after bonding the wiring board 9 to the package 1, the chip 5 is bonded.

(1) is suitable because alignment is easy and dimensional margins are small. In addition to conventional bonding wire and bonding ribbon, T
A B (Tape Automated Bondi
ng) technology can be easily applied, and the inductance can be significantly reduced by reducing the line length, increasing the line width, etc. For example, a normal 25 μΦ bonding wire has an inductance of ~inH per 1 mm, but a ribbon-shaped bonding material with a width of 100 μ and a thickness of 25 mm can reduce the inductance to 0.5 nH or less.

A second embodiment is shown in FIGS. 2(a) to 2(C).

These figures correspond to FIGS. 1(a) to (C), respectively. In the first embodiment shown in FIG. 1, a large-capacity bypass capacitor 15 is formed with a multilayer structure of metal and ceramic or metal and an organic insulating film that forms the power supply line, but it is formed with a high dielectric constant substrate 16. The capacitor thus prepared is bonded onto the metal substrate 11, and the upper electrode 17 of the high dielectric constant substrate 16 is used as a power supply line. With this structure, a large-capacity bypass capacitor 15 can be connected close to the chip, and the impedance of the power supply line can be lowered. Furthermore, since the area occupied by the bypass capacitor 15 can be reduced, the packaging can be downsized and the cavity resonance frequency of the package 1 can be lowered.

I have described the case of analog amplifiers so far, but if you do not need the bypass capacitor 15 close to the chip, such as a multi-terminal logic IC or LSI chip, the power supply line is thin and the input/output signal line section is reduced accordingly. It is also possible to increase the number of pins.

A third embodiment is shown in FIGS. 3(a) and 3(b).

These figures correspond to FIG. 1(b), respectively.

Hole 13 for chip mounting in metal substrate 11 of wiring board 9
Alternatively, a taper 18 or a step 19 is provided in the peripheral portion to increase the dimensional margin between the chip end face and the wiring board end face or the wiring board end face and the package side wall on the surface to be bonded to the lower package 1. As a result, chip 5 and package 1,
When bonding the wiring board and package with an adhesive, a portion can be created for excess adhesive to escape. This makes it possible to reduce the dimensional margin on the upper bonding surface and shorten the bonding length.

FIG. 4 shows a fourth embodiment. This corresponds to FIG. 1(b). A metal plate 20 is bonded to the upper ground of the signal line portion 14 of the wiring board 9. As a result, a ground layer is formed on the chip 5. If the ground is high frequency and perfect, isolation between signal input and output can be improved. Furthermore, by controlling the space above the chip 5 to be small using the metal plate 20, the cavity resonance frequency can be increased.

A fifth embodiment is shown in FIGS. 5(a) to 5(C).

These figures correspond to FIGS. 1(a) to (C), respectively. In the second embodiment shown in FIG. 2, the structure is such that the upper electrode 17 of the high dielectric constant substrate 16 is directly bonded to the chip 5, but the power line is once connected to the relay terminal in the same multilayer structure as the signal line part 12. 21 is provided and connected to the electrode on the high dielectric constant substrate 16 through this. As a result, the batten width can be increased at the relay terminal 21, so that the precision of batten formation on the high refractive index substrate 16 can be relaxed.

(Effects of the Invention) As explained above, the present invention has a multilayer structure of a metal layer and a ceramic layer, or a ceramic layer laminated on a metal plate, or a multilayer structure of an organic insulating layer and a metal layer. A low impedance power line with a large capacitance between the signal input/output line consisting of a coplanar transmission line, coaxial line or microstrip line and the ground, and a low inductance ground. It consists of a wiring board having wires and an opening for arranging a semiconductor IC chip, and a package in which the wiring board and the semiconductor IC chip are adhered.
In logic integrated circuits, high-speed operation, improvement of operating waveforms,
The noise margin is increased, and in analog integrated circuits such as amplifiers, higher frequencies, wider bands, and higher gains can be achieved. Specifically, stable operation at 10 GHz or higher can be achieved.

Further, the mounting method of the present invention includes bonding a semiconductor IC chip to a wiring board, inserting and bonding the wiring board and chip into a package at the same time, and then connecting terminals of the wiring on the wiring board with a conductor, and further, Since each terminal of the semiconductor IC chip and the terminal of the wiring board are connected with a conductor, alignment is easy and a small dimensional margin is required, so there is an advantage that the overall size can be reduced.

[Brief explanation of the drawing]

Figure 1 (a), (b), (c), Figure 2 (a), (b)
, (c) is the first aspect of this invention. FIG. 3(a) is a plan view showing the second embodiment and a diagram showing the relationship between the cross section taken along the line AA' and the cross section taken along the line B-B' and the package.
, (b) are sectional views of essential parts showing a third embodiment of the present invention, FIG. 4 is a sectional view of essential parts showing a fourth embodiment of this invention, and FIGS. ) and (C) are plan views showing the fifth embodiment of the present invention, a cross section taken along the line A-A, and a cross-section taken along the line B-
6 is a perspective view showing an example of a conventional mounting package; FIG. 7 is a sectional view of main parts for explaining the mounting form of a conventional package; FIG. 8 is an explanatory diagram of parasitic inductance, FIG. 9 is a diagram illustrating the transmission characteristics of the amplifier, and FIG. 10 is a diagram illustrating an example of isolation characteristics. In the figure, 1 is a multilayer ceramic or metal package,
2 is a human output signal terminal, 3 is a power supply or ground terminal, 4 is a chip mounting part, 5 is a chip, 6 is a bonding wire, 7 is a chip capacitor, 8 is a parasitic inductance, 9 is a wiring board, 1o is a connection Members, 11 is a metal board, 12 is a signal line part, 13 is a chip mounting hole, 14 is a signal line, 15 is a bypass capacitor, 16 is a high 8 current board, 17 is a power supply line, 18 is Taber, 19 is The stage 2o is a metal plate, and 21 is a relay terminal. 17: tam Figure Figure General Metal Plate Section 5 Iso-Shi 1 ((IB)

Claims (2)

[Claims] (1) In an integrated circuit device using a ceramic package or a metal package, it is formed with a multilayer structure of a metal layer and a ceramic layer, or a ceramic layer laminated on a metal plate or an organic insulating layer and a metal layer. A signal input/output line consisting of a coplanar transmission line, coaxial line, or microstrip line formed in a multilayer structure, and a low impedance power line with a large capacitance between the ground and the A wiring board having an inductance ground line and an opening for arranging a semiconductor IC chip, and a package in which the wiring board and the semiconductor IC chip are adhered. Integrated circuit device. (2) In the integrated circuit device according to claim (1), after bonding the semiconductor IC chip to the wiring board, the wiring board and the chip are simultaneously inserted and bonded into a package, and then the terminals of the wiring of the wiring board are bonded. A method for mounting an integrated circuit device, comprising connecting each terminal of the semiconductor IC chip to a terminal of the wiring board using a conductor.