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JPH02148833A - Selective vapor growth method - Google Patents

Selective vapor growth method

Info

Publication number
JPH02148833A
JPH02148833A JP30093188A JP30093188A JPH02148833A JP H02148833 A JPH02148833 A JP H02148833A JP 30093188 A JP30093188 A JP 30093188A JP 30093188 A JP30093188 A JP 30093188A JP H02148833 A JPH02148833 A JP H02148833A
Authority
JP
Japan
Prior art keywords
layer
etching
opening
substrate
selective vapor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP30093188A
Other languages
Japanese (ja)
Other versions
JP2654143B2 (en
Inventor
Shuichi Samata
秀一 佐俣
Yoshiaki Matsushita
松下 嘉明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP63300931A priority Critical patent/JP2654143B2/en
Publication of JPH02148833A publication Critical patent/JPH02148833A/en
Application granted granted Critical
Publication of JP2654143B2 publication Critical patent/JP2654143B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To eliminate contamination, etc., of a silicon substrate, and to remote a damaged layer even in an opening having fine and high aspect ratio by removing a damaged layer by RIE of isotropic dry etching method under low pressure before selective vapor growing. CONSTITUTION:When an SiO2 film is etched by a RIE method with resist 3 as a mask to form an opening, a damaged layer 4 is formed on the exposed Si substrate 1. Then, the resist 3 is removed, the exposed substrate 1 is isotropically etched approx. 300Angstrom by a CDE method using (CF4+O2) to remove the layer 4. Since the CDE method uses fluorine radical of low kinetic energy, damage by etching can be ignored as compared with the RIE method. Since the etching rate of Si to SiO2 in the CDE method is 20 or more, the etching of the SiO2 film 2 whole the layer 4 is removed can be ignored. Thereafter, an Si layer 5 is selectively formed in the opening.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は選択気相成長方法に関するもので、特にシリコ
ンの選択気相成長方法に使用されるものである。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a selective vapor phase growth method, and is particularly used in a selective vapor phase growth method for silicon.

(従来の技術) 選択気相成長方法は、例えばシリコン基板上に形成され
た絶縁膜の開口部にのみシリコン層を選択的に気相成長
させる方法である。
(Prior Art) A selective vapor phase growth method is a method in which, for example, a silicon layer is selectively grown in a vapor phase only in an opening of an insulating film formed on a silicon substrate.

従来、絶縁膜の開口部は主にウェットエツチング法又は
ドライエツチング法により形成されていたが、近年では
微細な開口部を形成するため異方性エツチングであるR
 I E (Reactive JonEtching
 )法が使用されることが多くなっている。
Conventionally, openings in insulating films were mainly formed by wet etching or dry etching, but in recent years, R etching, which is anisotropic etching, has been used to form fine openings.
I E (Reactive Jon Etching
) method is increasingly being used.

このRIE法は精度の高い微細加工が可能な反面、開口
部に露出したシリコン基板にダメージ層等を形成すると
いう性質をもっている。よって、RIE法で開口部を形
成した後選択気相成長前にダメージ層を除去する必要が
あり、これは異方性ウェットエツチング法により処理さ
れるのが一般的である。
Although this RIE method allows highly accurate microfabrication, it has the property of forming a damaged layer or the like on the silicon substrate exposed in the opening. Therefore, it is necessary to remove the damaged layer after forming the opening by RIE and before selective vapor deposition, and this is generally done by anisotropic wet etching.

しかしながら、異方性ウェットエツチング法は薬液を使
用するため、薬液中の不純物によるシリコン基板の汚染
や薬液に浮遊する微粒子のシリコン基板への付着等が問
題となっている。また、選択気相成長方法を用いたコン
タクト埋め込み技術が開発され、LSIの微細化に貢献
する一方で、コンタクトホールの寸法、アスペクト比は
それぞれ0.51以下、2a以上となり、コンタクトホ
ール内での薬液の置換がスムーズに行なわれずダメージ
層の除去が困難となる欠点もある。
However, since the anisotropic wet etching method uses a chemical solution, there are problems such as contamination of the silicon substrate by impurities in the chemical solution and adhesion of fine particles floating in the chemical solution to the silicon substrate. In addition, a contact embedding technology using selective vapor deposition has been developed, which contributes to the miniaturization of LSIs. However, the dimensions and aspect ratio of the contact hole are 0.51 or less and 2a or more, respectively, making it difficult to fill the inside of the contact hole. Another drawback is that the chemical solution cannot be replaced smoothly, making it difficult to remove the damaged layer.

(発明が解決しようとする課題) このように、従来はRIE法で開口部を形成した後のシ
リコン基板のダメージ層を異方性ウェットエツチング法
により除去していた。このため、シリコン基板の汚染、
シリコン基板への微粒子の付着、薬液の不十分な置換に
伴うダメージ層の除去困難等の欠点があった。
(Problems to be Solved by the Invention) As described above, conventionally, the damaged layer of a silicon substrate after forming an opening by the RIE method was removed by an anisotropic wet etching method. Therefore, contamination of the silicon substrate,
There were drawbacks such as adhesion of fine particles to the silicon substrate and difficulty in removing the damaged layer due to insufficient replacement of the chemical solution.

よって、本発明の目的は、シリコン基板の汚染等がない
とともに、微細かつ高アスペクト比の開口部においても
ダメージ層の除去を可能とする選択気相成長方法を提供
することである。
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a selective vapor phase growth method that does not cause contamination of a silicon substrate and allows removal of damaged layers even in fine and high aspect ratio openings.

[発明の構成] (課題を解決するための手段とその作用)上記目的を達
成するために、本発明の選択気相成長方法は、まず、例
えばシリコン基板上に絶縁体層を形成する。そして、R
IEを用いて前記絶縁体層にシリコン基板に達する微細
な開口部を形成する。そして、RIEによるダメージ層
を除去するため、前記シリコン基板を例えばCDE法に
より等方性エツチングする。この後、前記開口部にシリ
コン層を選択的に形成する。
[Structure of the Invention] (Means for Solving the Problems and Their Effects) In order to achieve the above object, the selective vapor deposition method of the present invention first forms an insulating layer on, for example, a silicon substrate. And R
A fine opening reaching the silicon substrate is formed in the insulating layer using IE. Then, in order to remove the layer damaged by RIE, the silicon substrate is isotropically etched using, for example, the CDE method. After this, a silicon layer is selectively formed in the opening.

また、前記半導体基板の主表面の面積に対して前記開口
部で露出する半導体基板の面積を50%以下とすれば、
ローディング効果を押えることができ、さらに効果的で
ある。
Further, if the area of the semiconductor substrate exposed at the opening is 50% or less of the area of the main surface of the semiconductor substrate,
It is possible to suppress the loading effect and is even more effective.

このような選択気相成長方法を用いれば、半導体基板の
ダメージ層は低圧の等方性ドライエツチング法により除
去でき、汚染等による選択性の劣化や選択気相成長工程
の歩留りも改善される。
If such a selective vapor phase growth method is used, the damaged layer of the semiconductor substrate can be removed by low-pressure isotropic dry etching, and the deterioration of selectivity due to contamination and the like and the yield of the selective vapor phase growth process can also be improved.

(実施例) 以下、図面を参照しつつ本発明の一実施例を詳細に説明
する。
(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

第1図(a)〜(h)は本発明の選択気相成長方法を示
している。まず、同図(a)に示すような(100)S
i  (シリコン)基板1を用意する。次に、前記Si
基板1表面に酸化又はCVD法により 1μm程度の5
i02膜2を形成する(同図(b)参照)。次に、前記
S i 02膜2上にレジスト 3を塗布する(同図(
c)参照)。次に、前記レジスト 3をE B (El
ectron Beam )描画法により部分的に除去
する(同図(d)参照)。次に、前記レジスト 3をマ
スクとしてRIE法により前記5i02膜2をエツチン
グし開口部を形成する。この時、露出した前記Si基板
1にはダメジ層4が形成される(同図(e)参照)。次
に、前記レジスト 3を除去しく同図(f)参照)、等
方性ドライエツチング法、例えばCF4+02を用いた
C D E (Chemical Dry Etchi
ng)法で露出した前記Si基板lを300人程度等方
性エツチングしダメージ層4を除去する(同図(g)参
照)。
FIGS. 1(a) to 1(h) show the selective vapor phase growth method of the present invention. First, (100)S as shown in figure (a)
i Prepare a (silicon) substrate 1. Next, the Si
A film of about 1 μm is deposited on the surface of the substrate 1 by oxidation or CVD.
An i02 film 2 is formed (see figure (b)). Next, a resist 3 is applied on the SiO2 film 2 (see FIG.
c). Next, the resist 3 is E B (El
It is partially removed using the electron beam (electron beam) drawing method (see figure (d)). Next, using the resist 3 as a mask, the 5i02 film 2 is etched by RIE to form an opening. At this time, a damaged layer 4 is formed on the exposed Si substrate 1 (see FIG. 4(e)). Next, the resist 3 is removed (see figure (f)) and isotropically dry etched using CDE (Chemical Dry Etching) using CF4+02, for example.
The exposed Si substrate 1 is subjected to isotropic etching by about 300 people to remove the damaged layer 4 (see (g) in the figure).

なお、CDE法は低運動エネルギーのフッ素ラジカルを
用いているので、RIE法と比べてエツチングによるダ
メージは無視できる。また、CDE法におけるSiと5
i02とのエツチングレート比は(S i/S i 0
2 ) =20以上であるから、ダメージ層4を除去す
る間の5iO9膜 2のエツチングも無視できる。この
後、S i H2Cjl 2 +HCfl +H2を用
いた900°C120torrの選択気相成長を行い、
開口部に51層5を選択的に形成する(同図(h)参照
)。
Note that since the CDE method uses fluorine radicals with low kinetic energy, the damage caused by etching can be ignored compared to the RIE method. In addition, Si and 5 in the CDE method
The etching rate ratio with i02 is (S i/S i 0
2) = 20 or more, the etching of the 5iO9 film 2 during the removal of the damaged layer 4 can also be ignored. After this, selective vapor phase growth was performed at 900°C and 120 torr using S i H2Cjl 2 +HCfl +H2,
51 layers 5 are selectively formed in the openings (see FIG. 5(h)).

このような選択気相成長方法によれば、ウェットエツチ
ング法を用いることなく等方性ドライエツチング法でダ
メージ層4を除去しているので、不純物汚染や微粒子に
よる影響はない。また、微細かつ高アスペクト比の開口
部に対しても、低圧のドライエツチング法によるためフ
ッ素ラジカル及び反応生成物の微細な開口部での置換は
スムーズであり、良好な気相成長が可能である。
According to this selective vapor deposition method, the damaged layer 4 is removed by isotropic dry etching without using wet etching, so there is no influence from impurity contamination or fine particles. In addition, since the low-pressure dry etching method is used for fine openings with high aspect ratios, the replacement of fluorine radicals and reaction products at the fine openings is smooth, and good vapor phase growth is possible. .

ところで、CDE法では被エツチング膜(Si基板1)
の露出面積によるエツチングレートの変化(ローディン
グ効果)が大きい。そこで、Si基板l主表面に対する
開口部で露出するSi基板lの面積比(以下「面積比」
という。)を50%以下とすることによりエツチングレ
ートのバラツキが押えられ、選択気相成長工程の一層の
歩留りの向上が達成できる。
By the way, in the CDE method, the film to be etched (Si substrate 1)
There is a large change in etching rate (loading effect) depending on the exposed area. Therefore, the area ratio of the Si substrate l exposed at the opening to the main surface of the Si substrate l (hereinafter referred to as "area ratio") is
That's what it means. ) is 50% or less, variations in etching rate can be suppressed, and further improvement in yield in the selective vapor deposition process can be achieved.

次に、本発明及び従来の気相成長方法を用いてSi層の
気相成長を行ない両者を比較検討した。まず、(100
)Si基板表面に1坤程度の5i02膜を形成し、この
5i02膜にEB描画法及びRIE法を用いて0.3μ
sから2.0坤の開口部を形成した。この後、本発明に
おいてはCF4 +o2を用いたCDE法、従来例にお
いてはアンモニア水を用いた異方性ウェットエツチング
法で露出した前記Si基板を300人程度エツチングし
た。そして、両者ともにS i H2Cp 2+HC,
l)+)(2を用いた900℃、20torrの選択気
相成長方法によりSi層が1−程度成長するように気相
成長を行なった。なお、本発明においては、面積比が4
5%のものと55%のものを用意した。
Next, a Si layer was grown in vapor phase using the present invention and the conventional vapor phase growth method, and the two were compared and studied. First, (100
) A 5i02 film of approximately one thickness is formed on the surface of the Si substrate, and a 0.3 μ
An opening of 2.0 kun was formed from s. Thereafter, about 300 people etched the exposed Si substrate using the CDE method using CF4 + O2 in the present invention, and the anisotropic wet etching method using ammonia water in the conventional example. And both are S i H2Cp 2+HC,
Vapor phase growth was performed using a selective vapor growth method at 900°C and 20 torr using l) +) (2) so that the Si layer grew to about 1-.
A 5% and a 55% version were prepared.

その結果、従来例では0.71以上の開口部にはIIA
稈度のSi層が成長していたが、0.51以下の開口部
にはSi層の成長は見られなかった。
As a result, in the conventional example, IIA
Although a Si layer with a culm degree was growing, no Si layer growth was observed in the openings with a culm degree of 0.51 or less.

また、その他の開口部においても 0.On−0,5゜
のSi層が不規則に成長していた。これは、エツチング
液がエツチング中に微細なコンタクトにおいて充分置換
されず、RIEによるダメージ層の除去が不十分となっ
たためと考えられる。これに対し、本発明では0.31
から2.0坤の開口部の全てに 1坤程度のSi層が成
長していた。また、従来例に比べt9染による選択性劣
化の発生率が1/10に低下した。さらに、面積比が4
5%のものは55%のものに比べてSi層厚のバラツキ
が1/2となった。なお、Si層厚の均一性が良くなっ
たのはローティング効果が面積比50%を境に小さくな
り、Si基板のエツチングレート均一性が向上したため
である。
Also, in other openings, 0. A Si layer of On-0.5° was growing irregularly. This is thought to be because the etching solution was not sufficiently replaced in the fine contacts during etching, resulting in insufficient removal of the damaged layer by RIE. In contrast, in the present invention, 0.31
A Si layer of approximately 1 kon was grown in every 2.0 kon opening. Furthermore, the incidence of selectivity deterioration due to t9 dyeing was reduced to 1/10 compared to the conventional example. Furthermore, the area ratio is 4
In the case of 5%, the variation in Si layer thickness was 1/2 compared to that of 55%. The reason why the uniformity of the Si layer thickness is improved is that the loading effect becomes smaller after the area ratio reaches 50%, and the uniformity of the etching rate of the Si substrate is improved.

[発明の効果] 以上、説明したように本発明の選択気相成長方法によれ
ば次のような効果を奏する。
[Effects of the Invention] As described above, the selective vapor growth method of the present invention provides the following effects.

選択気相成長前に低圧である等方性ドライエツチング法
でRIEによるダメージ層を除去しているので、シリコ
ン基板の汚染等がないとともに、微細かつ高アスペクト
比の開口部においてもダメージ層の除去が可能となった
。よって、選択性劣化の発生率の減少、選択気相成長工
程での高歩留りが可能となった。
Since the damaged layer caused by RIE is removed using a low-pressure isotropic dry etching method before selective vapor deposition, there is no contamination of the silicon substrate, and the damaged layer can be removed even from fine and high aspect ratio openings. became possible. Therefore, it has become possible to reduce the incidence of selectivity deterioration and achieve a high yield in the selective vapor phase growth process.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例に係わる選択気相成長方法を
説明するための断面図である。 ■・・・Si基板、2・・・5iO7膜、3・・・レジ
スト、 4・・・ダメージ層、 5・・・Si層。 出願人代理人 弁理士 鈴江武彦
FIG. 1 is a sectional view for explaining a selective vapor growth method according to an embodiment of the present invention. ■...Si substrate, 2...5iO7 film, 3...resist, 4...damaged layer, 5...Si layer. Applicant's agent Patent attorney Takehiko Suzue

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板の主表面に絶縁体層を形成する工程と
、この絶縁体層に半導体基板へ達する開口部を形成する
工程と、前記半導体基板をドライエッチング法により等
方性エッチングする工程と、前記開口部に半導体層を選
択的に形成する工程とを具備する選択気相成長方法。
(1) A step of forming an insulator layer on the main surface of a semiconductor substrate, a step of forming an opening in the insulator layer reaching the semiconductor substrate, and a step of isotropically etching the semiconductor substrate using a dry etching method. , selectively forming a semiconductor layer in the opening.
(2)前記半導体基板の主表面の面積に対して前記開口
部で露出する半導体基板の面積を50%以下とする請求
項1記載の選択気相成長方法。
(2) The selective vapor deposition method according to claim 1, wherein the area of the semiconductor substrate exposed through the opening is 50% or less of the area of the main surface of the semiconductor substrate.
JP63300931A 1988-11-30 1988-11-30 Selective vapor deposition method Expired - Fee Related JP2654143B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63300931A JP2654143B2 (en) 1988-11-30 1988-11-30 Selective vapor deposition method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63300931A JP2654143B2 (en) 1988-11-30 1988-11-30 Selective vapor deposition method

Publications (2)

Publication Number Publication Date
JPH02148833A true JPH02148833A (en) 1990-06-07
JP2654143B2 JP2654143B2 (en) 1997-09-17

Family

ID=17890839

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63300931A Expired - Fee Related JP2654143B2 (en) 1988-11-30 1988-11-30 Selective vapor deposition method

Country Status (1)

Country Link
JP (1) JP2654143B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100267698B1 (en) * 1992-12-16 2000-10-16 히가시 데쓰로 Etching Treatment Method and Etching Post Treatment Method and Etching Equipment

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5377169A (en) * 1976-12-20 1978-07-08 Fujitsu Ltd Production of semiconductor device
JPS5768033A (en) * 1980-10-16 1982-04-26 Toshiba Corp Manufacture of semiconductor device
JPS61224326A (en) * 1985-03-28 1986-10-06 Daikin Ind Ltd Removal of surface damage to silicon substrate
JPS6289324A (en) * 1985-10-16 1987-04-23 Nec Corp Manufacture of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5377169A (en) * 1976-12-20 1978-07-08 Fujitsu Ltd Production of semiconductor device
JPS5768033A (en) * 1980-10-16 1982-04-26 Toshiba Corp Manufacture of semiconductor device
JPS61224326A (en) * 1985-03-28 1986-10-06 Daikin Ind Ltd Removal of surface damage to silicon substrate
JPS6289324A (en) * 1985-10-16 1987-04-23 Nec Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100267698B1 (en) * 1992-12-16 2000-10-16 히가시 데쓰로 Etching Treatment Method and Etching Post Treatment Method and Etching Equipment

Also Published As

Publication number Publication date
JP2654143B2 (en) 1997-09-17

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