JPH02142291A - Digital signal processor - Google Patents

Abstract

PURPOSE:To reduce quantized noise of a chrominance signal and to make an A/D converter enough for the title processor by providing the A/D converter taking the difference of different chrominance signals and a decoder decoding the original signal from the output of the A/D converter. CONSTITUTION:A complementary color filter is formed on a sensor 101 and a driver 103 applies mixed readout in the vertical direction in the interlace scanning and the gain of the read signal is adjusted by an AGC circuit 102 and inputted to two sample-hold circuits 110, 111. Output of the A/D converter 114 is inputted to a signal processing circuit 106, in which simultaneously processing is taken and the resulting signal is converted into R-Y, B-Y signals. A luminance signal processing circuit 105 applies nonlinear conversion and filtering processing and its output is D/A-converted by a D/A converter 107. A standard video signal generator 109 receives a luminance signal, two color difference signals and a required pulse from a timing generating circuit 104 and outputs a standard video signal. Thus, quantized noise in the chrominance signal is decreased and one A/D converter is enough for the processor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal processing device suitable for color imaging means equipped with complementary color filters.

Although a video color camera will be explained below as an example, the present invention can also be effectively applied to still video cameras and the like.

[Conventional technology]

With recent advances in digital signal processing technology, digital signal processing, which has the advantages of high reliability and no adjustment, has become mainstream for video color camera signal processing circuits. On the other hand, color separation filters attached to sensors are increasingly using complementary colors rather than pure colors. This is because although pure colors have excellent color reproducibility, they have a low light utilization rate and are disadvantageous in terms of S/N and bandwidth of luminance signals.

[Problem that the invention seeks to solve]

Among these two trends, FIG. 2 shows a very general configuration example in which a single-chip color camera using complementary color filters is implemented by digital signal processing.

In the sensor 201, a complementary color filter as shown in FIG. 4 is formed for each pixel cell Ce, and signals from two vertically adjacent rows are mixed and read out, and interlaced scanning is performed for each field. do.

In this case, in the first horizontal scanning period (Mg+cy
) and (Gr+ye) signals are repeatedly read out, and the second
During the horizontal scanning period, (M g +Y e ) and (Gr+Cy) signals are repeatedly read out. This read signal is input to the A/D converter 211 via the AGC circuit 202 and the sample hold circuit 210.

Now, set the full scale of the A/D converter 211 to 0 to A m
If V and conversion accuracy is 10 bits, (Mg+C)
r) and (Gr+ye), (MgYe), (Gr+Cy
) It is considered that random quantization noise of - is superimposed on each signal of Δ.

The luminance signal is basically this read signal (Mg+Cy
), (Gr1Ye), (Mg+Ye),' (Gr1C
y), the magnitude of the quantization Δ noise that occupies the luminance signal is approximately -. This luminance signal is subjected to γ correction etc. in the luminance signal processing circuit 205, and then D/A
The signal is input to the NTSC encoder 209 via the converter 207.

On the other hand, the color signal is obtained by subtracting the output of the A/D converter 211 from the subtracter 21.
2, once (Mg+Cy) (Gr×Ye) or (M
After forming the color difference into the form g + Ye) - (Gr + Cy), the color signal processing circuit 206 performs color processing. In other words,
The color signal component is modulated into the luminance signal component, and the ratio of the color signal component to the luminance signal component is usually 20.
~30% or less. This means that the color signal processing circuit 206 must ultimately apply a gain of 3 to 5 times to the original signal in order to obtain a color signal of a sufficient level. Therefore, the magnitude of quantization noise in the color signal is 3 to 5 times that of the luminance signal, and on the order of 3Δ to 5Δ. Thereafter, the output of this color signal processing circuit 206 is D/
The signal is passed through the A converter 208 and combined with the luminance signal by the NTSC encoder 209 to form an NTSC signal. Therefore, in such a configuration, the S/N of the final color signal is
In order to ensure the ratio, the number of bits of the A/D converter 211 must be at least 12 bits, resulting in a significant increase in cost and power consumption.

To solve this problem, as shown in Figure 3, A/D
Two converters are provided, one of which takes the difference in advance with a differential amplifier 313, adjusts the gain, and then performs A/D conversion, and the result is used as a color difference signal, and the other is a sample hold circuit 31.
An A/D converter 315 performs A/D conversion at the full scale corresponding to the output sampled and held at 0.311,
A method of forming a luminance signal is also conceivable. Note that, for example, when the read clock is fc, the sample and hold circuits 310 and 311 each have a cycle of 2/fc, and the phases are inverted from each other. This configuration improves the deterioration of the S/N ratio of the color signal due to quantization noise, but the A/D converter
pcs are required.

In particular, when the signal is linear, the A/D converter 315 for the luminance signal is required to have a precision of at least 10 bits (at least 8 bits even if non-linear processing such as blenny is performed immediately before), which increases the circuit scale. This led to high costs.

[Means for solving problems]

In view of the above problems, the present invention takes the difference between different color signals.
By having two A/D converters and a decoder that decodes the original signal from the output of this A/D converter, the quantization noise of the color signal is low and only one A/D converter is required. This realizes a signal processing device.

[Effect]

Also, by doing this, the quantization noise in the decoded luminance signal will be on the same level as the quantization noise in the difference signal, so
For example, just by having one 8-bit A/D converter, it is possible to equimetrically obtain an accuracy of 8 bits or more (usually 9 to 10 bits) in the decoded luminance signal.

〔Example〕

FIG. 1 shows a block diagram of signal processing of a video camera to which the present invention is applied. The sensor 101 is, for example, a CC
D image sensor, on which a complementary color filter as shown in FIG. 4 is formed, for example, and a second. Mixed readout is performed in the vertical direction by ink-lace scanning similar to the conventional example shown in the third figure.

The read signal has its gain adjusted by the AGC circuit 102, and is then sent to two sample and hold circuits 110. 111. Sample and hold circuit 110. Each pulse PI is sent to Ill from the timing generation circuit 104.

F2 is supplied. ○ in Figure 8 (b) and (C)
As shown by the mark, PIF2 is synchronized with the sensor readout clock fc at a cycle twice as large as that, and the phases thereof are opposite to each other.

In addition, Fig. 8 (a), (b), (c), and (d) are respectively A.
Output of GC circuit 102, sample hold circuit 110.
111 is a schematic diagram of the output of the output differential amplifier 112.

The scale is time T'''C' T = 1 / f c. Also, in (b) and (C), the Q mark indicates the pulse PIF2.
The timing of the pulses at which the A/D converter 114 operates is shown in (e).

In this way, for example, in the first horizontal scanning period, the outputs of the sample and hold circuits 110 and ll are each (Mg
+Cy) and (Gr+Ye), and in the second horizontal scanning period, they become (Mg+Ye) and (Gr+Cy), respectively. Therefore, sample and hold circuit 110. The output of the differential amplifier 112 connected to 111 is as follows, where K is the gain.

The A/D converter 114 is an 8-bit A/D converter with a conversion range of -A/2 mW - A/2 mV, -A/2 to -
Input in the range of A/2 + Δ to O, (A/2 - Δ) to (A/
2) Convert input in mV range to 1023.

However, Δ=A/256 mV.

Of course, a level shifter or the like may be provided before the A/D converter to set the input range from 0 to A mV.

Now, set the maximum value of the output of S/H110 and S/H111 to V
Set to max. The possible values of the output of the differential amplifier 112 are in the range of -KV to KV mV.

However, if you actually examine the histogram of the output at point A, although the colors are different, there is a horizontal correlation in luminance between the differences between horizontally adjacent signals, so it is usually between -αKV and αKV.
It will be in the mV range. α is smaller than l and is approximately 115.

Follow, a, K, V, A are αKV=A/2 (7)
If the relationship is satisfied, the full scale of the A/D converter 114 is effectively used. However, although it is very rare,
In rare cases, the output of point A is less than 1 αKV or αKV
Since it may become even larger, the clipping circuit 113 clips the output within the range of 1 KV to αKV. The closer α is to 1, the smaller the error in the decoder 115 (described later) will be, but the more the color quantization error will be, so it is desirable to set it to an appropriate value. Note that the clip circuit 113 is not required if accuracy is not required.

The output of the A/D converter 114 is input to the color signal processing circuit 106 configured as shown in FIG.
-Y, B-Y.

Next, a configuration example of the color signal processing circuit 106 will be explained using FIG.

The output of the A/D converter 114 is input to an IH memory 501 and a constant multiplier 503. For example, when the input to the LH memory 501 is a signal corresponding to P, the input to the LH memory 502 is Q1, and the output is a signal corresponding to P.

Therefore, if the constants of the constant multipliers 503 and 505 are set to 1/2 and the constant of the constant multiplier 504 is set to 1, the outputs of the adders 506 and 504 will have P and Q alternately and different from each other for each IH. It is expressed in phase. Therefore, switch these
07, and by switching this and each IH, the output of Q is always obtained from P1 to O, and P and Q are made simultaneous.

In the case of a color filter array as shown in Figure 4, P = [(Mg
+Cy) −(Gr+Ye)] ]=2B−G,zB−
YQ=[(Mg+Ye) −(Gr+Cy)] ]=2
Since it is considered as B-G--R-, constant multiplier 508.50
9.511.512, and the dye matrix circuit consisting of adders 510 and 513 may not be necessary, but in order to obtain better color reproduction, the constants set from 509 to 512 should be set according to the spectral characteristics of the color filter. It is preferable to let them decide.

Further, the color difference gain may be adjusted using these constants. Next, the color difference signals R-Y and B-Y are D/A converted by the D/A converter 108, and the standard television signal generator 1
09.

Next, the operation of the decoder 115 will be explained.

Now, consider the horizontal scanning period in which Mg+CyGr+Ye are repeatedly scanned using the filter arrangement shown in FIG.

Here, the signal (Vn) to be demodulated is V, =Mgl +Cyl, V2=Gr, +Ye,
, V3=Mg2+Cy2.

It is...

Now, considering the signal (Un) determined by Un=Vn++-vn, U H= (Gr H+Ye H) (Mg r +
CyI)U2=(Mg2+Cy2)−(Gr,+Y
eI)U3 = (Gr2+Ye2)-(Mgz 1C
y2)...(3)

On the other hand, the output (pn) of the A/D converter 114 is P I=
(Mg 1 +cyI) −(Gr, +Ye
H) P2=(Mg2+Cy2) (Gr, +Ye,)
Ps ” CMgz +CY2) (Gr2 +Ye
2)...(4) Therefore, Un= (-1)'Pn...(5).

From (2) Because it is becomes.

Therefore, from (6), Vk-Vk-+ = (-1)' Ph
"e" (7), so Vk = (gkpk + Vk - 1am - book a * (B)
becomes. Decoding is performed according to this equation (8).

FIG. 6 shows an example of the configuration of the decoder. The output of A/D converter 114 is input to switch 602 and sign inverter 601. The switch 602 uses a clock φ synchronized with the pixel reading clock supplied from the timing generation circuit 104.
Select inverted output or non-inverted output. The output of the switch 602 is added to its own output delayed by one pixel in an adder 603. The calculation accuracy of the adder 603 is 2 to 4 bits higher than the bit accuracy of the A/D converter.
It is desirable to increase the precision by about t to io to 12 bits and to configure it so that overflow or underflow does not occur.

Also, the output of 603 is l/α times the maximum value of the output of A/D converter 114 (α is the constant described above), but since 10 bits or more is sufficient for the luminance signal circuit in the subsequent stage, shift circuit 605 - The bits may be regularly shifted to the right by 0 to 2 bits. By doing this, the brightness of the A/D converter is 8 bits, but the brightness signal is isometrically 1 bit.
The same effect as quantization with a precision of 0 bit or more is suffered.

The luminance signal processing circuit 105 performs nonlinear transformations such as Knee transformation and γ transformation, and filtering processing such as low-pass filtering and aperture compensation, and its output is D.
A/A converter 107 performs D/A conversion. The standard television signal generation device fi 109 supplies a luminance signal, two color difference signals, and necessary pulses from the timing generation circuit 104 to generate and output a standard television signal.

[Other Examples]

FIG. 7 shows a second embodiment of the invention.

The first embodiment has a simple configuration, but the clip circuit 1
13 and A/D converter 114 are large,
It is possible that this effect will propagate within a certain range. Therefore, when high image quality is the objective, it is preferable to construct a decoder using the portion 713 surrounded by a dotted line as shown in FIG. 7 and put it into a feedback loop.

The output from the AGC circuit 702 is sampled and held in a sample and hold circuit 720 at the same cycle as the sensor read clock fc. Differential amplifier 710 amplifies the difference between the output from sample hold circuit 720 and the output from D/A converter 717 provided in the feedback system by an appropriate gain.

This output is clipped by a clip circuit 711,
It is input to A/D converter 712. The settings of the gain, clip level, and range of the A/D converter may be the same as in the previous embodiment.

Next, the output of the A/D converter 712 is delayed by a delay circuit 714, and then sent to a delay circuit 716 and an adder 715.
is input to a decoder consisting of The output of adder 715 is D
A/A converter 717 performs D/A conversion.

This behavior will be analyzed below.

The signal from S/H710 is rVr, ), differential amplifier 71
0 [y n ], A/D converter 71
The output from 2 is (Unl, the output from adder 715 and (
X, l).

The output from the D/A converter 717 is assumed to be [xn').

The A/D converter 712 operates in the same synchronization as the read clock fc, (Unl, (xn) is digital data for each clock, (vn), rynl, (x
n'l is the analog data value at the corresponding time.

Therefore, Yn = Vnxn' Un = Yn - Qn (9) Xn''Un Xn-1. However, Qn is the error of the clip circuit 71M: A/D converter 712. If the error in is very small, then Xn=Xn, so Yn=V
n Xn tyn = yn + Qn (1
0)
1)X (Z) = Z-' U (Z) + Z-'
From X (Z) (11), y (z), v (z
), X(Z)=Z−' (v(z)+Q(
Z)) (12) Also, from (11), y (
z), X (Z), then U(Z) = (1-Z
-') (V(Z)+Q(Z)) (13). Also, Y(Z)=(1-Z-') v(z)-Z-'Q(Z)
(14).

In other words, X (Z) is the original signal (Vn) to which quantization noise [Qnl has been added, delayed by 14 days, so if this is input as is to the luminance signal processing circuit 705, it will be processed later. may be the same as in the previous embodiment.

From (14), (yn) is the difference between two different color signals. Therefore, in this embodiment as well, the difference between horizontally adjacent color signals is A/D converted. This result (Un) is shown in equation (3) of the previous example (Ur
l] is the same as. However, in order to match the phase with the luminance signal, the output of the delay circuit 714 is considered as [Unl, and this is input to the switch 719 and the inverter 718.

The switch 719 selects the output of 714 and the output of 718 for each clock fc, and the output of 719 is expressed by the formula (4
) is (pn).

Therefore, it is sufficient to input this as it is to the color signal processing circuit 706 and process the rest in the same manner as in the previous embodiment.

In addition, the D/A converter 717 has a bit number of 2 to 3 bits or more than that of the A/D converter 712 in order to make xn and It is desirable to use one with high accuracy.

In other words, in this embodiment, as in the previous embodiment, a signal corresponding to the difference between different color signals is A/D converted, and a color signal is formed based on this, while a color signal is formed from this A/D converted result. By decoding the luminance signal using a decoder, the S/N of the luminance and color signals is improved.

In the above description, the color filter array was explained using the case shown in FIG. 4 as an example, but other so-called complementary color mosaic filters are also applicable. Also of course Cy
, G, Ye, etc. arranged in a stripe pattern, or any type of stripe that performs color signal processing from the color signal difference or modulation component and forms a luminance signal from the baseband component. However, the present invention is effective.

〔Effect of the invention〕

According to the present invention, since the difference between different color signals is calculated in a -degree analog state and then A/D conversion is performed, quantization noise in the color signal can be reduced, and the original signal can be extracted from this difference signal. Since the signal is decoded to form a luminance signal, A/D
Only one converter is required, the quantization noise of the luminance signal can be reduced, and the circuit scale and cost can also be reduced.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, FIGS. 2 and 3 are diagrams showing a conventional example, FIG. 4 is a diagram showing an arrangement of color filters, and FIG. 5 is a configuration example of a color signal processing circuit. 6 is a diagram showing an example of the configuration of a decoder, FIG. 7 is a diagram showing another embodiment of the present invention, and FIG. 8 is a diagram explaining the operation of the first embodiment. 112.710...Differential amplifier, 113.711...Clip circuit, 114.712...A/D converter, 611.718...Inverter, 602.719...Switch, 603.715...Adder, 604.716...Delay, 605...Shifter, 717...D/A converter.

Claims (3)

[Claims] (1) A color imaging means using a complementary color filter and a signal corresponding to the difference between different color signals from the color imaging means.
an A/D converter that performs A/D conversion; a color signal processing means that forms a color signal using the output of the A/D converter;
A digital signal processing device comprising: a decoder that decodes an original color signal from the output of the converter; and a luminance signal processing device that uses the output of the decoder to form a luminance signal. (2) Differential amplification whose input is the output of two sample-and-hold circuits that operate so that the signal corresponding to the difference in color signals has a cycle twice as long as the readout clock of the color imaging means and whose phases are inverted from each other. The digital signal processing device according to claim 1, wherein the digital signal processing device is formed using a device. (3) A signal corresponding to the difference between the color signals is inputted with a digital signal decoded by a decoder from the output of the sample hold circuit having the same cycle as the readout clock of the color imaging means and the output of the A/D converter. The digital signal processing device according to claim 1, wherein the digital signal processing device is formed using a differential amplifier that receives as input the output of a D/A converter.