JPH02142122A - Manufacturing method of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor device manufacturing technology, and in particular to embedding of contact holes that connect a semiconductor substrate and wiring, and through holes that connect wiring between upper and lower layers. It's about technology.

[Conventional technology]

Conventionally, aluminum (
Aβ) is used.

However, as semiconductor integrated circuits become more highly integrated and interconnects become finer, contact holes are created to connect semiconductor substrates and interconnects, and connections between interconnects in upper and lower layers are created. As a result of the increase in the aspect ratio (depth/diameter of the connection hole) of the through-hole, a reduction in step coverage of the conductive film for wiring inside the connection hole becomes a serious problem.

As a countermeasure, conventionally proposed methods are to bury a conductive film such as a high melting point metal, its silicide, or polysilicon in the connection hole, and connect the wiring and the semiconductor substrate (or underlying wiring) through this conductive film. It is a technology that connects

A selective CVD method or an etch-back method is used to fill the contact holes with these conductive films. Regarding the connection hole embedding technology using high melting point metal, for example, "Solid State Technology (Solid State Technology)"
technology).

Japanese edition, February 1986 issue, “Tungsten selection process by low pressure CVD” (E, K, Broadb
ent, W, T, 5tacy) J.

[Problems to be Solved by the Invention] However, according to the studies of the present inventors, the above-mentioned connection hole embedding technique has the following problems.

7 and 8 show a semiconductor substrate in which wiring is connected over a contact hole filled with a conductive film, and in the figure, 20 is a semiconductor substrate made of silicon single crystal;
21 is a diffusion layer formed on this semiconductor substrate 20. An insulating film 22.23 made of, for example, SiO2 is deposited on the semiconductor substrate 20, and a connection hole 24 is formed in the insulating film 22.23 above the diffusion layer 21.

A conductive film 25 made of tungsten (W) or the like deposited by selective CVD, for example, is buried inside the connection hole 24, and a wiring 26 made of, for example, an Af gold alloy is connected to the conductive film 25. has been done.

In order to connect the wiring 26 above the connection hole 24, the insulating film 23 is
After a conductive film for wiring is deposited on top using the Svanta method, for example,
This wiring conductive film is etched using a photoresist mask. At this time, a margin for misalignment between the connection hole 24 and the photoresist mask is required, so in the prior art, a wide flange 27 is provided on the wiring 26 above the connection hole 24.

However, when the flange 27 is provided on a part of the wiring 26, the line width of the wiring 26 becomes thicker, which poses a problem in that miniaturization of the integrated circuit is hindered.

On the other hand, if an attempt is made to reduce the line width of the wiring 26 by eliminating the flange 27, when etching the conductive film for the wiring, misalignment with the photoresist mask will occur, causing the flange 27 to be buried in the inside of the connection hole 24 in advance. A part of the surface of the etched conductive film 25 is etched together with the wiring conductive film. At this time, the inventor has proposed that if the inner wall of the contact hole 24 is opened perpendicularly to the main surface of the semiconductor substrate 20 as shown in FIG. Since a gap (S) is likely to occur at the interface between the conductive film 25 and the conductive film 25,
Even the lower diffusion layer 21 is over-etched through this gap (S), and the conductive film 25 and the diffusion layer 21 are over-etched.
It has been found that problems occur such as poor conduction between the integrated circuit elements and deterioration of the electrical characteristics of the integrated circuit elements.

The present invention has been made by focusing on the problems of the connection hole embedding technique described above, and its purpose is to improve the connection reliability of connection holes in which a conductor 74 film is embedded, and to improve the manufacturing yield of semiconductor devices. The goal is to provide technology that can improve the

Another object of the present invention is to achieve the above-mentioned objects, and to achieve a high degree of integration of semiconductor devices by miniaturizing the wiring connected above the connection hole filled with a conductive film. Our goal is to provide the following.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Among the inventions disclosed in this application, a brief overview of typical inventions is as follows.

That is, the invention according to claim 1 provides a method for forming a connection hole in a part of an insulating film on a semiconductor substrate, burying a conductive film inside the connection hole, and then connecting a wiring on the conductive film. A method for manufacturing a semiconductor device including the step of providing a large diameter portion in a part of the contact hole, embedding a conductive film inside the contact hole using a selective CVD method, and adjusting the film thickness of the conductive film. is made thicker than the height from the bottom of the connection hole to the large diameter portion.

The invention according to claim 2 is a method for manufacturing a semiconductor device, in which a conductive film is buried inside the contact hole using an etch-back method instead of the selective CVD method.

A third aspect of the invention is a method for manufacturing a semiconductor device, in which the line width of the wiring is equal to or smaller than the diameter of the bottom of the connection hole.

A third aspect of the invention provides a method for manufacturing a semiconductor device, in which the insulating film is composed of a plurality of insulating films having different etching rates.

[Effect]

According to the invention described in claims 1 and 2, when forming a wiring by etching the conductive film for wiring deposited on the connection hole, only the conductive film in the large diameter portion is etched inside the connection hole. Therefore, even if a gap is formed at the interface between the inner wall of the contact hole and the conductive film, the underlying diffusion layer will not be over-etched through this gap.

According to the third aspect of the invention, even if the wiring connected above the connection hole is miniaturized, the connection reliability of the connection hole can be ensured, so there is no need to provide a flange on the wiring.

According to the fourth aspect of the present invention, the opening of the connection hole and the formation of the large diameter portion can be performed simultaneously by the -degree etching, so that the throughput of the step of forming the large diameter portion is improved.

[Example 1] Fig. 1 is a sectional view of a main part of a semiconductor substrate showing a semiconductor device which is an embodiment of the present invention, and Figs. 2(a) to 2(a) show a method for manufacturing this semiconductor device. FIG. 2 is a sectional view of a main part of a semiconductor substrate.

In FIG. 1, a semiconductor substrate l is made of, for example, a p-type silicon single crystal, and has, for example, an n-type diffusion layer 2 formed on a part of its main surface. On the semiconductor substrate 1, for example, S
A field insulating film 3 made of 02 is formed, and in an element formation region (not shown) surrounded by this field insulating film 3, integrated circuit elements such as MOS/FET are formed. An insulating film 4a made of, for example, SiO□ is formed on the field insulating film 3, and the integrated circuit element is covered with this insulating film 4a.

Above the diffusion layer 2, a field insulating film 3 and an insulating film 4a are provided.
A connection hole (contact hole) 5a is formed. The lower region of the connection hole 5a is perpendicular to the main surface of the semiconductor substrate l, and the diameter of the lower region is as follows.
For example, it is 0.5 μm. Further, a tapered large diameter portion 6a is provided in the upper region of the connection hole 5a.

A conductive film 7a made of a high melting point metal such as tungsten (W) is buried inside the connection hole 5a. The conductive film 7a is embedded so that its thickness is greater than the height from the bottom of the connection hole 5a to the large diameter portion 6a.

For example, an aluminum alloy (Af-3
A first layer wiring 8a made of i-Cu) is connected thereto. The line width of this wiring 8a is the same as the diameter of the lower region of the connection hole 5a, for example, 0.5 μm, and no flange is formed.

On the wiring 8a, for example, B P S G (Boro
Phospho 5ilicate Glass)
An interlayer insulating film 9 is formed, and a second layer wiring 10 made of, for example, an aluminum alloy is formed thereon. On the wiring 10, for example, PSG (Pho
spho 5ilicate GlaSS) and 513N
4 is formed to protect the integrated circuit from the external environment.

Next, the process of forming the contact hole 5a and the wiring 8a of the semiconductor device will be explained with reference to FIGS. 2(a) to 2(a).

In FIG. 2(a), for example, 51
This shows a state in which an insulating film 4a made of 0.02 is deposited by the CVD method.

Thereafter, first, a photoresist mask 12 for connection holes is formed on the insulating film 4a (FIG. 2Q)).

Next, a hole is formed in a part of the insulating film 4a by isotropic etching using, for example, a 5% hydrofluoric acid aqueous solution to form a large diameter portion 6a (FIG. 2(C)).

Subsequently, holes are formed perpendicularly in the insulating film 4a below the large diameter portion 6a and in the field insulating film 3 below the large diameter portion 6a by reactive ion etching using, for example, a parallel plate type dry etching device, and then holes are formed in the semiconductor substrate l. A connecting hole 5a is formed to reach the connecting hole 5a. The reaction gas used is, for example, CHF3. C.F.
It is a fluorocarbon gas such as C, F6 (
Figure 2(d)).

Thereafter, n-type impurity ions such as phosphorus (P) and arsenic (As) are implanted into the surface of the semiconductor substrate l to form an n-type wave dispersion layer 2 on the semiconductor substrate l below the connection hole 5a.
Figure 2(e)).

Next, for example, W Fe and a silane compound S r n F12n-2 (n=1.2
．． , , ) or W F s
A conductive film 7a made of W is embedded inside the connection hole 5a by a low-pressure CVD method using a reactive gas made of a mixed gas of SiCβ2H2 and SiCβ2H2 (FIG. 2(f)). At this time, the conductive film 7
The film thickness of a must be thicker than the height from the bottom of the connection hole 5a to the large diameter portion 6a.

Subsequently, a conductive film 13 for wiring made of an aluminum alloy (An-3i-Cu) is deposited on the semiconductor substrate 1 by, for example, sputtering, and then a photoresist mask 14 for wiring is deposited on the conductive film 13 for wiring. Form (Figure 2 ((a))
.

Next, the wiring conductive film 13 is sputter-etched to connect the wiring 8a over the connection hole 5a (FIG. 2, 01). At this time, if the line width of the wiring 8a is equal to or less than the diameter of the bottom of the connection hole 5a, even if there is a slight misalignment between the connection hole 5a and the photoresist mask 14,
As shown in the figure, the surface of the conductive film 7a buried inside the connection hole 5a is sputter-etched. However, in the first embodiment, the large diameter portion 6a is located in the upper region of the connection hole 5a.
Because of this, only the conductive film 7a in the large diameter portion 6a is spuck-etched, and the conductive film 7a in the lower region is not spack-etched.

Therefore, even if a gap is formed at the interface between the inner wall of the lower region of the connection hole 5a and the conductive film 7a, even the lower diffusion layer 2 will not be over-etched through this gap.

As described above, according to the first embodiment, the following effects can be obtained.

(1) A large diameter portion B6a is provided in the upper region of the connection hole 5a, and a large diameter portion 6a is provided inside the connection hole 5a from the bottom.
By embedding the conductive film 7a which is thicker than the height of the conductive film 7a, the diffusion layer 2 will not be over-etched when the wiring conductive film 13 is sputter-etched to form the wiring 8a.

As a result, poor conduction between the conductive film 7a and the diffusion layer 2,
Since deterioration of the electrical characteristics of the integrated circuit element can be reliably prevented, the reliability of the connection between the diffusion layer 2 and the wiring 8a connected via the conductive film 7a is improved, and the manufacturing yield of semiconductor devices is improved. .

(2) According to (1) above, connection reliability between the diffusion layer 2 and the wiring 8a connected via the conductive film 7a is ensured even without providing a flange on the wiring 8a connected above the connection hole 5a. Therefore, the wiring 8a can be made finer by that amount, and higher integration of semiconductor integrated circuits can be realized.

[Embodiment 2] FIG. 3 is a sectional view of a main part of a semiconductor substrate showing a semiconductor device according to another embodiment of the present invention, and FIGS. 4(a) to (e) show a method for manufacturing this semiconductor device. FIG. 2 is a cross-sectional view of a main part of the semiconductor substrate shown in FIG.

In FIG. 3, a semiconductor substrate 1 is made of, for example, a p-type silicon single crystal, and has, for example, an n-type diffusion layer 2 formed on a part of its main surface. A field insulating film 3 made of, for example, 5102 is formed on the semiconductor substrate 1, and integrated circuit elements such as MOS/FET are formed in an element formation region (not shown) surrounded by this field insulating film 3. .

An insulating film 4a made of, for example, 5i02 is formed on the field insulating film 3, and the integrated circuit element is covered with this insulating film 4a.

A second insulating film 4b is laminated on the insulating film 4a. The insulating film 4a and the insulating film 4b are made of materials with different etching rates, and when the insulating film 4a is 8102, the insulating film 4b is made of, for example, SOG (Spin On
Glass).

Above the diffusion layer 2, a field insulating film 3 and an insulating film 4a are provided.
, 4b are formed. The connecting hole 5b is opened so that its cross section is stepped, and its upper region is a large diameter portion 6b. Connection hole 5b
A conductive film 7b made of, for example, low-resistance polysilicon is embedded inside. The conductive film 7b is embedded so that its thickness is greater than the height from the bottom of the connection hole 5b to the large diameter portion 6b.

For example, an aluminum alloy (Affi
-5i-Cu) is connected to the first layer wiring 8a. In order to improve the migration resistance of the wiring 8a, for example, metal silicide (
A thin barrier metal layer 8b made of (WS i, Mo Si□, etc.) is formed. The line width of the wiring 8a and the barrier metal layer 8b is, for example, 0.5 μm, which is the same as the diameter of the lower part of the connection hole 5b, and no flange is formed.

An interlayer insulating film 9 made of BPSG, for example, is formed on the wiring 8a.
is formed, and a second layer wiring IO made of, for example, an aluminum alloy is formed thereon. A passivation film 11 made of two layers of PSG and 813N4, for example, is formed on the wiring 10 to protect the integrated circuit from the external environment.

Next, the process of forming the connection hole 5b and the wiring 8a of the semiconductor device will be explained with reference to FIGS. 4(a) to 4(e).

FIG. 4(a) shows that, for example, Si is formed on the field insulating film 3.
The figure shows a state in which an insulating film 4a made of O□ is deposited by the CVD method, and then an insulating film 4b made of SOG is deposited on this insulating film 4a using, for example, a spinner.

After that, first, a photoresist mask 12 for a contact hole is formed on the insulating film 4b, and then the insulating films 4a, 4b and the field insulating film 3 are opened by wet etching using, for example, a 5% hydrofluoric acid aqueous solution to form a contact hole. Form 5b. At this time, the insulating film 4b made of SOG has a higher etching rate than the insulating film 4a made of 5102 and the field insulating film 3, so it is quickly etched, and the upper region of the connection hole 5b (the region where the insulating film 4b is removed) is etched. ) is formed with a large diameter portion 6b (FIG. 4 (5)).

Next, n-type impurity ions such as phosphorus (P) and arsenic (ΔS) are implanted into the surface of the semiconductor substrate l, and the connection holes 5
After forming the n-type scattering layer 2 on the semiconductor substrate 1 below b,
For example, a conductive film 7b made of low-resistance polysilicon is deposited on the insulating film 4b by a CVD method using a reactive gas made of a mixed gas of S + 84, H2, and P H3 (or As H3). Figure 4(C)). At this time, since the connection hole 5b has a step-shaped cross section and a large diameter portion 6b in the upper region, the conductive film 7b can be completely buried inside the connection hole 5b even if the aspect ratio is large. Can be done.

Next, the conductive film 7b on the insulating film 4b is removed by an etch-back method, leaving the conductive film 7b inside the contact hole 5b (FIG. 4(d)). To etch back the conductive film 7b, for example, Reactive ion etching using a parallel plate dry etching device is used.

Thereafter, a barrier metal and a wiring conductive film are sequentially deposited on the insulating film 4b by, for example, sputtering.

The barrier metal is, for example, WS '2+ Mo Si2
The conductive film for wiring is, for example, an aluminum alloy.

Next, a photoresist mask 1 for wiring is applied on the conductive film for wiring.
4, the conductive film for wiring and the barrier metal are sputter-etched to connect the wiring 8a over the connection hole 5a via the barrier metal layer 8b (FIG. 4(e)). At this time, if the line widths of the barrier metal layer 8b and the wiring 8a are equal to or less than the diameter of the bottom of the connection hole 5b, even a slight misalignment between the connection hole 5b and the photoresist mask 14 may occur as shown in the figure. As shown, the connection hole 5b
The surface of the conductive film 7b buried inside is sputter etched. However, in the second embodiment, the connection hole 5
Since the large diameter portion 6b is provided in the upper region of b, only the conductive film 7b in the large diameter portion 6b is sputter etched, and the conductive film 7b in the lower region is not sputter etched.

In other words, even if a gap is formed at the interface between the inner wall of the lower region of the connection hole 5b and the conductive film 7b, the spreading layer 2 below is not over-etched through this gap. The same effect as 1 can be obtained.

In addition, in this embodiment 2, since the insulating film 4b having a higher notching rate than the insulating film 4a is deposited on the insulating film 4a, the opening of the connecting hole 5b and the thickness can be formed by etching at -degrees. As a result of being able to form the diameter portion 6b at the same time, the throughput of the step of forming the large diameter portion 6b is improved in addition to the above-described effects.

Furthermore, since the insulating film 4b made of SOG is deposited on the insulating film 4a, the surface of the insulating film 4a is flattened, and the reliability of the wirings 8a and 10 formed above it is improved.

The invention made by the present inventor has been specifically explained based on Examples above, but the present invention is not limited to Examples 1 and 2, and can be modified in various ways without departing from the gist thereof. Needless to say.

In the above examples, when providing a large diameter portion in a part of the connection hole, a part of the inner wall of the connection hole was processed into a tapered shape (Example 1) or a step shape (Example 2). For example, as shown in FIG. 5, a part of the inner wall of the connection hole 5C may be formed into a reverse tapered shape to provide a large diameter portion 6C, or as shown in FIG. After processing a part of the hole 5d into a tapered shape, it is processed into a reverse tapered shape to form a large diameter portion 6d.
It is also possible to set up

Further, in Example 1.2, the case where an Af gold alloy was used as the conductive film material for wiring was explained, but the material is not limited thereto. N or the like may also be used.

Furthermore, in Example L2, the case where the application is applied to a contact hole connecting the diffusion layer of the semiconductor substrate and the wiring is explained, but it is also applicable to the connection hole (through hole) connecting between the wiring in the upper and lower layers. You can also.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects obtained by typical inventions are briefly described below.

That is, according to the invention described in claim 1.2, when forming a wiring by etching the conductive film for wiring deposited over the connection hole, over-etching of the diffusion layer below can be prevented. , the connection reliability of the connection hole filled with the conductive film is improved, and the manufacturing yield of semiconductor devices is improved.

Furthermore, according to the invention as claimed in claim 3, it is possible to eliminate the flange of the wiring connected above the connection hole, so that the wiring can be made finer and higher integration of the semiconductor device can be realized. .

According to the invention as set forth in claim 4, it is possible to form the connecting hole and the large diameter portion at the same time by etching at -degree. The throughput of the process is improved.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part of a semiconductor substrate showing a semiconductor device which is an embodiment of the present invention, and FIGS. 3 is a sectional view of a main part of a semiconductor substrate showing a semiconductor device according to another embodiment of the present invention, and FIGS. 5 and 6 are cross-sectional views of main parts of a semiconductor substrate showing a method for manufacturing a semiconductor device according to another embodiment of the present invention. FIG. FIG. 8 is a schematic plan view of this semiconductor device, and FIG. 9 is a sectional view of essential parts of a conventional semiconductor device. 1.20... Semiconductor substrate 1.2° diffusion layer, 3... Field insulating film, 22.23= - Insulating film, 5a, 5b. d, 21...Connection hole, 5a, 6b, large diameter portion, 7a, 7b, 25=8a, 10.26-wiring, 3b-metal layer, 9...interlayer insulating film, 11/basion film, 12. 14... Homask, 13... Conductive film for wiring, 2 21... 4a, 4b c 5 i3c, 6d - Conductive film, ... Barrier l Barat resist 7... Flange, S - Gap.

Claims (1)

[Claims] 1. A step of forming a contact hole in a part of an insulating film on a semiconductor substrate, burying a conductive film inside the contact hole, and then connecting wiring onto the conductive film. A method of manufacturing a semiconductor device comprising: providing a large diameter portion in a part of the connection hole;
A method for manufacturing a semiconductor device, characterized in that a conductive film is buried inside the contact hole using a method, and the thickness of the conductive film is made thicker than the height from the bottom of the contact hole to the large diameter portion. . 2. The method of manufacturing a semiconductor device according to claim 1, characterized in that, instead of the selective CVD method, an etch-back method is used to bury a conductive film inside the connection hole. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the line width of the wiring is equal to or smaller than the diameter of the bottom of the connection hole. 4. The method of manufacturing a semiconductor device according to claim 1, 2 or 3, wherein the insulating film is composed of a plurality of insulating films having mutually different etching rates.