JPH02136966A - Clock stop control method using machine check - Google Patents

Abstract

PURPOSE:To improve the processing efficiency of the vector instructions of scalar units which are processed in parallel with each other by preventing such a case where the clock is stopped even at an excessive circuit part despite a machine check produced within a vector unit which is shared by plural scalar units. CONSTITUTION:In the case a machine check is produced by an error, etc., in a vector unit which is shared by the scalar unit SU0 and SU1, the clock is stopped only at a least and necessary circuit part without stopping the clock in the unit 14 as a whole. While the execution of the vector instructions are carried on as long as possible at the circuit parts having no relation with the factor of the machine check. Thus the processing efficiency of vector instructions can be improved for the scalar units which are processed in parallel with each other.

Description

[Detailed Description of the Invention] [Summary] Regarding the clock stop control method when a machine check occurs in a vector unit shared by a plurality of scalar units, the influence of a clock stop on the processing of vector instructions that are being processed in parallel but do not cause any problems. The circuit in the vector unit is divided into a common circuit part that is commonly used by vector instructions from all scalar units and a unique circuit part that is unique to the vector instructions of each scalar unit. A common circuit busy signal indicating that the above common circuit part is actually used is provided for each SCARA unit.
In addition, a machine check generation signal indicating that a machine check or z7 error has occurred is provided for each of the common circuit portion and the unique circuit portion, and the combination of the common circuit busy signal and the machine check generation signal detects the circuit portion where the clock should be stopped. It was configured to determine.

[Industrial application field]

The present invention relates to a clock stop control method when a machine check occurs in a vector unit shared by a plurality of scalar units.

There is a multiprocessor system in a scientific computer that includes a plurality of scalar units that process scalar instructions and one vector unit that is coupled to each scalar unit and processes vector instructions sent out by the scalar units at high speed.

When a machine check occurs due to an error in a vector unit shared by multiple scalar units, the clock is not stopped for the entire vector unit, but is limited to the minimum necessary circuit part. , Execution of vector instructions in circuit parts unrelated to the cause of the machine check was continued as much as possible.

[Prior Art] FIG. 5 shows an example of the basic configuration of a multiprocessor system to which the present invention is directed.

In FIG. 5, 10 is a main storage unit MSU.

11 is a storage control unit MCU, 12 and 13 are scalar units SU- and SU, respectively, 14 is a vector control unit VU, 15 is a vector control unit CU, 16 is a hector execution unit VEU, 17 is a vector register VR, 1B
is the load pipeline LOAD, and 19 is the store pipeline 5TORE.

20 is an addition pipeline ADD, 21 is a multiplication 'lli < Eveline MULT+, 22 is a division pipeline DIVI
It is DE.

The scalar units SUo and SIJ+ can each execute programs independently and process scalar instructions, but if a vector instruction is detected among the instructions to be executed,
The processing is delegated to the vector unit VU.

Vector unit ■U's hector system? III Part V CU
is each scalar Unisoto SL1. ．． It selects a vector command sent by the SUI and controls the 5-vector execution unit VEU to execute it.

In such a multiprocessor system or a uniprocessor system with a single scalar unit, when a machine check occurs in the vector unit VU, the following processing is performed.

■ Stop the entire clock of the VU where the machine check occurred and stop the operation.

■ The status of the VU at that time is checked by the service processor SVP.
(not shown).

■　■UReset the entire system.

■ Return to normal operation.

In this way, in the conventional system, the clock is uniformly stopped for the entire ■U by the machine check in the VU.

[Problem to be solved by the invention]

Multiple scalar unisoto SUs are one vector control unit)V
In a conventional multiprocessor system that shares U, V
Vector instructions from multiple SUs may be processed in parallel within U at the same time.

In such a case, when a machine check occurred with a vector instruction from one SU, the entire VU was simply stopped and reset, so the processing of vector instructions from other SUs was not guaranteed. There was a problem with it disappearing.

In the present invention, when a machine check occurs in a vector unit shared by multiple scalar units,
The purpose is to prevent clock stops from affecting the processing of vector instructions that are being processed in parallel but do not pose a problem.

[Means to solve the problem]

The present invention divides the vector unit VU into a common circuit section that commonly processes vector instructions from each scalar unit, and a plurality of unique circuit sections that process vector instructions from each scalar unit for each scalar unit. For the common circuit section, a common circuit busy signal is provided to identify which scalar unit is processing vectors and instructions, and a machine check is provided for the common circuit section and each unique circuit section. A machine check occurrence signal is provided to identify the occurrence.

According to the states of these common circuit busy signals and machine check generation signals, the minimum necessary circuit portions to be stopped are separated.

Figure 1 is a diagram showing the principle configuration of the 2nd invention.
An example of a multiprocessor is shown in which two scalar units share one vector unit 71-.

In Figure 1 1213 is a scalar unit SU, SO.

14 is a vector unit U shared by SU, , SU.

16 is a vector execution unit VEU.

23 and 27 are vector instruction fetch circuits VU-FO that input vector instructions sent by SU, , SU, respectively.
,VU-Fl,SU,,SU,.

Each is a unique circuit part.

31 is a vector instruction execution unit VU-+ that selects and executes the vector instructions su, , su, which are input to VU-FO and VU-Fl, respectively, and executes each SU, , SU.
, which is a common circuit part for vector instructions.

36 is a clock stop control circuit CKSTPC provided in the VU-1.

VU-I BUSYO, VU-I BtJSYl is VU
-1 is a common circuit busy signal indicating that vector instructions SUO and SU are respectively using the signal.

MCHVU-FO, MCHVU-F L MCHVU
-1 is a machine check occurrence signal indicating that a machine check has occurred in VU-FO, VUFl, and VU-1, respectively.

5TOP VU-FO, 5TOP VU-Fl.

5TOP VU-1 is VU-FO, VtJ respectively
This is a clock stomp signal for -Fl, VU-[.

[Effect]

In the principle configuration shown in FIG. 1, when the vector instruction fetch circuits VU-FO and VU-Fl of the vector unit U are capable of receiving, the corresponding scalar unit S
The vector instruction controller VU-f takes in vector instructions from U, , SU, and selects the vector instruction of VU-FO or VtJ-F 1 when executable, and controls the execution.

VU-1 outputs a common circuit busy signal V depending on which vector instruction, VU-FO or VU-Fl, is being processed.
Turn on one of U-I BUSYO and VLI-I BUSYI.

In addition, if a machine check occurs in any of VU-FO, VU-Fl, and VU-1, the machine check generation signal MCHVUFO, MCHVU-Fl of that circuit part
, turn on MCHVU.

The clock stop control circuit CKSTPC determines the minimum circuit portion to which the clock should be stopped according to the combination of the common circuit busy signal and the machine check generation signal, and outputs a clock stop signal. The details will be explained in detail in the examples, but basically it is as follows.

The circuit part that should be stopped is the circuit part that generated the machine check, and if the circuit part that caused the clock stop is either VUFO or VU-Fl, VU-1 is also included. It will be done.

Furthermore, when VLI-FO or VU-Fl generates a machine check, VtJ-[ is
, SU, ), the vector instruction fetch circuits (VU-Fl, VU-Fl, VU-
FO) is also subject to clock stop.

Furthermore, when VU-1 generates a machine check, VU
-1 is processing vector instructions of both systems, or if it is not processing vector instructions of either system, VU-1 is
Both FO and VU-Fl are clock stopped. The latter is for safety.

Furthermore, if the VU-+ is processing vector instructions of only one system, the clock of the vector instruction fetch circuit belonging to that system is stopped.

〔Example] FIG. 2 shows the configuration of a system according to an embodiment of the present invention.

In fig.

12 is a scalar unit SU.

13 is a scalar unisoto SUI.

14 is a vector unit VU.

16 is a vector execution unit VEU.

23 is a vector instruction fetch circuit VU-FO which fetches the vector instruction of SU1.

24 is the vector fetch stage register ■FSRO
It is.

25 is a vector fetch buffer VFBO.

26 is a selector SEL that selects between the VFSRO and VFBO (7) outputs.

27 is a vector instruction fetch circuit that fetches the SU+ vector instruction.

28 is the vector fetch stage register FSRI
It is.

29 is a vector fetch buffer VFB1.

30 is a selector SEL that selects the output of VFSRI and VFB1.

31 is a vector instruction execution unit VU-1.

32 is a selector SEL for selecting the VU-FO and VtJ-Flf7) outputs.

33 is a vector instruction predecode stage PS.

34 is a vector instruction queue stage VQS.

35 is a vector instruction execution stage YES.

36 is a cross-stop control circuit CKSTPC.

VU-FO and VU-FI are SU, SUl, respectively.
Vector instructions fetched from VFSRO.

VFSRI, but those vector instructions are stored in vu
If the next vector instruction must be fetched before being transferred to -r, the preceding vector instruction must be
Retained by BO, VFBI.

The VU-FO selector 5EL26 selects VFBO if VFBO is empty, and selects VFS if VFBO is empty.
Select RO. VU-Fl selector 5EL30 is also V
Similar choices are made for FB I and VFSRI.

VU-1 is set to VUFO and V by selector 5EL32.
Select one of the outputs of U-Fl and set the transferred vector instruction in VPS. The VES predecodes the set vector instruction and holds it until it can be transferred to the VQS.

The VQS maintains a queue of sequential vector instructions until it can issue them to the VEU.

The VES is a stage for monitoring the execution of vector instructions sent to the VEU, and includes an instruction management control unit (not shown) for each instruction execution pipeline (18 to 22 in FIG. 5).

CKSTPC is VU-FO, VLI-Fl, VPS,
Machine check signal MCHV that turns ON when a machine check occurs in VQS, VES, and VELJ.
U-FO, MCHVU-Fl, and MCHVU-1 were manually operated as one signal group, and VPS, VQS, and VES were respectively StJ.

Common circuit busy signal VPS BUSYO/VPSB indicating which vector instruction, SU or SU, is being processed.
tJSY1. VQS BtJSYO/VQS BU
SYI VES BUSYO/VESBUSYI are input as the other signal group, and a certain logic is established between these signals. The logical result outputs are VU-FO, VU-
Clock stop signal 5TOP for Fl, VU-1
VU-FO, 5TOP VU-Fl, 5TOP
It becomes VU-1.

Clock stomp control circuit CKS shown in FIG.
Details of TPC will be explained with reference to FIGS. 3 and 4.

FIG. 3 shows the control logic of CKSTPC, and FIG. 4 shows the configuration of its concrete embodiment.

In FIG. 3, the machine check generation signal and the common circuit busy signal are the input logic signals, and the clock stop signal is the resulting output logic signal. ■ or ■ indicates a different control case, O mark is ON ("BI") × mark is 0FF ("
O') represents the logical value. Also, a blank space indicates that it has no relation to logic (Don't Care). Each case will be explained in turn below.

Case (2) A machine check occurred on the VU-FO while Sul was using the VU-1. At this time, it is necessary to stop the instructions of SU in VU-1 in addition to VLI-FO, and as a result, V
It became necessary to stop the command of U-Fl as well, and VU-1
, VU-FO, and VUFl are clock-stopped.

Case (2) When SU was not using VU-1, a machine check occurred on VU-Fo. At this time, VU-FO and VU-1 instructions are stopped, but even if VU-1 instructions are stopped, VU-FO and VU-1 instructions are stopped.
Since it does not affect U-Fl, the VU-Fl instruction does not stop. Therefore, the clocks of VU-1 and VU-FO are stopped.

Case (2) This is a case (2) in which S U + and SUo are exchanged.

Case (2) In case (2), SU and SUo are exchanged.

In case ①, VUI generated a machine check while both SU and SU were using VU-1, so in addition to VU, VU-FO and VtJ-Fl instructions also needed to be stopped.
1. Stop all clocks of VU-FO and VUFl.

Standard case SU, while VU-1 is being used, VU-1 is machine tier '7
Due to the error, VU-FO is sent along with the VU-1 command.
It is necessary to stop the instruction of VU-1 and VU-
Stop the FO clock.

Case ① While SU was using VU-1, V[J-1 generated a machine check, so VU-Fl was sent along with the vu-r instruction.
commands must also be stopped.

Clock stop VU-1 and VU-Fl.

■ Case SUo and SU do not use VU-1, but VU-
SU due to a machine check occurring in 1.

It is not possible to separate SU and SU. For this reason, the clocks of all circuits are stopped for safety reasons.

Figure 4 shows the control logic in Figure 3 as an OR gate OR/NOR.
FIG. 2 is a logic circuit diagram configured using gates and AND gates.

In Fig. 4, MCHVU-FO (1), (2)...
・, (I) is a machine check generation signal output from one machine check detection section (not shown) in the VLI-FO, and the OR gate 37 performs an OR operation to generate one machine check generation signal M. It becomes CHVU-FO.

MCHVU-Fl(+), (2).

..., (1) and MCHVU-1 (IL (2),
...(J) can be summarized in the same way in OR game 1-38.39.

VPS BUSYO, VQS BUSYO, VES
BUSYO is the vps in Figure 2, respectively.

This is a common circuit busy signal output from VQS and VES, and indicates that a vector instruction from SU exists in each stage. These signals are ORed and NORed by an OR/NOR gate 40, and the OR output is VU-
Become I BLJSYO.

VPS BUSYI, VQS BUSYI, VES
Similarly for BUSYI, OR/NOR gate 4
1 is ORed and NORed, and the OR output is VU-I
It becomes BUSYI.

AND gates 42 to 49 respectively implement the conditions of cases 1 to 2 of the control logic in FIG.

The OR gate 50 has A, ND gates 42.43, 44°46.47, corresponding to cases ■, ■, ■, ■, ■■.
．． The outputs of 49 are ORed to produce a clock stop signal 5TOP VUFO for VU-FO.

The OR gate 51 has cases ■, ■1■, ■, ■.

Corresponding to ■, AND gate 42, 44.45°46.4
The outputs of 8.49 are ORed to produce the clock stop signal 5TOP VUFl for VU-Fl.

The OR gate 52 takes 0R of the outputs of the AND gates 42 to 49 corresponding to all of the cases ■ to ■, and outputs VU.
Clock stop signal 5TOP VU- for -1
yields 1.

〔Effect of the invention〕

According to the present invention, ? Even if a machine check occurs in a vector unit shared by Jl number of scalar units, the clock will not be stopped to the extra circuit parts, thereby improving the processing efficiency of vector instructions of each scalar unit that is processed in parallel. Can be done.

[Brief explanation of the drawing]

FIG. 1 is a diagram of the principle of the present invention; FIG. 2 is a diagram of a system according to an embodiment of the present invention; and FIG. 3 is an explanatory diagram of an example of the control logic of the clock stop control circuit in the system of the embodiment shown in FIG. , FIG. 4 is a circuit diagram of an embodiment of a CLOCK71 control circuit that implements the control logic shown in FIG. 3, and FIG. 5 is a block diagram of a conventional multiprocessor system to which the present invention is applied. In Figure 1. SUo, SU, Niscara unit ■U: Vector unit VEU: Vector execution unit vur”o VU-Fl: Vector instruction fetch circuit vu-yz vector instruction execution unit CKSTPC: Cronks [・Tub control circuit VU-I
BUSYO, VU-I BUSYI: Common circuit and G signal

Claims (1)

[Claims] The vector unit (VU) is composed of a plurality of scalar units (SU) that process scalar instructions, and a vector unit (VU) that processes vector instructions sent from these scalar units (SU). ) is a multiprocessor system that selects and executes vector instructions sent from multiple scalar units (SUs). It is divided into a common circuit part (VU-I) used for the scalar unit (SU) and a unique circuit part specific to the vector instruction of each scalar unit (SU), and shows that the common circuit part (VU-I) is actually used. A common circuit busy signal (VU-IBUSY) is provided for each scalar unit (SU), and a machine check generation signal indicating that a machine check has occurred is provided for each common circuit section (VU-I) and specific circuit section. A clock stop control method using a machine check, characterized in that a circuit portion to be stopped is determined by a combination of the common circuit busy signal and the machine check generation signal.