JPH02136000U - - Google Patents

Description

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a read-only memory according to the present invention, FIG. 2 is a timing chart showing waveforms of various parts of FIG. 1, and FIG. 3 is a circuit diagram showing a conventional example. 6...Monitor circuit, 7...Latch circuit, 8...
...Latch clock generation circuit, 16...Latch clock switching circuit.

Claims (1)

[Claims for Utility Model Registration] (1) A plurality of data storage devices connected in parallel or series between a first potential and a data readout node and controlled by applying an address signal to the gate. a MOS transistor, and a precharge MOS transistor connected between a second potential and the data read node and controlled by a precharge signal for precharging the data read node to the second potential. A read-only memory comprising: a latch circuit that latches data obtained from the data read node; and a monitor configured identically to the data storage MOS transistor and the precharge MOS transistor and operated by the precharge signal. A read-only memory comprising: a latch clock generating circuit that delays a monitor output obtained from the monitor circuit and generates a latch clock for operating the latch circuit. (2) a first latch clock obtained from the latch clock generation circuit and a second latch clock obtained from the clock generator are applied;
Based on a frequency switching signal that switches the frequency of the oscillation signal applied to the clock generator,
The read-only memory according to claim 1, further comprising a latch clock switching circuit that outputs either the first or second latch clock to the latch circuit.