JPH02131022A - Encoder/decoder - Google Patents

Abstract

PURPOSE:To decrease a processing circuit in speed and to reduce a cost by providing an encoder converting a code into a 11-bit code word and giving a function reading the code word generated by the encoder and outputting the result sequentially as the 11-bit code word to a timing circuit in addition. CONSTITUTION:The sequence of data words 1 expressed as series '0' and '1' applied to a coding circuit 3 is divided into data words in 8-bit each by a timing circuit 5 and fed to a coder 4 sequentially. The 8-bit data word fed to the coder 4 is converted into a 11-bit code word 2 according to the reference list between codes exclusive for coding stored in a ROM in the coder 4. It is stored in advance in the ROM as the reference list between codes and the list converts and outputs the pattern of the data word inputted to the coder. Thus, the recording with a lower clock rate and longer recording bit length is applied in comparison with 2, 7 codes, a 4/15 code to attain the optical recording with high quality.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applied in the field of optical recording and reproducing, where conversion to data is generally performed by a forward conversion method using a sequence using a logic circuit or by converting data words into specific words. A method has been adopted in which the signal is applied to an encoder containing a ROM storing an inter-code correspondence table, and the encoder converts the signal into a code word pattern according to the inter-code correspondence table. In this way, the intensity of the laser beam is modulated according to the code word pattern generated by the encoder and recorded on the recording medium. In addition, conversion from a compound word to a code word during playback can be performed using an inverse conversion method using a sequence using a logic circuit, or by converting a code word pattern read from a recording medium into a ROM that stores a specific code-to-code correspondence table. A method in which the decoder generates a data word pattern converted according to an inter-code correspondence table, converts it into an original signal, and extracts it.
etc. are taken. However, as mentioned above, the conversion method from data words to code words affects the bit rate and recording density, and when this conversion is performed using a specific code correspondence table stored in ROM, the conversion method The present invention relates to a novel device for encoding and decoding codewords with a ROM size.

[Prior Art] In the field of digital optical recording such as optical discs,
First, the original signal to be recorded is divided into 0 and '1' based on the binary system.
It is converted into a data word pattern consisting of 8 bits expressed as a sequence of numbers. In this case, if the data word pattern is recorded as is on the optical disk, the following problems generally occur. In other words, if there are consecutive '0's or 1's in a data word, the DC component of the reproduced signal will fluctuate and the focus servo or tracking servo will be disturbed, so a certain upper limit is set for the length of consecutive '0's or 1's. Control as follows. In this way, the data word pattern is converted into an appropriate code word pattern and recorded. Therefore, the key to improving the bit rate, recording density, and reproduction accuracy is how to convert data words into code words or convert compound words into data words.

Among these, the code word is determined from the data word to be recorded.

The conversion method from data words to code words is as follows:
Several methods have been proposed in the past, and the (2,7) code (Japanese Patent Application Laid-open No. 5O-142131) and the 4/15 code (Japanese Patent Application Laid-open No. 6O-182061) are known as representative ones for optical recording. It is being Of these, (2,7)
The code is a method of converting a sequence of original data words into a sequence of code words that are twice as long as the bits, and as a result, an 8-bit long data word is converted into a 16-bit long code word. considered to be a thing. As is well known, the (2,7) code has the advantage that the ROM in the encoder can be made smaller because the code correspondence table requires only seven bit patterns.

On the other hand, the 4/15 code is an encoding method that directly converts a sequence of 8-bit original data words into a 15-bit code word. In this case, there are 215 = 32,768 possible combinations of bit patterns represented by a sequence of '0' and '1' as the converted code word, but in the 4/15 code, this combination of bit patterns We extract the even-numbered groups and the odd-numbered groups as bit groups, and select those in which there are two '1's in the bit groups of each group, and make them correspond to the data word pattern. A feature is that the number of 1's included in a code word of a 1-bit pattern is limited to four.

[Problem to be solved by the invention] As mentioned above, in conventional encoding methods such as (2,7) code and 4/15 code, the correspondence table between codes can be small, so the ROM can be made relatively small. There are advantages that can be achieved. However, when comparing the bit rates, when converted to code words and recorded, the (2,7) code is twice as much as the data words are recorded as they are, and the 4/15 code is 1 times the bit rate.
5/8 times, and there was a problem in that the speed of the processing circuit had to be increased accordingly. Furthermore, if there is an upper limit to the speed of the processing circuit, there is also the problem that the required data word transfer speed cannot be obtained.

The present invention solves the above problems and includes a bit extraction circuit for determining the pin rate of 7 bits, a function for reading a first group of data words consisting of 7 bits output from the bit extraction circuit, and a code-to-code correspondence function. 7 '0' by ROM
and converted into an 11-bit code word consisting of four '1's.
, and an encoder for storing the converted codeword consisting of 11 bits as a first group of codewords, and an MSB and LSB of each of the first group of codewords stored in the encoder. and a code permutation inversion circuit for inverting, and when encoding data words No. 1 to No. 128, the code words of the first group stored in the encoder are provided in the encoding circuit. The output of is the conversion result, and when encoding the 129th data word to the 256th data word, the MSB and LS of the first group of code words stored in the encoder are
In addition to providing a function to output the code word obtained by inverting B as a conversion result, when decoding the reproduced code word, seven '0's and 4 ' It is an object of the present invention to provide an encoding/decoding device equipped with an encoder and a decoder that can increase the number of 1'' bits or decrease the clock frequency by 11 bits.

[Means for Solving the Problems] In order to achieve the above object, the encoding/decoding device of the present invention converts a sequence of data words into symbols of 8 bits each in an encoding circuit for encoding. A timing circuit for dividing the code and an 8-bit data word from the timing circuit are read and converted into an 11-bit code word consisting of 7 0's and 4 1's by a ROM equipped with an inter-code correspondence function. The present invention is characterized in that the timing circuit has a function of reading the code word generated by the encoder and sequentially outputting it as a code word of 11 bits each.

In addition, in the encoding circuit, a first
a switch circuit for reading a sequence of 8-bit data words representing data words numbered to number 256, and reading and outputting code words of data words numbered 1 to 128; 1 output from the switch circuit
a decoder for reading a code word consisting of 1 bit and converting it into a data word consisting of 8 pins 1- by a ROM having an inter-code correspondence function as an address; a 2-bit decoder serving as a bit pattern determination circuit; a code permutation inversion circuit for inverting the permutation of code words when the 2-bit decoder outputs false; and a selection circuit for causing the output from the decoder to be output from the decoding circuit as a composite data word. Another feature is that it has the following.

[Operation] According to such an encoding/decoding device, when encoding a data word, a 1-byte data word consisting of 8 bits is only converted into a code word of 11 bits at most. , (2.7) code or 4/15 code, the number of bits after conversion is smaller, so it can be expected that the speed of the processing circuit will be reduced, that is, the cost will be reduced. The proportion of '1' in it is 1
Since it is constant at 4/1, a kind of DC-free code is obtained. Further, since encoding is performed by a two-step operation, an inter-code correspondence table can be constructed using a small ROM during encoding.

On the other hand, when decoding a code word, by using the rule that there are four °1's in a code word,
Error words can be found and data words can be accurately decoded from ambiguous code words.

Furthermore, since decoding is performed by a two-step operation, an inter-code correspondence table can be constructed using a small ROM during decoding.

[Example] Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows an encoding circuit for encoding in a first embodiment of the encoding/decoding apparatus of the present invention.
1 is data word, 2 is code word, 3 is encoding circuit, 4 is RO
5 is a timing circuit.

The sequence of data word 1, which is expressed as a sequence of 0's and 1's, is applied to the encoding circuit 3 by selecting a bit pattern that does not include four consecutive 1's from among the timing patterns. , furthermore, there are 4 consecutive codes at the connection between code words
It is created by arranging three consecutive bit patterns that do not include 1' at the end of a word in ascending order so that there is no 1°.

(Left below) is divided into data words of 8 bits each by the processing circuit 5,
The data are sequentially sent to the encoder 4. The 8-bit data word sent to the encoder 4 is divided into 11 and 11 bits according to an inter-code correspondence table dedicated to encoding stored in the ROM in the encoder 4.
It is converted into a code word 2 consisting of bits. Although such a conversion method is well known, the present invention is characterized in that a special modification has been made to the code correspondence table as described below.

In other words, as a code word in this case, there are 211 = 2048 possible combinations of bit patterns, but from among these, we first select 330 bit patterns consisting of combinations of '0' and four '1's. Furthermore, 255 patterns suitable for optical recording are selected.These are stored in the ROM in advance as an inter-code correspondence table, and are converted and output into code words in correspondence with the data word patterns input to the encoder.

An example of an inter-code correspondence table for the 4/11 code determined in this way is shown in Table 1. There are 33 wooden tables available.
The bit pattern converted into an 11-bit Table 1 code word containing four zero '1's is sequentially outputted from the encoding circuit 3 via the timing circuit 5 again. This data word/code word conversion process continues until there are no more data words. Therefore, by using the encoding circuit configured in this way, the bit rate is 11/16 times that of the 2/7 code, which is the conventional conversion method, and 4/15
The code is 11/15 times smaller (as a result, a larger reproduced signal amplitude can be extracted and the reliability of the entire device can be improved. Also, the recording/reproducing clock frequency is 2/15 times smaller than that of the conventional code). 11/16 times the 7 chord, 4/
Since it is 11/15 times lower than that of 15 codes, it is advantageous when implementing an encoding/decoding device into an LSI. Note that the decoding circuit according to the first embodiment has a function that is an inversion of the function of the above-mentioned encoding circuit, so a description thereof will be omitted here.

FIG. 2 shows an encoding circuit for encoding in a second embodiment of the encoding/decoding device of the present invention.
6 is a bit extraction circuit, and 7 is a code permutation inversion circuit.

In this case, prior to generating a code word, a bit sampling circuit first extracts data from a sequence of 8-bit data words representing data words from the first data word to the 256th data word applied to the encoding circuit 3. 6, the data words from the 1st to the 128th data word consisting of 7 bits are taken out as the first group of data words, and the data of the first group are shown in Table 2-2 (
In this way, when encoding the data words No. 1 to No. 128, the output of the first group of code words stored in the encoder 4 is used as the conversion result, and the data word No. 129 is used as the conversion result. When encoding the 256th data word from the word, the code permutation inversion circuit 7 converts the word into seven degrees according to the code correspondence table shown in Table 2 stored in the ROM in the encoder 4. It is converted into an 11-bit code word consisting of O' and four '1 degrees, and the converted code word consisting of II bits is stored in the encoder 4 as a first group of code words.

From Table 2-1 (in order), the MSB (Most
Significant Bits) and LSB (Le
The code word obtained by inverting the code word (ast 51gn1ficant BitS) is used as a conversion result, and is output from the encoding circuit 3 as a second group of code words. The effects obtained by this conversion method are similar to those of the first embodiment, but there is a new advantage that the ROM for storing the code correspondence table can be halved. Regarding Table 2, which shows the code-to-code correspondence table used here, in addition to the rules for configuring the bit patterns of code words in Table 1, we first remove left-right symmetrical ones from among the 330, and then perform permutation. When horizontally reversed, the first
148 items were selected that satisfied the conditions in the table, and 128 items with the lowest values were retained. Therefore, not only do these codewords have four 1's, but when their permutations are reversed, they become completely different codes, creating a total of 256 bit patterns.These are 8 bits x 128 Since the word ROM is stored, the size of the ROM is only half that of the first embodiment.In this embodiment, the code words of the second group are obtained by reversing the permutation of the code words of the first group. In addition, there are also the following methods: obtaining the second group of codewords by subjecting the first group of codewords to constant bit rotation, or There are methods to perform random sorting.

FIG. 3 shows a decoding circuit for decoding in the second embodiment, where 8 is a decoding circuit, 9 is a switch circuit, 10 is a switch, 11 is a decoder, and 12 is an R
OM input lotus, 13 is ROM output lotus, 14 is pin l-
8 lines, 15 is a code word input line, 16 is a clock line, 17 is a 2-bit decoder, 18 is a selection circuit, and 19 is a decoded data word output line. In this case, since the input code word attempts to refer to each /sROM in forward and reverse order, the R
Can be combined with OM. The clock line 16 has
A clock signal indicating one cycle is generated for each hide of the input code word. The input code word is displayed on the code word input line 15 one by one.

Next, in decoding the second reverse order code (the second group of code words inverted and encoded during encoding), when the clock signal is true,
The switch 1° in the switch circuit 9 sends the reproduced code words in forward order to the ROM in the decoder 11. The decoder 11 is
The content data at the address is output to the ROM output bus 13, but at this time, the bit 8 line 1 of the ROM output bus 13
4 is stored in the ROM in advance so as to output '0' to indicate that the ROM contents are invalid.

Therefore, since the clock signal is true but the bit 8 line 14 is false, the 2-bit decoder 17 does not output the data word on the ROM output lot 13 to the decoded data word output line 19. After this, when the clock signal becomes false, the switch 10 sends the permuted data of the reproduced code word to the ROM.
The decoded data word is output to the output bus 13, and the bit 8 line 14 outputs true to indicate a valid decoded data word. Therefore, if the clock signal is false, bit 8 line 1
When 4 is also false, the 2-bit decoder 17 is assumed to be in code order. The decoding operation will be explained below in two cases.

First, the first forward code (the first code that did not need to be inverted during encoding)
When the clock signal is true, the switch 10 in the switch circuit 9 converts the reproduced codeword in the forward order into R.
via the OM input bus 12 to the ROM in the decoder II. The decoder 11 outputs the content data of the address to the ROM output bus 13, and at this time, when the bit 8 line 14 of the ROM output bus 13 outputs true as a valid decoded word, "I" is displayed. It is stored in the ROM in advance. Therefore, when the clock signal is true and the bit 8 line 14 is also true, the 2-bit data decoder 17 outputs the decoded data word on the ROM output bus 13 to the decoded data word output line 19. On the other hand, when the clock signal is false, switch 1
0 is inverted through the code permutation circuit 7 and sends the permuted code word of the reproduced code word to the ROM in the decoder 11 through the ROM input path 12 so that the ROM output bus 13
All "0"s are outputted to the decoded data word output line 19, and the output via the column inversion circuit 7', which is not a reverse order code, is outputted to the decoded data word output line 19. Note that in the case of the second group generation method as described in the above encoding section, the following operations are performed instead of the permuted data correspondingly. That is, in the case of generation by constant bit rotation, in the case of using a data pattern by reverse rotation or pseudo-random rearrangement, rearrangement by inverse transformation is used.

[Effect] As explained above, according to the encoding/decoding device of the present invention, an 8-bit data word can be easily converted into an 11-bit compound word, so that the conventional (2,7) code can be easily converted into an 11-bit compound word. ,4/
Compared to the 15 code, the clock rate is lower, recording with a longer recording bit length can be realized, and high-quality optical recording can be realized.

Additionally, since the codeword clock speed increases less than the data clock speed, it contributes to lower costs for processing circuits.
Under conditions of constant processing speed, the data clock speed can be increased.

Furthermore, although removable codes generally require a large ROM for encoding and decoding, they have the advantage of being able to reduce the size of the ROM by more than half through a two-step operation when decoding codewords. .

[Brief explanation of drawings]

FIG. 1 shows a first embodiment of the encoding circuit used in the encoding/decoding device of the present invention for encoding, and FIG. 2 shows the encoding circuit in the encoding/decoding device of the present invention. This is a second embodiment showing an encoding circuit for performing encoding;
The figure shows a decoding circuit for performing decoding in the second embodiment. 1... Code word 2... Compound word 3
... Encoding circuit 4 ... Encoder death ... Timing circuit 6 ... Bit sampling circuit 7.7゛ ... Code permutation inversion Circuit 8...
Decoding circuit 9...Switch circuit 10...
...Switch 11...Decoder 12.
...ROM input lotus 13...ROM output lotus 14...Bit 8 line 16...Clock line 18...Selection circuit 15... ... Code word input line 17 ... 2-bit decoder 19 ... Compound data word output line

Claims (2)

[Claims] (1) Encoding and decoding functions that combine encoding and decoding functions
In the decoding device, a timing circuit for reading and outputting a sequence of data words as a symbol of 8 bits each is included in an encoding circuit for encoding, and a symbol of 8 bits each output from the timing circuit. and an encoder for reading the code and converting it into an 11-bit code word consisting of 7 '0's and 4 '1's using a ROM having an inter-code correspondence function, and the timing circuit. , reads the code word generated by the encoder,
An encoding/decoding device characterized in that it also has a function of sequentially outputting code words of 11 bits from the encoding circuit. (2) Encoding and decoding functions that combine encoding and decoding functions
In the decoding device, in the encoding circuit for encoding, data words from the first to the second data word are stored in the encoding circuit for encoding.
a bit sampling circuit for reading a sequence of 8-bit data words representing data words up to 56 and outputting data words 1 through 128 as a first group of 7-bit data words; reading a first group of data words consisting of 7 bits output from the bit extraction circuit;
A ROM with an inter-code correspondence function converts it into an 11-bit code word consisting of 7 '0's and 4 '1's, and converts the converted 11-bit code word into the first group code word. a code permutation inversion circuit for inverting the MSB and LSB of each of the first group of code words stored in the encoder; , when encoding data words No. 1 to No. 128, the output of the first group of code words stored in the encoder is used as the conversion result, and data words No. 129 to No. 256 are encoded. When encoding a data word, the code word obtained by inverting the MSB and LSB of the first group of code words stored in the encoder is provided as a conversion result, and a function is provided to output the code word as a conversion result. When decoding a word, seven '0's are stored in the decoding circuit for decoding.
A switch circuit for reading and outputting an 11-bit code word consisting of ' and four '1's, and a ROM equipped with a function to read the 11-bit code word output from the switch circuit and use it as an address to correspond between codes. a decoder for converting into a data word consisting of 8 bits, a 2-bit decoder as a bit pattern determination circuit, a code permutation inversion circuit for reversing the permutation of an input code word or a decoded data word; An encoding/decoding device comprising: a selection circuit for outputting a data word output from a decoder from the decoding circuit.