JPH02130828A - How to form fine wiring - Google Patents
How to form fine wiringInfo
- Publication number
- JPH02130828A JPH02130828A JP28358988A JP28358988A JPH02130828A JP H02130828 A JPH02130828 A JP H02130828A JP 28358988 A JP28358988 A JP 28358988A JP 28358988 A JP28358988 A JP 28358988A JP H02130828 A JPH02130828 A JP H02130828A
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- Prior art keywords
- forming
- base
- fine wiring
- thin film
- forming fine
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は微細配線の形成方法に係り、特に積層構造を有
する密着性の良好な薄膜の形成法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming fine wiring, and particularly to a method for forming a thin film having a laminated structure and having good adhesion.
従来の微細配線の形成方法には、薄膜の密着性を改善す
る方法として、薄膜形成直後に熱処理を施したり、別の
薄膜を挿入するなどが行なわれてきた。In conventional methods for forming fine wiring, methods for improving the adhesion of the thin film include applying heat treatment immediately after forming the thin film or inserting another thin film.
上記従来技術は、いずれも平坦な面と、面の接触構造を
対象としたものであり、機械的な構造や形状については
配慮されておらず、LSIの製造工程において、形成し
た薄膜が剥離するという問題があった。The above-mentioned conventional technologies are all aimed at flat surfaces and contact structures between the surfaces, and do not take into consideration the mechanical structure or shape, resulting in the thin film formed peeling off during the LSI manufacturing process. There was a problem.
本発明の目的は、上記薄膜の密着性を向上することにあ
る。An object of the present invention is to improve the adhesion of the above-mentioned thin film.
上記目的は、薄膜を形成しようとする下地の表面に窄み
または突起を形成し、機械的に上記薄膜を保持する構造
とすることにより達成される。The above object is achieved by forming depressions or protrusions on the surface of the base on which the thin film is to be formed, and creating a structure for mechanically holding the thin film.
下地表面に窪みを形成し、この上に薄膜を形成した場合
においては、薄膜の一部が下地の窪みの中に埋まった構
造となる。窪みの側壁の形状が半導体基板の主平面と垂
直の場合には、この側壁面での下地材と薄膜材の間との
摩擦力によって薄膜は下地表面から剥離しにくくなり、
密着性が向上する。また窪みの側壁が逆テーパ形状であ
る場合には、下地または形成した薄膜の窪み近傍に破壊
または大きな変形が生じない限り剥離しないので特性を
大幅に改善することができる。また、下地表面に突起を
形成した場合についても、突起の側壁形状により、それ
に応じた密着性の改善が可能である。When a depression is formed on the surface of the base and a thin film is formed thereon, a part of the thin film is buried in the depression of the base. When the shape of the sidewall of the recess is perpendicular to the main plane of the semiconductor substrate, the thin film becomes difficult to peel off from the underlying surface due to the frictional force between the base material and the thin film material on this sidewall surface.
Adhesion is improved. Furthermore, when the sidewalls of the recesses have an inversely tapered shape, the properties can be significantly improved because peeling will not occur unless the underlying layer or the formed thin film is destroyed or greatly deformed in the vicinity of the recesses. Furthermore, even when protrusions are formed on the base surface, adhesion can be improved accordingly depending on the shape of the side walls of the protrusions.
以下9本発明の一実施例を第1図により説明する。第1
図は、タングステンをLSIの配線に適用した断面図を
示す。An embodiment of the present invention will be described below with reference to FIG. 1st
The figure shows a cross-sectional view of tungsten applied to LSI wiring.
第1図に至る工程を説明する。まずP型Si基板1を準
備し、主表面の所望の領域を選択的に熱酸化して5iO
z膜2を形成し2次にリンイオン注入と熱処理によりリ
ン拡散層3を形成した。次に、平坦部での膜厚が0.8
μmの5iOz4をCVD法により形成し、バターニン
グしたホトレジストをマスクとしてドライエツチング法
で該S i Oz4 に開口部を設けた。The steps leading to FIG. 1 will be explained. First, a P-type Si substrate 1 is prepared, and a desired region of the main surface is selectively thermally oxidized to produce 5iO
A Z film 2 was formed, and then a phosphorus diffusion layer 3 was formed by phosphorus ion implantation and heat treatment. Next, the film thickness at the flat part is 0.8
A 5iOz4 film having a thickness of 5 μm was formed by a CVD method, and an opening was formed in the SiOz4 film by a dry etching method using a patterned photoresist as a mask.
次に、本発明の一例である薄膜表面に密着性を強化する
ための窪み5を形成した。この窪みは、直径0.5μm
の円形パターンを有するホトレジストをマスクとして、
CHF aガスを用いたドライエツチング法で0.2μ
mの深さとした。マスクとしたホトレジストを除去した
後、DCマグネトロン・スパッタ法によりWを0.4μ
m形成した。Next, depressions 5 were formed on the surface of the thin film, which is an example of the present invention, to strengthen adhesion. This depression has a diameter of 0.5 μm
As a mask, a photoresist with a circular pattern of
0.2μ by dry etching method using CHFa gas
The depth was set to m. After removing the photoresist mask, 0.4μ of W was applied using DC magnetron sputtering.
m was formed.
次に、ホトレジストの配線パターンをマスクとして、ド
ライエツチング法でWを加工してWの配線パターンを形
成した。Next, using the photoresist wiring pattern as a mask, W was processed by dry etching to form a W wiring pattern.
次に、本発明の一例である窪み7をW表面に形成した。Next, a depression 7, which is an example of the present invention, was formed on the W surface.
該窪み7は、窪み5を形成した工程と同種のホトリソグ
ラフィ工程でホトレジストパターンを形成し、SFeガ
スを用いたドライエツチング法で深さ0.1μmとした
1次に、マスクとしたホトレジストを除去した後、絶縁
膜8を形成した。The depressions 7 are formed by forming a photoresist pattern using the same photolithography process as that used to form the depressions 5, and by dry etching using SFe gas to a depth of 0.1 μm.Then, the photoresist used as a mask is removed. After that, an insulating film 8 was formed.
この状態の断面図が第1図である。ここに示した窪み7
の形成にあたっては、上記説明のようにW配線を加工後
窪み7を形成しても、また加工順序を変えて窪み7を形
成した後W層6を配線パターンに加工しても良く、窪み
7を形成することにより同様の効果が得られた。A cross-sectional view of this state is shown in FIG. Hollow 7 shown here
In forming the recesses 7, the recesses 7 may be formed after processing the W wiring as described above, or the recesses 7 may be formed by changing the processing order and the W layer 6 may be processed into the wiring pattern. A similar effect was obtained by forming .
次に、第2図を用いて窪みの密度と密着性評価試験にお
ける臨界荷重との関係を示す、試料には4インチSi基
板上にCVD法で0.45μmの5insを形成し、直
径0.5pm、深さ0.15μmの窪みを密度を変えて
形成し、その上に膜厚0.4μmのWをスパッタ法で形
成したものを用いた。窪みの密度がIC)m″″2の場
合には臨界荷重は0.50kgwであったが、窪み密度
が50m重′″2100+nm−”ではそれぞれ0 、
57kgv、 0 、72kgvであった。!み密度が
500mm−2以上の場合には測定限界(1,kgw)
以上であった。鐸みの密度が増大するほど、すなわち窪
みの個数が多いほど密着性が向上することがわかる。Next, the relationship between the density of the depression and the critical load in the adhesion evaluation test is shown using FIG. Recesses each having a thickness of 5 pm and a depth of 0.15 μm were formed at different densities, and a W film having a thickness of 0.4 μm was formed thereon by sputtering. The critical load was 0.50 kgw when the density of the hollow was IC) m″″2, but when the density of the hollow was 50 m″2100+nm−”, the critical load was 0, respectively.
They were 57 kgv, 0, and 72 kgv. ! If the density is 500 mm-2 or more, the measurement limit (1, kgw)
That was it. It can be seen that as the density of the bells increases, that is, as the number of depressions increases, the adhesion improves.
次に第3図を用いてCVD−WSiX膜の組成比Xを変
えた場合の臨界荷重について説明する。Next, the critical load when the composition ratio X of the CVD-WSiX film is changed will be explained using FIG.
窪みの形状は2種類とし、垂直から約10@逆テーパの
窪みと垂直の窪みを有する試料を用意し。Two types of depressions were prepared, and samples were prepared that had a vertical to approximately 10@reverse taper and a vertical depression.
窪みの無いものと比較した。試料には窪み密度が108
am−”とした窪みを有するC V D S i O
z上に0.4μmのCVD−WSixを堆積したものを
使用した。CVD−WSixの組成比Xは大きい程、す
なわちSiリッチな膜程臨界荷重は大きく密着性は良い
。組成比Xが2.2の場合、窪み形状の違いに注目して
臨界荷重の値を見ると、窪みが無い平坦なCV D −
S i Oz上では臨界荷重は100gwであった(曲
線C)のに対し、垂直形状の窪みを形成した試料(曲線
b)では680gwまで上昇した。垂直から約10°逆
テーパの試料(曲線a)では、更に大きな値となり81
0gwが測定された。CvD−WSiXのXの値)zか
んにかかわらず、窪みの無い試料よりも垂直形状の窪み
の方が、更に逆テーパの窪みの方が臨界荷重が大きく、
密着性が良いことがわかる。Comparison was made with one without dents. The sample has a depression density of 108
C V D Si O with a recess shaped like “am-”
0.4 μm of CVD-WSix was deposited on Z. The larger the composition ratio X of CVD-WSix, that is, the more Si-rich the film, the larger the critical load and the better the adhesion. When the composition ratio
On S i Oz, the critical load was 100 gw (curve C), whereas it rose to 680 gw for the sample with vertically shaped depressions (curve b). For the sample with a reverse taper of approximately 10° from the vertical (curve a), the value is even larger, 81
0 gw was measured. Regardless of the value of
It can be seen that the adhesion is good.
次に、第4図を用いて絶縁膜上に突起を形成した場合の
Wの密着性の測定結果を説明する。試料には、4インチ
Si基板上に0.6μmのCVD−8iOzを形成し、
ホトレジストをマスクとしてCVD 5iOzを0.
15μmzツチングし、高さ0.15μmの円柱状の突
起を形成した。Next, the measurement results of the adhesion of W when protrusions are formed on the insulating film will be explained using FIG. For the sample, 0.6 μm CVD-8iOz was formed on a 4-inch Si substrate,
CVD 5iOz using photoresist as a mask.
A cylindrical protrusion with a height of 0.15 μm was formed by 15 μmz cutting.
CV D S i Ozのドライエツチング条件を変
えて垂直と逆テーバの突起を形成した。突起の直径は0
.5μmとした。Vertical and reverse tapered protrusions were formed by changing the dry etching conditions of CVD SiOz. The diameter of the protrusion is 0
.. It was set to 5 μm.
第4図の横軸のAは、0.4μmのWを形成後CV D
−S i Ozを0.6μm堆積した状態を示す。A on the horizontal axis in Fig. 4 indicates CV D after forming 0.4 μm W.
-S i Oz is deposited to a thickness of 0.6 μm.
突起を形成したC V D −S i Oz膜とW膜の
間の密着性はひつかき試験の臨界荷重の値で評価した。The adhesion between the C V D -S i Oz film on which protrusions were formed and the W film was evaluated based on the critical load value of the squeeze test.
Bは、Aの状態から更に600℃30分のN2アニール
を行った後の状態、CはBの状態から0.15μm厚の
TiNを形成した後の状態、DはCの状態から0.9μ
mのAQを形成した後の状態、EはDの状態からHt中
で450℃、30分アニールを施した状態を示す。各工
程を経過する毎に、若干の臨界荷重の低下が認められ、
密着性が低下していることがわかる。B is the state after further N2 annealing at 600°C for 30 minutes from state A, C is the state after forming 0.15 μm thick TiN from state B, and D is 0.9 μm from state C.
E shows the state after forming AQ of m, and E shows the state after annealing in Ht at 450° C. for 30 minutes from state D. As each process progresses, a slight decrease in critical load is observed.
It can be seen that the adhesion has decreased.
第4図は、突起を形成しない場合(曲線C)、垂直な突
起を形成した場合(曲線b)、逆テーパの突起を形成し
た場合(曲線a)についてのプロットである。突起を形
成すると密着性が改善され、突起の形状を逆テーパにす
ると、更に密着性が改善されることがわかった。FIG. 4 is a plot for the case where no protrusion is formed (curve C), the case where a vertical protrusion is formed (curve b), and the case where a reversely tapered protrusion is formed (curve a). It was found that adhesion was improved by forming protrusions, and that adhesion was further improved by making the protrusions tapered.
次に、別の実施例を説明する。第5図は、5iOz上に
凹凸を形成し、この5iOz上に密着させてタングステ
ン配線を形成する工程の断面図である。Next, another example will be described. FIG. 5 is a cross-sectional view of the process of forming unevenness on 5iOz and forming tungsten wiring in close contact with this 5iOz.
Si基板1上に絶縁膜5iOz2を形成した表面上に、
レジストと塗布系硅素化合物(SOa)を約1=1の体
積の割合で混合した液を約0.5μmの膜厚で5iOz
Z上に塗布し、希釈フッ酸液でSOGをエツチングし、
乾燥させた状態の断面を第5図aに示した。この状態の
表面のSEM写真を第6図に示した。On the surface of the insulating film 5iOz2 formed on the Si substrate 1,
A solution containing a mixture of resist and coating silicon compound (SOa) in a volume ratio of approximately 1=1 was applied to a film thickness of approximately 0.5 μm at 5 iOz.
Apply it on Z, etch the SOG with diluted hydrofluoric acid solution,
A cross section of the dried product is shown in FIG. 5a. A SEM photograph of the surface in this state is shown in FIG.
第5図aの試料を酸素プラズマ中で2分間処理し、レジ
ストの一部をエツチングし、5iOz2上に島状のレジ
ストを形成した状態を第5図すに示す、この状態の試料
をCHFδガスを用いたプラズマエツチングで0.1μ
m5iozをエツチングし、マスクとして用いたレジス
ト3を除去した断面を第5図Cに示した。膜厚0.6μ
mの表面に0.1μmの凹凸を形成したSi○22上に
スパッタ蒸着法でタングステンを形成した状態の断面図
が第5図dである。この状態の試料のタングステンの密
着性を評価した結果、臨界荷重は680gwであり、凹
凸を形成しない場合の360g%lに比して、密着性が
大きく改善された。The sample in Fig. 5a is treated in oxygen plasma for 2 minutes to etch a part of the resist, forming an island-like resist on 5iOz2, as shown in Fig. 5. 0.1μ by plasma etching using
FIG. 5C shows a cross section after etching m5ioz and removing the resist 3 used as a mask. Film thickness 0.6μ
FIG. 5d is a cross-sectional view of a state in which tungsten is formed by sputter deposition on Si22 with 0.1 .mu.m unevenness formed on the surface of tungsten. As a result of evaluating the tungsten adhesion of the sample in this state, the critical load was 680 gw, which was significantly improved as compared to 360 g%l when no unevenness was formed.
以上、W配線とWSix配線について説明したが、配線
材料としてW以外の高融点金属やこれら金属の化合物を
用いても同様の効果がある。上記実施例でわかるように
、窪みや突起の形状は逆テーバの場合が最も効果的であ
り、その寸法は下地及び形成する薄膜の膜厚、薄膜のパ
ターン等を考慮して決定する。窪み及び突起の形成は、
上記の記載例の他に、液エツチング材料に応じてエツチ
ングガスやエツチング液を用いた加工技術の適用が可能
である。Although the W wiring and the WSix wiring have been described above, similar effects can be obtained even if high melting point metals other than W or compounds of these metals are used as the wiring material. As can be seen from the above embodiments, the shape of the depressions and protrusions is most effective when they are inverted tapered, and the dimensions are determined by taking into account the underlying material, the thickness of the thin film to be formed, the pattern of the thin film, etc. The formation of depressions and protrusions is
In addition to the examples described above, processing techniques using etching gas or etching liquid can be applied depending on the liquid etching material.
本発明によれば、薄膜の密着性を著しく向上できるので
、LSIの製造分野においては、薄膜の剥離による不良
発生率を著しく低下させることができる。また、本発明
によれば、製造工程中における積層薄膜の応力や歪みに
関する制限条件を緩和できるので、経済性、効率向上の
効果を有する。According to the present invention, the adhesion of the thin film can be significantly improved, so that in the field of LSI manufacturing, the incidence of defects due to peeling of the thin film can be significantly reduced. Further, according to the present invention, the restrictive conditions regarding stress and distortion of the laminated thin film during the manufacturing process can be relaxed, so that it has the effect of improving economy and efficiency.
第1図は本発明の一実施例のタングステン配線の断面図
、第2図は窪みをもつ5ins上W薄膜の痛みと臨界荷
重の関係を示す測定図、第3図は5iOz上に形成した
W S i xのXと臨界荷重との関係を示す測定図、
第4図はLSIの配線工程におけるS↓O2とWとの密
着性を示す臨界荷重の推移の説明図、第5図は本発明の
一実施例の工程説明のための断面図、第6図は本発明の
一実施例の試料表面組織の形状を示す走査電子顕微鏡写
真である。
1・・・Si基板、2・・・Si熱酸化膜、3・・・リ
ン拡散層、4・・・層間絶縁膜1.5・・・層間絶縁膜
1に形成した窪み、6・・・タングステン配線、7・・
・タングステン配線に形成した窪み、8・・・層間絶縁
膜2.9・・・レジスト。
第 3 阻
第 2 口
第 4 図
7み2度 (憩ぼり
t Stk扱
5LI−叛
SL□z
タンク”ステ゛ノ
Lダスト
b 日
S乙O2Fig. 1 is a cross-sectional view of a tungsten wiring according to an embodiment of the present invention, Fig. 2 is a measurement diagram showing the relationship between pain and critical load of a W thin film formed on 5 ins. A measurement diagram showing the relationship between X of S i x and critical load,
Fig. 4 is an explanatory diagram of the transition of critical load showing the adhesion between S↓O2 and W in the LSI wiring process, Fig. 5 is a sectional view for explaining the process of an embodiment of the present invention, and Fig. 6 is a scanning electron micrograph showing the shape of a sample surface structure in an example of the present invention. DESCRIPTION OF SYMBOLS 1... Si substrate, 2... Si thermal oxide film, 3... Phosphorus diffusion layer, 4... Interlayer insulating film 1.5... Recess formed in interlayer insulating film 1, 6... Tungsten wiring, 7...
- Hollow formed in tungsten wiring, 8... interlayer insulating film 2.9... resist. 3rd barrier 2nd mouth 4 Figure 7 2nd degree (Ikubori t Stk handling 5LI-Rebellion SL□z Tank "Stenno L Dust b Niss Otsu O2
Claims (1)
または突起を形成させた後、薄膜を形成することを特徴
とする微細配線の形成方法。 2、下地表面に窪みまたは突起を形成する際に、固体ま
たは液体の粒状物質を含む液体を下地表面に塗布し、該
下地表面上に上記粒状物質のパターンを形成し、該粒状
物質パターンをマスクとして上記下地表面をエッチング
する工程を含む請求項第1項記載の微細配線の形成方法
。 3、下地表面に窪みまたは突起を形成する際に、レジス
トパターンをマスクとして該下地表面をエッチングする
ことを特徴とする請求項第1項記載の微細配線の形成方
法。 4、レジストパターンを形成する際に、レジストと塗布
用硅素化合物(SOG)の混合物を下地表面に塗布する
工程を含むことを特徴とする請求項第3項記載の微細配
線の形成方法。 5、レジストパターンを形成する際に、光、X線、電子
線のいずれかをレジストに照射することを特徴とする微
細配線の形成方法。 6、形成された窪みの深さまたは突起の高さの寸法が0
.01μm以上でかつ、下地上に形成する薄膜の膜厚以
下であることを特徴とする請求項第1項記載の微細配線
の形成方法。 7、薄膜としてW、Mo、タングステン硅化物、チタン
硅化物、TiW、TiN、Al、Cuの中の少なくとも
一つを適用することを特徴とする請求項第1項乃至第6
項記載の微細配線の形成方法。 8、薄膜を形成する際に、CVD法またはスパッタ蒸着
法を使用することを特徴とする請求項第1項乃至第7項
記載の微細配線の形成方法。[Scope of Claims] 1. A method for forming fine wiring, which comprises forming a thin film after forming depressions or protrusions on the surface of a base when laminating thin films in close contact with each other. 2. When forming depressions or protrusions on the base surface, a liquid containing solid or liquid particulate matter is applied to the base surface, a pattern of the above-mentioned particulate matter is formed on the base surface, and the particulate matter pattern is masked. 2. The method for forming fine wiring according to claim 1, further comprising the step of etching the surface of the base as a step. 3. The method for forming fine interconnects according to claim 1, wherein when forming the depression or protrusion on the surface of the base, the surface of the base is etched using a resist pattern as a mask. 4. The method for forming fine wiring according to claim 3, further comprising the step of applying a mixture of a resist and a silicon compound for coating (SOG) to the underlying surface when forming the resist pattern. 5. A method for forming fine wiring, which comprises irradiating the resist with light, X-rays, or electron beams when forming the resist pattern. 6. The depth of the formed depression or the height of the protrusion is 0
.. 2. The method for forming fine wiring according to claim 1, wherein the thickness is 0.1 μm or more and less than the thickness of the thin film formed on the base. 7. Claims 1 to 6, characterized in that at least one of W, Mo, tungsten silicide, titanium silicide, TiW, TiN, Al, and Cu is used as the thin film.
The method for forming fine wiring described in Section 1. 8. The method for forming fine wiring according to any one of claims 1 to 7, characterized in that a CVD method or a sputter deposition method is used when forming the thin film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28358988A JPH02130828A (en) | 1988-11-11 | 1988-11-11 | How to form fine wiring |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28358988A JPH02130828A (en) | 1988-11-11 | 1988-11-11 | How to form fine wiring |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02130828A true JPH02130828A (en) | 1990-05-18 |
Family
ID=17667465
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP28358988A Pending JPH02130828A (en) | 1988-11-11 | 1988-11-11 | How to form fine wiring |
Country Status (1)
Country | Link |
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JP (1) | JPH02130828A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6858936B2 (en) | 2002-07-01 | 2005-02-22 | Kabushiki Kaisha Toshiba | Semiconductor device having an improved construction in the interlayer insulating film |
US7183189B2 (en) | 1996-12-04 | 2007-02-27 | Seiko Epson Corporation | Semiconductor device, circuit board, and electronic instrument |
US7470979B2 (en) | 1996-12-04 | 2008-12-30 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
-
1988
- 1988-11-11 JP JP28358988A patent/JPH02130828A/en active Pending
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7183189B2 (en) | 1996-12-04 | 2007-02-27 | Seiko Epson Corporation | Semiconductor device, circuit board, and electronic instrument |
US7470979B2 (en) | 1996-12-04 | 2008-12-30 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
US7511362B2 (en) | 1996-12-04 | 2009-03-31 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
US7521796B2 (en) | 1996-12-04 | 2009-04-21 | Seiko Epson Corporation | Method of making the semiconductor device, circuit board, and electronic instrument |
US7842598B2 (en) | 1996-12-04 | 2010-11-30 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
US7888260B2 (en) | 1996-12-04 | 2011-02-15 | Seiko Epson Corporation | Method of making electronic device |
US8115284B2 (en) | 1996-12-04 | 2012-02-14 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board and electronic instrument |
US8384213B2 (en) | 1996-12-04 | 2013-02-26 | Seiko Epson Corporation | Semiconductor device, circuit board, and electronic instrument |
US6858936B2 (en) | 2002-07-01 | 2005-02-22 | Kabushiki Kaisha Toshiba | Semiconductor device having an improved construction in the interlayer insulating film |
US7144804B2 (en) | 2002-07-01 | 2006-12-05 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
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