JPH02127092A - Ic card module - Google Patents
Ic card moduleInfo
- Publication number
- JPH02127092A JPH02127092A JP63280434A JP28043488A JPH02127092A JP H02127092 A JPH02127092 A JP H02127092A JP 63280434 A JP63280434 A JP 63280434A JP 28043488 A JP28043488 A JP 28043488A JP H02127092 A JPH02127092 A JP H02127092A
- Authority
- JP
- Japan
- Prior art keywords
- die pad
- card module
- die
- chip
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07745—Mounting details of integrated circuit chips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Credit Cards Or The Like (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ＩＣカードに装着または内１代されるＩＣカ
ードモジュールに係わり、さらに詳しくは第７図に従来
例に係るＩＣカードモジュール１の縦断面図を示す。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an IC card module that is installed in or included in an IC card, and more specifically, FIG. 7 shows a conventional IC card module 1. A vertical cross-sectional view is shown.
従来のＩＣカードモジュール１において、ダイパッド３
は基板の銅箔又はこれに保護メツキを設けて形成するた
め、表面は平滑（表面ｔ■さＲ，＝２μｍ以下）であり
グイパッド３とｔＣチップ７との接着力が低かった。In the conventional IC card module 1, the die pad 3
Since it is formed by providing the copper foil of the substrate or protective plating on the copper foil, the surface is smooth (surface thickness R = 2 μm or less) and the adhesive force between the Gui pad 3 and the tC chip 7 is low.
尚、図においで、２は基板、４は基板側端子、５は基板
２に設けたスルーホール、６はスルーホール５を介して
基板側端子４と接続される外部端子、８はダイパッド３
とＩＣチップ７を接着するダイボンド材、９は金ワイヤ
、１０は封止樹脂である。In the figure, 2 is a board, 4 is a board side terminal, 5 is a through hole provided in the board 2, 6 is an external terminal connected to the board side terminal 4 via the through hole 5, and 8 is a die pad 3.
9 is a gold wire, and 10 is a sealing resin.
ところで、ＩＣカードモジュール１の製造工程では、第
５図に示すようにダイボンド工程後に、ワイヤボンド工
程及び樹脂封止工程を行わねばならない。このため、ダ
イボンドによるダイパッド３とＩＣチップ７との接着力
が小さいと、ワイヤボンド工程及び樹脂封止工程でＩＣ
チップ７が剥離し、移動してしまうことがあり、両工程
の歩留まりが低いという欠点があった。By the way, in the manufacturing process of the IC card module 1, as shown in FIG. 5, a wire bonding process and a resin sealing process must be performed after the die bonding process. For this reason, if the adhesive strength between the die pad 3 and the IC chip 7 due to die bonding is weak, the IC chip 7 will be damaged during the wire bonding process and the resin sealing process.
The chip 7 may peel off and move, resulting in a low yield in both processes.
本発明は、上記従来製品が持っていたＩＣチップの剥離
という欠点を解決し、ダイパッドとＩＣチップとの接着
力を高め、以て製造歩留まりの向上及び信頼性に優れた
ＩＣカードモジュールを提供することを目的とする。The present invention solves the drawback of IC chip peeling that the conventional products had, improves the adhesive strength between the die pad and the IC chip, and thereby provides an IC card module with improved manufacturing yield and excellent reliability. The purpose is to
この目的のために、本発明は、基板上にダイバンドを設
け、さらにこの上にダイボンド材を介してＩＣチップを
固定すると共に、基板側端子と外部端子を設けたＩＣカ
ードモジュールにおいて、ダイパッド表面を粗化処理し
たことを特徴とする。For this purpose, the present invention provides an IC card module in which a die band is provided on a substrate, an IC chip is fixed thereon via a die bonding material, and substrate side terminals and external terminals are provided. It is characterized by roughening treatment.
本発明では、ダイパッドの表面を粗化することにより、
ダイパッドとダイボンド材との接着面積を大きくでき、
接着力を高めている。また、剪断方向の力に対しては、
ダイパッドの表面の凹凸にダイボンド材が良く食い込み
、剪断方向の耐力を高めている。In the present invention, by roughening the surface of the die pad,
The bonding area between the die pad and die bonding material can be increased,
Improves adhesive strength. In addition, for the force in the shear direction,
The die bonding material bites into the unevenness of the die pad's surface, increasing its strength in the shear direction.
この効果を第１０図に示した。この図から、ダイパッド
表面にＲＺ＝１５μｍ程度の粗化処理を施すことにより
、表面が平滑なダイパッド（従来品）に止ぺ約２０％接
着力が向」ニすることがわかる。This effect is shown in FIG. From this figure, it can be seen that by roughening the die pad surface to RZ=15 μm, the adhesive strength is improved by about 20% compared to the die pad (conventional product) with a smooth surface.
以下、本発明の実施例を図面を参照して説明する。 Embodiments of the present invention will be described below with reference to the drawings.
（実施例１）
第１図、第２図に示すように、トランスファーモールド
・タイプのＩＣカードモジュール１のダイパッドを表面
を粗化したダイパッド１２で構成する。(Example 1) As shown in FIGS. 1 and 2, the die pad of a transfer mold type IC card module 1 is constructed of a die pad 12 with a roughened surface.
トランスファーモールドでは、封止樹脂１０の射出の際
、ＩＣチップ７の側面に大きな力が加わるので、ダイパ
ッド３とＩＣチップ７との接着力の向上は不可欠であり
、特に有効である。また、ワイヤボンディングの際にキ
ャピラリから受ける力に対しても有効である。In transfer molding, a large force is applied to the side surface of the IC chip 7 when the sealing resin 10 is injected, so improving the adhesive strength between the die pad 3 and the IC chip 7 is essential and particularly effective. It is also effective against the force received from the capillary during wire bonding.
（実施例２）
第３図、第４図に示すように、ポツティング封止タイプ
のＩＣカードモジュール１のダイパッドを、表面を粗化
したダイパッド１２で構成する。(Embodiment 2) As shown in FIGS. 3 and 4, the die pad of a potting-sealing type IC card module 1 is constructed of a die pad 12 with a roughened surface.
ポツティング封止では、封止樹脂１０の硬化の際ＩＣチ
ップ７に力が加わるので、ダイパッド１２とＩＣチップ
７との接着力の向上は有効である。In potting sealing, since force is applied to the IC chip 7 when the sealing resin 10 is cured, it is effective to improve the adhesive strength between the die pad 12 and the IC chip 7.
また、ワイヤボンディングの際にキャピラリから受ける
力に対しても有効である。It is also effective against the force received from the capillary during wire bonding.
（実施例３）
第６図に示すように、表面をＲ２＝１０μｍ以上粗化し
たダイパッド１２に、ヤング率５０ｋｇｆ／ ｍ ｍ
”以下のシリコンゴム１）を用いてＩＣチップ７をダイ
ボンドする。(Example 3) As shown in FIG. 6, a die pad 12 whose surface is roughened by R2=10 μm or more has a Young's modulus of 50 kgf/mm.
``Die-bond the IC chip 7 using silicone rubber 1) below.
第８図に示すように、ヤング率の低いシリコンゴム１）
を用いてダイボンドすると、実装工程によって生じるチ
ップ残留応力を大幅に低減できる。As shown in Figure 8, silicone rubber with low Young's modulus 1)
When die-bonding is used, chip residual stress caused by the mounting process can be significantly reduced.
また、第９図に示すように、ダイボンド材としてシリコ
ンゴム１）を用いると、ＩＣカードに外力が加わり、Ｉ
Ｃカードモジュール１が曲げられた場合に、ＩＣチップ
７に生じる応力を軽減でき、以てＩＣカードモジュール
１の強度も高めることができる。ところが、シリコンゴ
ム１）はダイバンド３との接着力が低いことから、これ
だけはワイヤボンディング及び樹脂封止工程での歩留ま
りが低いため、この対策として、従来表面粗さがＲ２＝
２μｍ以下であったダイパッドの表面を粗化することに
より、ＩＣチップ７とダイパッド１２との接着力を高め
るようにしている。ダイパッド表面の粗化処理を施して
いない場合とダイパッド表面をＲｚ＝１５μｍ程度に粗
化した場合について、ＩＣチップ７とダイパッド３，１
２との接着力を調べた結果を第１０図に示す。この図か
ら、ダイパッド表面を粗化することにより（表面粗化ダ
イパッド１２）、ＩＣチップ７とグイパッド１２との接
着力が向上することがわかる。Furthermore, as shown in Fig. 9, when silicone rubber 1) is used as the die-bonding material, external force is applied to the IC card.
When the C card module 1 is bent, the stress generated on the IC chip 7 can be reduced, and the strength of the IC card module 1 can also be increased. However, since silicone rubber 1) has a low adhesive strength with the die band 3, the yield rate in wire bonding and resin sealing processes is low.As a countermeasure, conventional surface roughness R2=
By roughening the surface of the die pad, which was 2 μm or less, the adhesive force between the IC chip 7 and the die pad 12 is increased. IC chip 7 and die pads 3 and 1 for the case where the die pad surface is not roughened and the die pad surface is roughened to approximately Rz = 15 μm.
Figure 10 shows the results of examining the adhesive strength with No. 2. From this figure, it can be seen that by roughening the die pad surface (surface roughened die pad 12), the adhesive force between the IC chip 7 and the goo pad 12 is improved.
以上から、表面を粗化されたグイパッド１２によりＩＣ
チップ７との接着力を向上させたので、ワイヤボンディ
ング及び樹脂封止工程の歩留まりを高めることができる
。From the above, it can be seen that the IC is
Since the adhesive strength with the chip 7 is improved, the yield of wire bonding and resin sealing processes can be increased.
以上説明したように、本発明によれば、ダイパッドの表
面を粗化処理することにより、このダイパッドとＩＣチ
ップの接着力を高めることができるから、製造歩留まり
の向上及びＩＣカードモジュールを用いるＩＣカードの
信頼性の向上を図ることができる。As explained above, according to the present invention, by roughening the surface of the die pad, it is possible to increase the adhesion between the die pad and the IC chip. The reliability of the system can be improved.
第１図は本発明の第１の実施例に係るＩＣカードモジュ
ールの平面図、第２図はその縦断面図、第３図は第２の
実施例に係るＩＣカードモジュールの平面図（第４図は
その縦断面図、第５図はＩＣカードモジュールの製造工
程図、第６図は第３の実施例に係るＩＣカードモジュー
ルの縦断面図、第７図は従来のＩＣカードモジュールの
縦断面図、第８図、第９図、第１０図は参考のための各
種の特性図である。
１・・・ＩＣカードモジュール、２・・・基手反、３・
・・ダイパッド、４・・・基板側端子、５・・・スルー
ホール、６・・・外部端子、７・・・ＩＣチップ、８・
・・ダイボンド材、９・・・金ワイヤ、１０・・・封止
樹脂、１）・・・シリコンゴム、１２・・・表面粗化ダ
イパッド。
第
図
第
図
第
図
第
図
第
図
第
図
（Ｒ２ｌ１２Ｊｉｒｎ議下）
（Ｒｚ ｍ １５訓１）FIG. 1 is a plan view of an IC card module according to a first embodiment of the present invention, FIG. 2 is a longitudinal sectional view thereof, and FIG. 3 is a plan view (fourth 5 is a manufacturing process diagram of the IC card module. FIG. 6 is a vertical sectional view of the IC card module according to the third embodiment. FIG. 7 is a vertical sectional view of the conventional IC card module. Figures 8, 9, and 10 are various characteristic diagrams for reference. 1... IC card module, 2... base plate, 3...
... Die pad, 4... Board side terminal, 5... Through hole, 6... External terminal, 7... IC chip, 8...
...Die bonding material, 9...Gold wire, 10...Sealing resin, 1)...Silicon rubber, 12...Surface roughened die pad. Figure Figure Figure Figure Figure Figure Figure (Under R2l12Jirn) (Rz m 15 Precept 1)
Claims (4)
イボンド材を介してＩＣチツプを固定すると共に、基板
側端子と外部端子とを設けたＩＣカードモジユールにお
いて、ダイパツド表面を粗化処理したことを特徴とする
ＩＣカードモジユール。(1) In an IC card module in which a die pad is provided on a substrate, an IC chip is fixed thereon via a die bonding material, and a terminal on the substrate side and an external terminal are provided, the surface of the die pad is roughened. An IC card module featuring
理したことを特徴とする請求項（１）に記載のＩＣカー
ドモジユール。(2) The IC card module according to claim 1, wherein the die pad surface is roughened to an Rz value of 10 μm or more.
２以下のシリコンゴムあるいはシリコンゲルとすると共
に、表面をＲｚ値１０μｍ以上で粗化処理したことを特
徴とする請求項（１）に記載のＩＣカードモジユール。(3) Young's modulus of the die pad material is 50 kgf/mm^
2. The IC card module according to claim 1, wherein the IC card module is made of silicone rubber or silicone gel having an Rz value of 2 or less and whose surface is roughened to an Rz value of 10 μm or more.
キ、エツチングにより行うことを特徴とする請求項（１
）に記載のＩＣカードモジユール。(4) Claim (1) characterized in that the die pad surface is roughened by machining, plating, or etching.
).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63280434A JPH02127092A (en) | 1988-11-08 | 1988-11-08 | Ic card module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63280434A JPH02127092A (en) | 1988-11-08 | 1988-11-08 | Ic card module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02127092A true JPH02127092A (en) | 1990-05-15 |
Family
ID=17625001
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63280434A Pending JPH02127092A (en) | 1988-11-08 | 1988-11-08 | Ic card module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02127092A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003064962A (en) * | 2001-08-30 | 2003-03-05 | Nitto Electric Works Ltd | Panel ventilation system |
| JP2006073825A (en) * | 2004-09-02 | 2006-03-16 | Toshiba Corp | Semiconductor device and packaging method thereof |
| JP2008196714A (en) * | 2007-02-08 | 2008-08-28 | Nitto Electric Works Ltd | Louver for electrical and electronic equipment storage box |
| JP2014203861A (en) * | 2013-04-02 | 2014-10-27 | 三菱電機株式会社 | Semiconductor device and semiconductor module |
-
1988
- 1988-11-08 JP JP63280434A patent/JPH02127092A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003064962A (en) * | 2001-08-30 | 2003-03-05 | Nitto Electric Works Ltd | Panel ventilation system |
| JP2006073825A (en) * | 2004-09-02 | 2006-03-16 | Toshiba Corp | Semiconductor device and packaging method thereof |
| JP2008196714A (en) * | 2007-02-08 | 2008-08-28 | Nitto Electric Works Ltd | Louver for electrical and electronic equipment storage box |
| JP2014203861A (en) * | 2013-04-02 | 2014-10-27 | 三菱電機株式会社 | Semiconductor device and semiconductor module |
| US9613888B2 (en) | 2013-04-02 | 2017-04-04 | Mitsubishi Electric Corporation | Semiconductor device and semiconductor module |
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