JPH02123743A - Manufacturing method of thin film transistor - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Previous Requirements] A method for manufacturing a thin film transistor used to drive pixels of a display panel using liquid crystal, etc., which reduces the mobility of carriers in an operating semiconductor film of the thin film transistor. With the aim of controlling the threshold voltage without causing any damage, in the manufacture of thin film transistors in which a gate electrode, a gate insulating film, an amorphous silicon film, etc. are laminated in this order on an insulating substrate, the amorphous silicon film is exposed to plasma. After forming a film with a predetermined thickness by the CVD method, the surface of the amorphous silicon film is exposed to a plasma atmosphere created by switching the reaction gas to a gas containing a group III or V element, and a predetermined thickness is formed from the surface of the film. I at the depth of
A special (industrial) method characterized by including a step of implanting a group II or group V element and forming a doped layer containing the group III or V element in the surface layer of the amorphous silicon film. Field of Application) The present invention relates to a method of manufacturing a thin film transistor used to drive pixels of a display panel using liquid crystal or the like.

[Conventional technology]

BACKGROUND ART Recently, in display panels using liquid crystals, an active matrix type is often used in which a nonlinear element is provided for each pixel and each pixel is driven by one nonlinear element.

Among the nonlinear elements that are widely used is an inverted staggered thin film transistor (hereinafter referred to as an inverted staggered TPT).

FIG. 3 shows a side sectional view of the main part of this inverted staggered TPT.

In the figure, l is a transparent insulating substrate, for example a glass substrate,
2 is a gate insulating film; 3 is an amorphous silicon film (hereinafter referred to as the a-5i film); 4 is a doped layer formed by implanting a group III or V element into the surface layer of the a-3i film; G is a gate electrode, S is a source electrode, and D is a drain electrode.

Next, as shown in FIG. 5, the conventional inverted staggered type T P
The method for forming T will be explained step by step.

See Figure 5 (a); titanium (Ti) is coated on the surface of the glass substrate l.
) was vacuum-deposited to a film thickness of about 500 people, and only the region of the Ti film that would become the gate electrode G was masked with a resist to remove unnecessary T.
After removing one film by etching, the resist is removed and a gate electrode G is formed.

See Figure 5 (b); surface of glass substrate 1 and gate electrode G
- Silicon nitride is deposited on the surface by a low-pressure plasma CVD method using a reaction gas in which monosilane gas (SiHa) and ammonia gas (NH3) are mixed at a predetermined molar ratio of flow rates, for example, monosilane gas (SiHa) and ammonia gas (NH3) at a flow rate molar ratio of 1 and 2, respectively. A gate insulating film 2 is formed by depositing (SiN) to a thickness of about 3,000.

Refer to FIG. 5(c); the above plasma CV
By method D, amorphous silicon is deposited on the surface of the gate insulating film 2 to a thickness of about 100 wafers to form an a-3t film 3 which is an active semiconductor film.

Refer to FIG. 5(d); On the surface of the a-3T film 3, monosilane gas and diborane gas (B2H,
) A doped layer 4 doped with boron (B) is formed to a thickness of about 200 layers using a plasma CVD method using a reactive gas containing .

Refer to FIG. 5 (E); After vacuum-depositing aluminum (AI) for electrodes to a thickness of about 1000 on the surface of the doped layer 4, the source electrode S and drain electrode will be formed on this At film. Mask only the area with resist.

Then, in this state, the unnecessary AI film is removed by etching, and the resist is further removed to form a source electrode S and a drain electrode made of the AI film.

Since the threshold voltage of this TPT is set on the positive side, stable pixel driving is possible even when applied to the gate-connected facing type matrix liquid crystal display device proposed in Japanese Patent Application No. 61-212696. It is valid.

[Problem to be solved by the invention]

As mentioned above, in the conventional method, a
After forming the -3i film 3, II
The doped layer 4 doped with a predetermined amount of a group I or V element was formed by a plasma CVD method or the like.

However, when the doped layer 4 is formed in this way, the above-mentioned elements of the flute group or the
It penetrates into the i-film 3.

As a result, even if the threshold voltage can be controlled, there is a problem in that the drain current (d) during operation is reduced due to a decrease in the mobility of electrons in the aSi film or of the genuine bill.

Therefore, the present invention provides an FJ in which the threshold voltage can be controlled and the drain current 1d does not decrease when the operation is on.
II! The object of the present invention is to provide a method for manufacturing a J transistor.

[Means to solve the problem]

In the present invention, as shown in FIG. 1, a gate electrode G, a gate insulating film 2. In manufacturing a thin film transistor formed by laminating the amorphous silicon film 3 and the like in this order, the amorphous silicon film 3 is subjected to plasma CVD.
After forming a film with a predetermined thickness by method D, the reaction gas is
The surface of the amorphous silicon film 3 is exposed to a plasma atmosphere formed by switching to a gas containing a group I or V element, and a group III or V element is implanted into a predetermined depth from the surface of the film. , the amorphous silicon film 3
The problem is solved by a method for manufacturing a thin film transistor, which comprises a step of forming a doped layer 4 containing the group III or group V element on the surface layer of the thin film transistor.

[For production]

As shown in FIG. 2, when a gas containing a group III or V element, such as boron, is brought into a plasma state by plasma CVD and the surface of the a-3t film 3 is exposed to the plasma atmosphere, the boron is implanted into the a-3i film.

The depth of this injection is determined by the discharge power and gas pressure that form the plasma state, so by appropriately selecting these sizes, it is possible to implant from the surface of the a-3i film 3 to a predetermined depth. Boron implantation and deeper a-3i
It can be prevented from being injected into the membrane.

Therefore, it is possible to partially form a doped layer implanted with a Group III or Group V element that controls the threshold voltage only in the surface layer of the a-3T film.

As a result, it is possible to provide an inverted staggered TFT in which the threshold voltage is controlled and the drain current Id during operation does not decrease.

〔Example〕

An example of manufacturing an inverted staggered TPT according to the present invention will be explained in the order of steps with reference to FIG.

Refer to FIG. 1 (A); After vacuum-depositing Ti on the surface of the glass substrate 1 to form a Ti film with a thickness of approximately 500 mm, a resist (not shown) is applied to the Ti film in the region that will become the gate electrode G. The unnecessary Ti film is removed by etching by masking only the Ti film.

Thereafter, the resist is removed and a gate electrode G is formed on the glass substrate.

Refer to FIG. 1 (b); using a reaction gas in which silane gas and ammonia gas are mixed at a flow rate molar ratio of approximately 1:2, the temperature of the glass substrate 1 is approximately 250°C, and the pressure of the reaction gas is 0.
By low pressure plasma CVD method at about 1 to I Torr,
300 μm of iN was applied to the surface of the gate electrode G and the surface of the glass substrate 1.

The gate insulating film 2 is formed by depositing the film to a thickness comparable to that of a human body.

Refer to FIG. 1 (c); without breaking the vacuum of the reaction tank in which the gate insulating film 2 is formed, the reaction gas is switched to a reaction gas consisting of a mixture of silane gas and hydrogen gas at a flow rate molar ratio of approximately 1:9. , set the temperature of the glass substrate 1 to around 250°C,
Amorphous silicon is deposited on the surface of the gate insulating film 2 to a thickness of about 200 cm using a low-pressure plasma CVD method with the pressure of the reaction gas set at about 0.1 to 17'orr, thereby forming an a-3i film 3. form.

See Figure 1 (d); Without breaking the vacuum in the reaction tank in which the a-3i film 3 was formed, the reaction gases are mixed with hydrogen gas at a flow rate of silane gas and diborane gas at a flow rate of about 0.1% by molar ratio. At the same time, the degree of vacuum of this mixed gas is changed to 0. Plasma is generated under the following conditions: I Torr, the temperature of the glass substrate 1 is set to 250'C, the discharge power is 50W, and the discharge frequency is 13.56M11z.

The surface of the a-3i film 3 is exposed to this plasma atmosphere for about 10 minutes to remove boron (B) from the surface of the a-3i film 3.
Injected to a depth of about 0.00 people, this caused the a-3t membrane 3
A doped layer 4 is formed on the surface.

Refer to FIG. 1 (E); After vacuum-depositing aluminum (AI) to a thickness of about 1,000 on the surface of the doped layer 4, only the regions on the AI film that will become the source electrode S and the drain electrode are formed. mask with resist.

Then, in this state, the unnecessary AI film is removed by etching, and then the resist is removed to form a source electrode S and a drain electrode.

This completes an inverted staggered TPT.

Therefore, in the inverted staggered TPT formed by the above process, boron is injected from the surface to a depth of about 100 depths to form the doped layer 4, but boron is injected into the remaining 100 depths. You will have a pure a-3i film with no implants.

As a result, the threshold voltage can be shifted in the positive direction as before, and the drain current Td
will not decrease.

FIG. 4 shows an example of drain current (d) - gate voltage (Vg) characteristics of the TPT according to the embodiment.

As is clear from this figure, the drain current 1d of the TPT according to the present invention is sufficiently larger than the drain current 1d of the conventional TFT, and is significantly improved.

[Effects of the Invention] As explained above, according to the manufacturing method of the present invention, the threshold voltage is shifted, for example, in the positive direction, and an inverted staggered structure having a drain current 1d-gate voltage Vg characteristic sufficient for practical use is obtained. Type TPT can be provided.

Therefore, when the inverted staggered TPT according to the present invention is applied to the pixel driving element of the gate-connected opposing type liquid crystal display device described above, it is possible to provide a display device with good display quality.

[Brief Description of the Drawings] Figure 1 shows an inverted staggered TPT according to an embodiment of the present invention.
2 is a side cross-sectional view of the main parts explaining the manufacturing method step by step; FIG. 2 is a diagram showing an example of the boron concentration in the film when the a-3i film in TPT shown in FIG. Figure 3 is a sectional side view of the main part of an inverted staggered TPT, Figure 4 is a drain current 1d and gate voltage characteristic diagram for comparison between the embodiment of the present invention and a conventional example, and Figure 5 is a conventional inverted staggered TFT. FIG. 3 is a side cross-sectional view of a main part showing a manufacturing example of the same in order of steps. In the figure, 1 is a glass substrate, 2 is a gate insulating film, 3 is an a-3i film, 4 is a doped layer, G is a gate electrode, S is a source electrode, and D is a drain electrode. G boot'tl&ノ托呵vst 帥某某面面閏１ fig.a-5i1'1lalilren4y(＾)さ１廓＾東FT,=八す3 α-5; 弥奓E111事I? Multi-L plus"n l1kg hand Aokawa Sarachu-1 possible 1 concentration r-f
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Claims (1)

[Claims] In manufacturing a thin film transistor in which a gate electrode (G), a gate insulating film (2), an amorphous silicon film (3), etc. are laminated in this order on an insulating substrate (1), the amorphous silicon film (3) is deposited by plasma CVD. After forming the amorphous silicon film (3) to a predetermined thickness by a method, the surface of the amorphous silicon film (3) is exposed to a plasma atmosphere created by switching the reaction gas to a gas containing a Group III or V element. A group III or V element is implanted to a predetermined depth from the amorphous silicon film (3), and a doped layer (4) containing the group III or V element is formed in the surface layer of the amorphous silicon film (3).
1. A method for manufacturing a thin film transistor, comprising the step of forming a thin film transistor.