JPH02123640U - - Google Patents
Info
- Publication number
- JPH02123640U JPH02123640U JP2998889U JP2998889U JPH02123640U JP H02123640 U JPH02123640 U JP H02123640U JP 2998889 U JP2998889 U JP 2998889U JP 2998889 U JP2998889 U JP 2998889U JP H02123640 U JPH02123640 U JP H02123640U
- Authority
- JP
- Japan
- Prior art keywords
- address
- selected signal
- outputs
- memory element
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
Description
第１図は本考案の一実施例の構成を示す回路ブ
ロツク図、第２図は前記実施例の使用状態を示す
説明図である。
１０……設定アドレス・バス、１２……設定ア
ドレス・ラツチ部、１４……コンパレータ、１６
……バス方向変換部、１８……アドレス・バス、
２０……メモリ素子、２２……制御部、２４……
制御回路、２６……トランジスタ、２８……デー
タ・バス、３０……アドレス・デコーダ。
FIG. 1 is a circuit block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is an explanatory diagram showing the usage state of the embodiment. 10... Setting address bus, 12... Setting address latch section, 14... Comparator, 16
... bus direction conversion section, 18 ... address bus,
20...Memory element, 22...Control unit, 24...
Control circuit, 26...transistor, 28...data bus, 30...address decoder.
Claims (1)
き込みが行なわれるとともにセレクテツド信号を
出力するメモリ素子に対し、アドレス・バス上に
出力されたアドレスをデコードしてアクセスする
アドレス・デコーダにおいて、 前記セレクテツド信号に基づいて、このセレク
テツド信号を出力したメモリ素子のアドレス情報
を前記アドレス・バスに出力するアドレス出力手
段を備えたこと特徴とするアドレス・デコーダ。[Claims for Utility Model Registration] An address and an address that decode and access an address output on an address bus to a memory element that is selected from among a plurality of memory elements, data is written, and outputs a selected signal. An address decoder comprising: address output means for outputting address information of a memory element that outputs the selected signal to the address bus based on the selected signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2998889U JPH02123640U (en) | 1989-03-16 | 1989-03-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2998889U JPH02123640U (en) | 1989-03-16 | 1989-03-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02123640U true JPH02123640U (en) | 1990-10-11 |
Family
ID=31254649
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2998889U Pending JPH02123640U (en) | 1989-03-16 | 1989-03-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02123640U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5817587A (en) * | 1981-07-23 | 1983-02-01 | Mitsubishi Electric Corp | Blank area controller for main memory |
| JPS6095649A (en) * | 1983-10-28 | 1985-05-29 | Fujitsu Ltd | Memory card allocation method |
-
1989
- 1989-03-16 JP JP2998889U patent/JPH02123640U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5817587A (en) * | 1981-07-23 | 1983-02-01 | Mitsubishi Electric Corp | Blank area controller for main memory |
| JPS6095649A (en) * | 1983-10-28 | 1985-05-29 | Fujitsu Ltd | Memory card allocation method |
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