JPH02121589A - High-efficiency coding device for picture signal - Google Patents

Abstract

PURPOSE:To improve the quality of a reproduced picture and reduce the number of control codes by performing transmitting and thinning processes in accordance the size of an estimation error of plural interpolating picture elements, and transmitting a control code indication indicating transmission or thinning together with the data of transmitted picture elements. CONSTITUTION:An estimated value is calculated from two picture element data (a) and (b) taken out to output terminals 4 and 5 of a peripheral picture element taking out circuit 2. An estimated value 1/2(a+b) is formed by means of an adder circuit 13 and 1/2-multiplication circuit 14. The estimated value is supplied to a subtraction circuit 15 by which the difference between the estimated value and a real value is calculated and an estimated error is obtained from a absolute value production circuit 16. A threshold value is supplied to the other input terminal of a comparator circuit 17 from a terminal 18. The comparator circuit 17 performs thinning when estimated error is the same as or smaller than a threshold value and makes no thinning when estimated value is larger than the threshold value. Thus the data of each picture element on which transmission/thinning is controlled are transmitted together with one-bit control code indicating the transmission/thinning.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a highly efficient encoding device for an image signal such as a television signal, and particularly to one using subsampling.

[Summary of the invention]

In this invention, basic pixels regularly located among a plurality of pixels having a temporal or spatial arrangement are transmitted, and the basic pixels are used to generate a plurality of interpolated pixels between the basic pixels. When prediction is made and the prediction error is large, the interpolation pixel located approximately at the center of the interpolation pixels is transmitted, and when the prediction error is small, multiple interpolation pixels are thinned out and the basic pixel and the interpolation pixel are separated. This is used to predict the next step of fineness, and depending on the size of the prediction error, transmission and thinning are performed. By repeating the steps of transmission and thinning, all pixels are transmitted. Alternatively, thinning processing is performed, and a control code indicating the transmission or thinning processing is transmitted together with the transmitted pixel data. According to this invention, the density of subsampling is changed according to the characteristics of minute parts of the image, the restored image quality can be improved, a high compression rate can be obtained, and the number of control codes to be transmitted can be reduced. can.

[Conventional technology]

When transmitting a digital video signal, a known method for compressing the amount of data to be transmitted compared to the original amount of data is to thin out pixels by subsampling and lower the sampling frequency. As one type of subsampling, a method has been proposed in which image data is thinned out to %, and a subsampling point and a 2-bit flag indicating the position of the subsampling point used during interpolation are transmitted. If the 1+1hil data of digital video I, ;3 is 8 bits, adding 2 bits of flag,
There are 5 bits per pixel, and the compression ratio is (5/8).

In this conventional sub-sampling, since the sub-sampling pattern is always the same, there is a problem in that the restored image quality is noticeably degraded in areas such as the ring 76 of the object in the image. In particular, when the subsampling rate is set higher than %, the image quality deteriorates significantly.

In order to solve the above-mentioned problems, the applicant of the present application, as described in Japanese Patent Application No. 110098/1983,
Divide one image into many two-dimensional blocks, find the difference (dynamic range) between the maximum and minimum values of multiple pixel data in this block, and set the subsampling period according to the dynamic range of the block. A variable encoding method is proposed.

That is, for blocks with a small dynamic range, it is determined that the image is a flat image and the subsampling period is lengthened, for example (1/8), and for blocks with a relatively large dynamic range, changes are made. It is determined that the image is a certain image, and the subsampling period is set to ('A).Furthermore, for a block with an extremely large dynamic range, it is determined that the image changes rapidly, and subsampling is not performed.

As mentioned above, a high-efficiency encoding device that selectively switches the subsampling period according to the dynamic range sets the subsampling period in units of blocks, so it is possible to determine the quality of the restored image in each block. This had the disadvantage that block distortion was noticeable. Furthermore, there are limits to the types of subsampling cycles that can be selected, and the adaptability to image characteristics is insufficient.

The applicant has proposed a high-efficiency encoding device for image signals that does not cause such block-by-block deterioration, can form arbitrary subsampling densities that are adapted to image characteristics, and can obtain good restored images. (Special application 1986-
208957).

In addition, it has the same advantages as the invention described in the above application specification, uses real data when calculating interpolation errors, and therefore can perform real-time processing, and can generate image signals that can be used for moving images. A high-efficiency encoding device has been proposed by the applicant of the present invention (see specification of Japanese Patent Application No. 1985-6285210).

[Problem to be solved by the invention]

For the previously proposed variable density subsampling,
Since a 1-bit control code indicating transmission and thinning is assigned to all pixels, there is a problem in that there are many control codes to be transmitted.

Therefore, an object of the present invention is to create an image that does not cause block-by-block deterioration, can form an arbitrary subsampling density that is adapted to the characteristics of the image, has the advantage of obtaining a good restored image, and can reduce control coats. An object of the present invention is to provide a highly efficient signal encoding device.

(Means for Solving the Problems) In the present invention, basic pixels S1 regularly located among a plurality of pixels having a temporal or spatial arrangement are transmitted, and the basic pixels S1 are transmitted using the basic pixels S1. A plurality of interpolation pixels S5 and S9.313 located between the same ten pixels are predicted, and when the prediction error is large, the interpolation pixel S9 located approximately in the center of the interpolation pixels is transmitted, and the prediction error is reduced. When it is small, a plurality of interpolation pixels S5, S9, and S13 are thinned out, and the basic pixel S1 and the interpolation pixel are used to predict the next step of fineness. Accordingly, transmission and thinning processing are performed, and by repeating the steps of transmission and thinning processing, transmission or thinning processing of all pixels is performed, and the transmission or thinning processing is performed together with the data of the pixels to be transmitted. A control code indicating this is transmitted.

[Effect]

As an example, (4 samples x 4
The basic pixels Sl located in each pixel (line) are always transmitted without being thinned out. The interpolation pixels other than the basic pixel Sl are thinned out by subsampling or transmitted as they are. This determination is made depending on the size of the predicted error when the thinned out pixels are interpolated using data of surrounding pixels on the receiving side. The prediction error is compared with a threshold value to determine its magnitude. That is, when the prediction error is larger than the threshold, the original data is transmitted because thinning is not possible, and when the prediction error is smaller than the threshold, the original data is not transmitted because thinning is possible.

Subsampling is performed in order from coarse subsampling density to finer subsampling density. In the case of coarse density subsampling that is first performed using the basic pixel S1, a plurality of pixels, for example, three pixels S5, S9, and S13 between the basic pixels SL are predicted, and when the prediction error is small, three pixels are predicted. The pixels S5, S9, and S13 are thinned out at once.

Is transmission/thinning controlled in this way? The data of the removed pixel and the data of the basic pixel S1 are transmitted.

A 1-bit control code is added to each pixel data to indicate transmission/thinning. On the receiving side, it is determined whether to use the received original data or the interpolated value by looking at this control code.

〔Example〕

The present invention will be explained below with reference to the drawings. This description will be given in the following order.

a. Overall configuration of an embodiment 1. Surrounding pixel extraction circuit C1. Prediction error of three pixels between basic pixels d. Write control circuit e. Modification a. Overall configuration of an embodiment. , an embodiment of the present invention is shown, and in FIG. 1, a digital image signal, for example a digital video signal, is supplied to an input terminal indicated by l. This digital video signal has a sampling frequency of 13.5 (MHz), for example, and one pixel data is 8 bits.

A digital video signal is supplied to a blocking circuit LA. As shown in FIG. 2, the blocking circuit IA converts one field (or one frame) of image into a large number of blocks B.
ll, B12. ...Subdivide into BNM.

Each block has a (4×4') structure as shown in FIG. 3, and one block includes 16 pixel data. The order of the data generated from the blocking circuit IA is the order of the blocks indicated by the arrows in FIG. Within the block, 16 pixels are transmitted in order from the leftmost pixel of line LL in FIG. 3 to lines L2, L3, and L4.

The output data of the blocking circuit IA is supplied to the peripheral pixel extraction circuit 2. The 0 peripheral pixel extraction circuit 2 extracts peripheral pixel data necessary for transmission and thinning processing. Data of the pixel of interest, which is the target of processing, is taken out to the output terminal 3. Two pieces of pixel data necessary for calculating an interpolation value are taken out from output terminals 4 and 5. The 0 peripheral pixel extraction circuit 2 from which the true value of pixel data is extracted to the output terminal 6.7.8.9 in order to calculate a prediction error will be described later.

Data of the pixel of interest from the terminal 3 of the peripheral pixel extraction circuit 2 is supplied to the gate circuit 10. The gate circuit 10 is
This is for subsampling, and when the gate circuit 10 is on, pixel data is transmitted, and when the gate circuit 10 is off, the pixel data is thinned out.

A bitmap for controlling on/off of the gate circuit 10 is output to an output terminal 12. This bitmap is 1
Each pixel is 0 (logical 0) or 1 (logical 1), and in this example, 0 means thinning out, that is, the gate circuit 10 is turned off, and ■ means transmission, that is, gate circuit 10 is turned off. circuit 1
0 means on. Further, the gate circuit 10 is turned off by a blanking signal.

A predicted value is calculated from two pixel data taken out to the output terminals 4 and 5 of the peripheral pixel extraction circuit 2 (assuming the values of these pixel data are a and b). Addition circuit 1
The predicted value 'A(a+b) is formed by the 3 and η multiplier circuit 14. This predicted value is supplied to the subtraction circuit 15, the difference between the predicted value and the true value is calculated, and this difference signal is supplied to the absolute value conversion circuit 16. A prediction error is obtained from the absolute value conversion circuit 16, and this prediction error is supplied to one input terminal of the comparison circuit 17.

The other input terminal of the comparison circuit 17 is supplied with a threshold value from the terminal 18 . The comparison circuit 17 generates an output signal of O, which means that thinning is allowed when (prediction error≦threshold), and means that thinning is not allowed when (prediction error>threshold). generates an output signal of 1. The threshold value is determined in consideration of the degree of deterioration of restored image quality, compression rate, and the like. The output signal of the comparison circuit 17 is supplied to one input terminal 20a of the switch circuit 19 and the OR gate 21.

Other predicted values are calculated from the two pixel data taken out to the output terminals 4 and 5 of the peripheral pixel extraction circuit 2. A predicted value +A (3a+b) is formed by a multiplication circuit 22, an addition circuit 23, and an A multiplication circuit 24, which triple the pixel data a. This predicted value is supplied to the subtraction circuit 25, the difference between the predicted value and the true value is calculated, and this difference signal is sent to the absolute value conversion circuit 25.
6. A prediction error is obtained from the absolute value conversion circuit 26, and this prediction error is supplied to one input terminal of the comparison circuit 27. The comparison circuit 27 compares the prediction error with a threshold value. The comparison circuit 27 performs the same comparison operation as the comparison circuit 17, and the output signal of the comparison circuit 27 is output from the OR gate 2.
1.

The true value supplied to the subtraction circuit 25 is supplied from the peripheral pixel extraction circuit 2 via the switch circuit 28. Pixel data from the output terminal 6 of the peripheral pixel extraction circuit 2 is supplied to the first input terminal 29a of the switch circuit 28.
The second input terminal 29b of the switch circuit 2 is a terminal to which pixel data is not supplied, and the third input terminal 29b of the switch circuit 28 is
The input terminal 29 ef of is supplied with pixel data from the output terminal 7 of the peripheral pixel extraction circuit 2 .

Furthermore, a multiplication circuit 30, an addition circuit 31, and a doubling circuit 32, which triple the pixel data b, calculate the predicted value S(a+3b).
is formed. This predicted value is supplied to the subtraction circuit 33,
The difference between the predicted value and the true value is calculated, and this difference signal is supplied to the absolute value conversion circuit 34.

A prediction error is obtained from the absolute value conversion circuit 34, and this prediction error is supplied to one input terminal of the comparison circuit 35. The comparison circuit 35 compares the prediction error with a threshold value. The comparison circuit 35 performs the same comparison operation as the comparison circuits 17 and 27, and the output signal of the comparison circuit 35 is supplied to the OR gate 21.

The true value supplied to the subtraction circuit 33 is supplied from the switch circuit 36. First input terminal 37 of switch circuit 36
pixel data from the output terminal 8 of the peripheral pixel extraction circuit 2 is supplied to a, the second input terminal 37b of the switch circuit 36 is a terminal to which no pixel data is supplied, and the third input terminal of the switch circuit 36 is Pixel data from the output terminal 9 of the peripheral pixel extraction circuit 2 is supplied to the terminal 37c.

The switch circuits 19, 28, and 36 are controlled by the selector control circuit 39, in which the output signal of the OR gate 21 is supplied to the other input terminal 20b of the switch circuit 19, and the output signal of the switch circuit 19 is supplied to the write control circuit 38. , the connection state is controlled.

For the write control circuit 38, the selector control circuit 39
output signal is provided. The selector control circuit 39 generates a control signal synchronized with the pixel position. The output signal of the counter 40 is supplied to the selector control circuit 39 . This counter 40 counts the sampling clock from the terminal 41 and is cleared by the block clock of the block period from the terminal 42.

b0 peripheral pixel extraction circuit An example of the peripheral pixel extraction circuit 2 is shown in FIG.

Delay circuits 51.5 and 51.5 are connected to the input terminal 50 to which the digital video signal from the blocking circuit IA is supplied.
2.53.54.55.56.57.58.59.60
．． 61 and 62 are connected in series. Delay circuits 51 and 5
3 is a line delay circuit, which has a delay amount for one line indicated by LD. The delay circuit 52 has a delay amount of 2LD.

The delay circuits 54 to 61 have a delay amount of a sampling period indicated by SD. The delay circuit 62 has a delay amount of 4SD.

FIG. 5 shows the pixel arrangement of l block, where the horizontal pixel interval is the sampling period SD, and the vertical pixel interval is the line period LD. Within the block,
Pixel data is transmitted in the order of S1, S2, S3, . . . 315, S16. The symbols (Δ, ·, mouth, ×, ○) attached to each pixel in this (4×4)8 block represent differences in the interpolation processing performed on the receiving side, as explained below. ing.

First, the pixel S1 denoted by O represents the basic pixel located every 4 lines and every 4 pixels, and 1 pixel for every 16 pixels.
A proportion of basic pixels are always transmitted without being thinned out.

Therefore, the prediction error is naturally 0.

Basic pixel 317 of another block adjacent to basic pixel S1
and Si are used to predict three pixels located between the basic pixels. In this embodiment, pixels S5, S9, and S13 are predicted by vertical interpolation of basic pixels S1 and Si, and similarly, pixels S2, S3, and S4 are predicted by horizontal interpolation of basic pixels S1 and S17. Pixels S9 and S25
Pixels SIO, Sll, 312 are predicted by horizontal interpolation. When all prediction errors for three pixels are below the threshold, the bitmap is set to O and three pixels are thinned out, or when at least one prediction error exceeds the threshold, the bitmap is is set to 1, and the central three pixels S9 (indicated by *), S3 and 5ll (indicated by mouth) are transmitted. When these three pixels cannot be thinned out, a prediction error between each pixel and the average value of the other two pixels is determined, and a decision on transmission or thinning is made according to this prediction error.

Pixels S5, S7, S13, S15 represented by Δ: Comparison with the average value of pixel data located on the upper and lower lines, respectively,
The prediction error is determined.

Pixels represented by × S2, S6, SIO, S14, S4,
S8.312, S16: A prediction error is determined by comparison with the average value of pixels adjacent to the left and right.

Selectors 63 and 64, to which predetermined output signals of the delay circuits 51 to 62 are supplied to the first input terminal aO to the seventh input terminal a6, output two pixel data used to calculate the interpolation value. The terminals 4 and 5 are provided for taking out, respectively. Selectors 63 and 64 are controlled by a selector control signal from ROM 65. The ROM 65 is supplied with a sampling clock synchronized with the output signal of the blocking circuit IA and a block clock having a block period from terminals 66 and 67.

FIG. 6 shows an example of the ROM 65, and 68 is the ROM 6.
5 address counter. The ROM 65 stores 3-bit selector control signals corresponding to the respective positions of the pixels 51 to S16 of one block. However, the 6th
In the figure, for simplicity, (000) (001) (010)
・・・・・・3 bits of (110) are 0.1.2,・
... is shown as 6. When the selector control signal is O,
The selectors 63 and 64 selectively output the data supplied to the input terminal aO, and similarly, according to the selector control signals 1 to 6, the selectors 63 and 64 output the data supplied to the input terminals a1 to a6. Selectively output the data that is displayed.

As can be seen from the selector control signal from the ROM 65 shown in FIG. 6, when each pixel in the block is the pixel of interest, that is,
When the data of the pixel of interest is generated on the output side (output terminal 3) of the delay circuit 57, these selectors 63 and 64 selectively output two pixel data for forming an interpolated value.

A prediction error is formed from the two pixel data taken out from the selectors 63 and 64 (output terminals 4 and 5) using the configuration shown in FIG. 1 as described above.

The two pixel data selected by the selectors 63 and 64 when each of the pixels 31 to S16 shown in FIG. 5 is the pixel of interest will be described below.

When the pixel Sl is the pixel of interest, a selector control signal of 0 is generated, and the selectors 63 and 64 selectively output the data of the pixel of interest that is supplied from the output side of the delay circuit 57 to the input terminal aO. S1 is a basic pixel that is always transmitted, and the prediction error is always 0.

When the pixel S2 is the pixel of interest, the selector control signal (■) is generated. The delay circuit 5 is connected to the input terminal al of the selector 63.
The data of the pixel S1 one sampling period (ISD) before from 8 is supplied, and the input terminal a1 of the selector 64
In this case, I is applied from the output side of the delay circuit 56 to the pixel S2.
Pixel S3 after SD is supplied. Therefore, the data of these two pixels S1 and S3 are sent to the selectors 63 and 6.
4, respectively.

When pixel S3 is the pixel of interest, selector control signal 2 is generated. The input terminal a2 of the selector 63 is supplied with the data of the pixel S1 2 SD before the pixel S3 from the delay circuit 59, and the input terminal a2 of the selector 64 is supplied with the data of the pixel S1 2 SD before the pixel S3.
On the other hand, the pixel S17 after 14SD is supplied from an intermediate stage of the delay circuit 53. That is, the delay circuit 54.5
5.56.57, a delay amount of 4SD is generated, and a delay amount of 103D is generated on the output side of the delay circuit 53 at an intermediate stage of the delay circuit 53. Therefore, the data of these two pixels Sl and S17 are sent to the selectors 63 and 64.
are selected respectively.

When pixel S4 is the pixel of interest, selector control signal 3 is generated. The delay circuit 5 is connected to the input terminal a3 of the selector 63.
The input terminal a3 of the selector 64 is supplied with the data of the pixel 317 after 13SD from the delay circuit 53 to the input terminal a3 of the selector 64. That is, delay circuits 54, 55, 56
．． 57, a delay amount of 4SD is generated, and the delay circuit 53
At an intermediate stage, 9SD is applied to the output side of the delay circuit 53.
amount of delay occurs. These two pixels S3 and 31
7 data are selected by selectors 63 and 64, respectively.

When pixel S5 is the pixel of interest, selector control signal 4 is generated. The delay circuit 6 is connected to the input terminal a4 of the selector 63.
The data of the pixel sl 4SD before the pixel S5 is supplied to the input terminal a4 of the selector 64 from the output side of the delay circuit 53.

Therefore, the data of these two pixels St and S9 are selected by selectors 63 and 64, respectively.

When pixel S6 is the pixel of interest, a selector control signal of 1 is generated. The delay circuit 5 is connected to the input terminal a1 of the selector 63.
The data of the pixel S5 before ISD from 8 is supplied, and the pixel S7 after ISD is supplied to the input terminal al of the selector 64 with respect to the pixel S6. Therefore, the data of these two pixels S5 and S7 are selected by selectors 63 and 64, respectively.

When pixel S7 is the pixel of interest, selector control signal 4 is generated. The delay circuit 6 is connected to the input terminal a4 of the selector 63.
The data of the pixel S3 after 4SD from pixel S7 is supplied to the input terminal a4 of the selector 64 from the output side of the delay circuit 53.

Therefore, the data of these two pixels S3 and Sll are selected by selectors 63 and 64, respectively.

When pixel S8 is the pixel of interest, selector control signal 3 is generated. The delay circuit 5 is connected to the input terminal a3 of the selector 63.
The input terminal a3 of the selector 64 is supplied with the data of the pixel S21 after 13 sD from the delay circuit 53 to the input terminal a3 of the selector 64. Therefore, these two pixels S7
and S21 are selected by selectors 63 and 64, respectively.

When pixel S9 is the pixel of interest, a selector control signal of 5 is generated. As shown in FIG. 4, the input terminal a5 of the selector 63 is supplied with the data of the pixel S1 8 SD before from the delay circuit 62, and the data of the pixel S1 after (4LD-83D) is supplied to the input terminal a5 of the selector 64. Data of pixel Si is supplied. In the block below the block shown in FIG. 5, the position of the pixel 4LD after pixel S9 is pixel S9.
For this pixel, which is the pixel corresponding to (not shown), pixel St is pre-BSD. Delay circuit 51.52.
53 causes a delay amount of 4LD, and the delay circuit 5
4.55.56.57 causes a delay amount of 4SD. Therefore, the output signal from the position 123D relative to the input side of the delay circuit 51 is supplied to the input terminal a5 of the selector 64.

Selectors 63 and 64 select data of pixels S1 and St, respectively.

When pixel SIO is the pixel of interest, a selector control signal of 1 is generated. The input terminal a1 of the selector 63 is supplied with the data of the pixel S9 before ISD from the delay circuit 58, and the input terminal a1 of the selector 64 is supplied with the data of the pixel S11 after ISD for the pixel S10. ing. Therefore, the data of these two pixels S9 and S11 are selected by selectors 63 and 64, respectively.

When pixel Sll is the pixel of interest, selector control signal 2 is generated. The input terminal a2 of the selector 63 has a pixel Sl.
The data of the pixel S9 2SD before l is supplied from the delay circuit 59, and the data of the pixel S25 after 1JSD with respect to the pixel Sll is supplied to the input terminal a2 of the selector 64.
It has been supplied since the middle stage of 3. Therefore, the data of these two pixels S9 and S25 are selected by selectors 63 and 64, respectively.

When pixel S12 is the pixel of interest, selector control signal 3 is generated. The input terminal a3 of the selector 63 is supplied with the data of the pixel Sll before ISD from the delay circuit 58, and the data of the pixel S25 after 13SD with respect to the pixel S12 is supplied to the input terminal a3 of the selector 64. It has been supplied from the middle of 53. Therefore, the data of these two pixels S11 and S25 are selected by selectors 63 and 64, respectively.

When pixel 313 is the pixel of interest, selector control signal 6 is generated. The input terminal a6 of the selector 63 is supplied with the data of the pixel S9 4SD before from the delay circuit 61, and the input terminal a6 of the selector 64 is supplied with (4LD-123
D) Later pixel 5i (7) data is supplied. Fifth
In the block below the block shown in the figure, dLD
The position of the subsequent pixel is a pixel (not shown) corresponding to pixel S13. For this pixel, pixel Si is 12SD
In front. A delay amount of 4LD is generated by the delay circuits 51, 52, 53, and the delay circuits 54, 55, 56, 57
Therefore, a delay amount of 4SD occurs.

Therefore, the output signal from the position -16 SD with respect to the input side of the delay circuit 51 is supplied to the input terminal a6 of the selector 64. The data of these pixels S9 and Si are selected by selectors 63 and 64, respectively.

When the pixel S14 is the pixel of interest, l selector control signals are generated. The input terminal a1 of the selector 63 is supplied with the data of the pixel S13 before ISD from the delay circuit 58, and the input terminal a1 of the selector 64 is supplied with the data of the pixel S15 after LSD for the pixel S14. ing. Therefore, the data of these two pixels S13 and S15 are selected by selectors 63 and 64, respectively.

When pixel S15 is the pixel of interest, selector control signal 6 is generated. The input terminal a6 of the selector 63 is supplied with the data of the pixel Sll 4SD before from the delay circuit 61, and the input terminal a6 of the selector 64 is supplied with (4LD-12
SD) The data of the next pixel Sk is supplied to the input side of the delay circuit 51 from a position of -16 SD. The data of these pixels Sll and Sk are selected by selectors 63 and 64, respectively.

When pixel S16 is the pixel of interest, selector control signal 3 is generated. The input terminal a3 of the selector 63 is supplied with the data of the pixel S15 before the ISD from the delay circuit 58, and the data of the pixel S29 after 13SD with respect to the pixel 316 is supplied to the input terminal a3 of the selector 64. It has been supplied from the middle of 53. Therefore, the data of these two pixels 315 and S29 are selected by selectors 63 and 64, respectively.

As understood from the above description, the two pixel data generated from the output terminals 4 and 5 of the peripheral pixel extraction circuit 2 are added to the adder circuit 13, the X-fold circuit 14, the subtracter circuit 15,
This is processed by the absolute value conversion circuit 16 and the comparison circuit 17, and the comparison circuit 17 generates a bitmap for controlling transmission or thinning of the pixel of interest.

Prediction error of three pixels among C1 basic pixels In this embodiment, when the pixel of interest is S3, S9, or S11, the input terminal 20b of the switch circuit 19 is selected, and when the pixel other than the above is the pixel of interest, Input terminal 20 of switch circuit 19
a is selected.

Further, when the pixel of interest is 33 and Sll, the input terminals 29a and 37a of the switch circuits 28 and 36 are selected,
When the pixel of interest is S9, the input terminals 29c and 37c of the switch circuits 28 and 36 are selected, and when the pixel other than the above-mentioned pixel is the pixel of interest, the input terminals 29b and 37b of the switch circuits 28 and 36 are selected.

The operation when the pixel of interest is 83 will be explained.

As mentioned above, when the pixel S3 is the pixel of interest, the data of the pixel S1 2 SD before the pixel S3 is generated from the output terminal 4 of the peripheral pixel extraction circuit 2, and the data of the pixel S1 2 SD before the pixel S3 is generated from the output terminal 5. On the other hand, pixel S17 occurs after 14SD. Therefore, in the comparison circuit 17, l53-%(S1
The prediction error, denoted +517)l, is compared to a threshold.

The multiplier circuit 22, the adder circuit 23, and the
(3S1+317)) is formed. At this time, since the switch circuit 28 selects the input terminal 29a, the subtraction circuit 25 is supplied with pixel data from the output terminal 6 of the peripheral pixel extraction circuit 2. As is clear from FIG. 4, the pixel S2 before the LSD of the pixel S3 is generated at the output terminal 6. Therefore, in the comparison circuit 27,
The prediction error, denoted S2'A (3S1+517)l, is compared to a threshold.

The multiplier circuit 30, the adder circuit 31, and the
A predicted value of (S1+3S17)) is formed. At this time, since the switch circuit 36 selects the input terminal 37a, the subtraction circuit 33 is supplied with pixel data from the output terminal 8 of the peripheral pixel extraction circuit 2. As is clear from FIG. 4, the pixel S4 after the LSD of the pixel S3 is generated at the output terminal 8. Therefore, in the comparison circuit 35,
The prediction error, represented by Si-S(S1+3317)l, is compared to a threshold.

Comparison circuit 17. Output signals of 27 and 35 are OR gate 2
1, so if the output signal of at least one of the three comparison circuits is 1, the output signal of the OR gate 21 becomes 1. The output signal of OR gate 21 is supplied to write control circuit 38.

The same operation as when the pixel of interest is 33 is performed when the pixel of interest is Sit. As described above, when the pixel S11 is the pixel of interest, the output terminal 4 of the peripheral pixel extraction circuit 2 generates the data of the pixel S9 2 SD before the pixel 311, and the data of the pixel S9 2 SD before the pixel 311 is generated from the output terminal 5. On the other hand, pixel S25 occurs after 14SD. Therefore, in the comparison circuit 17, the prediction error represented by ISl 1 'A (S9+325)l is compared with the threshold value. Also, comparison circuit 2
In 7, l5IO! The prediction error, expressed as /5(3S9+325)l, is compared to a threshold. Furthermore, comparison circuit 3
5, the prediction error, denoted l 312-% (S9+3325), is compared to a threshold.

The output signals of these comparison circuits 17, 27 and 35 are ORed.
Since the signal is supplied to the gate 21, if the output signal of at least one of the three comparison circuits is 1, the output signal of the OR gate 21 becomes 1.

The output signal of OR gate 21 is supplied to write control circuit 38.

The operation when the pixel of interest is 39 will be explained.

As described above, when the pixel S9 is the pixel of interest, the data of the pixel Sl is generated from the output terminal 4 of the peripheral pixel extraction circuit 2, and the data of the pixel St is generated from the output terminal 5. Therefore, in the comparison circuit 17, l 33 'A
The prediction error, denoted by (S 1+S i)l, is compared to a threshold.

The multiplier circuit 22, the adder circuit 23, and the
'A(3S1+5i)) is formed. At this time, since the switch circuit 28 selects the input terminal 29C, the subtraction circuit 25 is supplied with pixel data from the output terminal 7 of the peripheral pixel extraction circuit 2. As is clear from FIG. 4, the pixel S5, which is 4 SD before the pixel S9, is generated at the output terminal 7. Therefore, in the comparison circuit 27,
S 5 Va (3S 1 +S i ) l Te!
The Sarel prediction t,% difference is compared to a threshold.

Multiplication circuit 30, addition circuit 31. By the W multiplication circuit 32, (
'/4(S 1+3S i)) predicted values are formed.

At this time, since the switch circuit 36 selects the input terminal 37C, the subtraction circuit 33 is supplied with pixel data from the output terminal 9 of the peripheral pixel extraction circuit 2. As is clear from FIG. 4, the output terminal 9 has 4S of the pixel S9.
Pixel S13 after D is generated. Therefore, comparison circuit 3
5, the prediction error, expressed as 313%(S1+3Si)l, is compared to a threshold.

Comparison circuit 17. Output signals of 27 and 35 are OR gate 2
1, so if the output signal of at least one of the three comparison circuits is 1, the output signal of the OR gate 21 becomes 1. The output signal of OR gate 21 is supplied to write control circuit 38.

d. Write control circuit The write control circuit 38 to which the output signal of the switch circuit 19 is supplied will be explained with reference to FIGS. 7 and 8. FIG. 7 shows an example of the write control circuit 38.
A bit map (0: thinning, l: transmission) from the switch circuit 19 is supplied to the input terminal indicated by 1. This bitmap is taken out to an output terminal 73 via an adder circuit 72 and is also supplied to a blanking signal generating circuit 74. A memory 43 (see FIG. 1) for generating a bitmap is connected to the output terminal 73.

A control signal from the selector control circuit 39 is supplied to the blanking signal generation circuit 74 via a terminal 75. This control signal is applied to the pixels before and after (S2, S4), (S10.51) when pixel S3.311 or S9 is the pixel of interest.
This is to generate a blanking signal indicating that there is no transmission data at the address 2) or (S5.513). A blanking signal generated by blanking signal generation circuit 74 is supplied to addition circuit 72 via switch circuit 76 . The switch circuit 76 connects to the terminal 75
The pixel of interest is S3, S9, S
At 11, the switch circuit 76 is turned on.

The above write control circuit 38 will be explained with reference to FIG. FIG. 8 shows a bitmap stored in the memory 43, and the bits circled are pixels S3 and S9.
and 311. As shown in FIG. 8A, the pixels S3 and S supplied via the switch circuit 19
When bits 9 and Sll are 1, no blanking signal is generated and bit 1 is written into the memory 43 as is.

As shown in FIG. 8B, when the bits of pixels S3, S9, and Sll supplied via the switch circuit 19 are 0, a blanking signal is generated, and the blanking signal (indicated by The previous bitmap is forcibly marked with an x. Furthermore, Figure 8C
As shown in FIG. 3, when the bits of pixels S3 and Sll are 0 and the bit of pixel S9 is 1, a blanking signal is generated and the blanking signal is selectively written into the memory 43.

e. Modification The present invention can be applied to manual data in scan order without converting the input data to block order.

Further, the present invention has a method in which the prediction error is small, and when performing thinning processing, the data of the pixel to be thinned out may be replaced with a predicted value, and this predicted value may be used in the next step of processing.
In order to perform this processing, it is necessary to configure a peripheral pixel extraction circuit using RAM.

〔Effect of the invention〕

Since this invention uses variable density subsampling without a block structure, it is possible to prevent noticeable deterioration of the restored image on a block-by-block basis. Furthermore, since the present invention uses adaptive variable density subsampling, subsampling is performed with very good adaptability to image features, and the restored image quality can be improved. Furthermore, since this invention uses hierarchical encoding, it is possible to display images that change from coarse to fine without rearranging data, making this invention suitable for still image transmission and image database searches. ing. Furthermore, since the present invention calculates prediction errors using basic pixel data for a plurality of pixels located between basic pixels, it is possible to reduce the amount of bitmap that needs to be transmitted.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIGS. 2 and 3 are route diagrams used to explain an example of a block in this embodiment, and FIG. 4 is a block diagram of an example of a peripheral pixel extraction circuit. , FIG. 5 is a route diagram showing the arrangement of pixel data used to explain the peripheral pixel extraction circuit, FIG. 6 is a block diagram showing the configuration for generating the selector control signal, and FIG.
8 are a block diagram of an example of a write control circuit and a route diagram for explaining its operation. Explanation of main symbols in the drawings 1: Input terminal, 2: Surrounding pixel extraction circuit, 3: Terminal from which pixel of interest is extracted, 10: Gate circuit, 11: Data output terminal, 12: Bitmap output terminal, 17.27 .35: Comparison circuit, 38: Write control circuit. Fig. 2 r”o,,,'7 ′δゞ. Agent Patent attorney Tadashi Sugiura Chisho 5 included h & + helmet circuit, -4 case j Fig. 1

Claims (1)

[Scope of Claims] Transmits regularly located basic pixels among a plurality of pixels having a temporal or spatial arrangement; When the error in the prediction is large, the interpolation pixel located approximately in the center of the interpolation pixels is transmitted, and when the error in the prediction is small, the plurality of interpolation pixels are thinned out. perform prediction of the next step of fineness using the basic pixels and the interpolation pixels, and perform transmission and thinning processing according to the size of the prediction error, and perform the transmission and thinning processing. By repeating the steps, all pixels are transmitted or thinned out, and together with the transmitted pixel data, a control code indicating the transmission or thinning process is transmitted. Encoding device.