JPH021155A - semiconductor equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] Regarding a semiconductor device having a structure in which a polycrystalline silicon electrode or wiring is in contact with an extremely thin insulating film, when increasing the degree of integration, fluctuations in dark value, deterioration of gate breakdown voltage, etc. In order to prevent the occurrence of defects in The polycrystalline silicon film in the part of the polycrystalline silicon film in contact with the insulating film having at least the minimum film thickness contains a lower concentration of impurities than the other parts of the polycrystalline silicon film, or a dielectric film is formed on the storage electrode. , a dynamic memory cell having a memory cell capacity formed by stacking opposing electrodes, wherein the opposing electrode is made of a polycrystalline silicon film, and the impurity concentration thereof is equal to the impurity concentration of the polycrystalline silicon film constituting another electrode or wiring. Construct a semiconductor device with a lower cost than the above.

[Industrial application field]

The present invention relates to improvements in semiconductor devices, particularly semiconductor devices having a structure in which polycrystalline silicon electrodes or wiring are in contact with an extremely thin insulating film.

In MIS type semiconductor devices such as LSIs, gate insulating films such as silicon dioxide (Si02) films are becoming thinner and thinner as elements become smaller.

The thinning of this gate insulating film is less than 100 people, for example, 5
When the number of MIS semiconductor devices decreases to about 0, the characteristics of the MIS semiconductor device begin to fluctuate and deteriorate, such as fluctuations in dark values and deterioration in gate withstand voltage, so improvements are desired.

[Prior Art] Polycrystalline silicon (poly-Si) is often used as the material for lower-layer electrodes or wiring including gate electrodes in MIS semiconductor devices, but conventional electrode wiring made of acid poly-Si has low wiring resistance. In order to reduce the impurity concentration, the entire structure was formed to have a uniform high impurity concentration. This also applies to stacked dynamic memory cells, and the polycrystalline silicon film that forms the counter electrode of the memory cell capacitor has a resistance similar to the polycrystalline silicon film that forms the other electrodes or wiring. The impurity concentration was set to be high in order to reduce it as much as possible.

[Problem to be solved by the invention]

In conventional MIS type semiconductor devices having such poly-Si electrodes or interconnections, the above-mentioned impurities in the gate insulating film, such as gate Sin, in the gate electrode cause fluctuations in the dark value and deterioration of the gate breakdown voltage.

Diffusion into the substrate through the film or the gate SiO□ film is considered.

Even though it is difficult for impurities to diffuse into the 5iOz film, it is an unavoidable fact that they will diffuse to some extent into the 5iOz film due to heat treatment after forming the gate electrode.

This diffused impurity diffuses into the gate 5iOz film with a concentration distribution that decreases exponentially, as shown in the impurity concentration profile in Figure 5, and this diffusion region depends on the temperature, time, atmosphere, etc. of the heat treatment, and has a unique Although it is not determined exactly, it exists with a finite value in any case.

In Fig. 5, the vertical axis 1ogC is the impurity concentration expressed in logarithms, the horizontal axis t is the depth, poly-Si is inside the poly-Si gate electrode, SiO□ is the gate Sin, inside the film, and S is the poly-Si gate electrode and gate). Interface with SiO□ film, Ct, Cz
indicates the concentration distribution of impurities.

For example, if the depth of the diffusion region is about 20, the thickness of the conventionally used 5 iOz film, which is about 200 to 300, is less than 10% of that and does not have a negative effect on the kneading properties. However, as device miniaturization progresses and the gate SiO2 film thickness is reduced to about 50%, the diffusion method described above accounts for a high proportion of about 40% of the gate Si0g film thickness, and the This has a serious effect on transistor characteristics, such as fluctuations in value voltage and reduction in gate breakdown voltage.

On the other hand, in the semiconductor device, as the degree of integration increases, the length of the wiring becomes longer and the width of the wiring becomes smaller, increasing the wiring resistance and causing a problem of operation delay.

Therefore, when poly-Si is used for electrodes and wiring, such as gate electrodes, the wiring resistance can be reduced by increasing its impurity concentration, but in this case, the entire poly-Si electrode wiring including the gate electrode is uniformly impurity In the conventional MIS type semiconductor device, which is formed with a high concentration, the gate 5 is formed by diffusion of impurities from the poly-Si layer.
It is conceivable that as the depth of the impurity diffusion region formed in the iOz film increases, further fluctuations and deterioration of the characteristics will inevitably occur. Furthermore, according to experiments conducted by the present inventors, in a stacked dynamic memory cell in which the opposing electrode of the memory cell capacitor is made of poly-Si, as the insulating film for forming the capacitor is made thinner for miniaturization, the gap between the electrodes becomes smaller. It was confirmed that the incidence of defects such as short circuits increased.

Therefore, the present invention aims to achieve high integration of a MIS type semiconductor device having a thin insulating film under a poly-Si electrode/wiring.
The purpose is to prevent the occurrence of defects such as fluctuations in dark values and deterioration of gate breakdown voltage.

[Means to solve the problem]

The above problem has an insulating film having a plurality of thicknesses, an electrode or wiring of a polycrystalline silicon film extending on the insulating film, and an insulating film having at least the minimum thickness among the insulating films. A semiconductor device characterized in that a polycrystalline silicon film in a contacting part contains a lower concentration of impurities than the polycrystalline silicon film in other parts, and a dielectric film and a counter electrode are laminated on a storage electrode. comprising a dynamic memory cell having a memory cell capacity;
The problem is solved by a semiconductor device characterized in that the counter electrode is made of a polycrystalline silicon film, and its impurity concentration is lower than the impurity concentration of the polycrystalline silicon film constituting other electrodes or wiring.

[For production]

That is, the present invention has found that when devices are miniaturized, the relationship between the impurity concentration in poly-Si and the thickness of the underlying insulating film has a large effect on the failure rate of the device. In areas that are disposed on an extremely thin insulating film where device characteristics may deteriorate due to the diffusion of impurities from electrodes or wiring, and which function as, for example, gate electrodes, the concentration of introduced impurities is reduced and the impurity-containing insulating film is The depth of the inward diffusion is made shallow to prevent fluctuations and deterioration of element characteristics due to deterioration of the thin insulating film, and the wiring is extended over a thick insulating film so that performance deterioration due to impurity diffusion does not appear noticeably. Impurities are introduced at a high concentration into the portions that function as a wire to lower the resistance, thereby reducing the wiring resistance. Furthermore, in the static capacitor of the dynamic memory cell, the impurity concentration in the poly-Si, which constitutes the counter electrode in contact with the extremely thin insulating film, is lower than the impurity concentration in the poly-Si in other wiring parts. Reduces the mechanical stress applied and lowers the failure rate of memory cell capacity.

In this way, a highly reliable and highly integrated MIS type semiconductor device having stable transistor characteristics and high operating speed is formed.

〔Example〕

The present invention will be specifically explained below with reference to illustrated embodiments.

FIG. 1 is a schematic plan view (a) and a schematic cross-sectional view taken along the line A-A of the first embodiment of the present invention (b), and FIGS. A process sectional view showing an example of the forming method, FIG. 3 is a schematic plan view (a) and A of the second embodiment of the present invention.
-A schematic cross-sectional view (g)) and FIGS. 4(a) to (C) are process cross-sectional views showing an example of the forming method of the second embodiment.

Identical objects are indicated by the same reference numerals throughout the figures.

A first embodiment shown in FIG.
This is an example in which i-electrode wiring is made separately from one layer of poly 5iJi.

In FIG. 1, ■ is a p-type Si substrate, 2 is a field SiO□ film, 3 is a p-type channel stopper, 4A and 4B are first and second transistor (Tr) formation regions, and 5 is a silicon dioxide film. , 6 is a contact window, 7 is a poly-S in the same layer.
The i pattern, 7A+, 7A2 is an n-type gate electrode portion with a low impurity (phosphorus or arsenic) concentration and has a high sheet resistance of, for example, about 600 Ω/R formed from the poly-Si pattern 7, and 7B, 7B+, 78z, 7B3 are The n-type wire portions 8A, 8B, 8C18D of high impurity (phosphorus or arsenic) concentration and having a low sheet resistance of, for example, about 25 Ω/hole and made of the poly-Si pattern 7 are first, second, third,
Fourth n2 type source/drain (S/D)? The fI region is shown.

In the MIS type semiconductor device shown in this example,
Consisting of a poly-Si layer with a low impurity concentration, the gate Si
Gate electrode portion where diffusion of impurities into the O□ film 5 is restricted? AI, 7^2, etc., and wiring portions 7B, 7B, 78z, 7B, etc. having high impurity concentration and low resistance are separately formed in an integrated poly-Si electrode wiring.

The structure of this embodiment is easily formed by the manufacturing method described below by way of example with reference to FIGS. 2(a)-(d) and FIG.

Refer to FIG. 2(a). First, the first and second transistor formation regions 4A and 4B are exposed by a conventional method, and a field SiO□ film 2 having a p-type channel stopper 3 at the bottom is formed on the p-type St substrate 1. Then, first and second transistor formation regions 4 are formed.
A thickness of about 50 layers is formed by thermal oxidation on A and 4B)
A SiO□ film 5 is formed.

Referring to FIG. 2, the gate Sin and film 5 on regions 9A, 9B, etc. where S/D contact is to be made are selectively removed by ordinary photolithography to form a contact window 6, and then the contact window 6 is formed.
A layer of 0-poly Si with a thickness of about 5000 is deposited on the substrate using the VD method.
A layer 107 is formed, and phosphorus (P), for example, is introduced at a low concentration onto the entire surface of the poly-Si layer 107 by a normal gas diffusion means, and the poly-Si layer 107 has a P concentration of about 10''cln-'.
The sheet resistance is controlled to be n-type with a sheet resistance of about 600Ω/R.

Refer to FIG. 2(C). Then, by thermal oxidation or the like, a thickness of 5 mm is formed on the poly-Si layer 107.
A SiO□ film 10 for a mask of about 0000 is formed, and then patterned by ordinary photolithography to form a continuous n film having a SiO□ film 10 for a mask on top.
- type poly-Si pattern 37 is formed.

Referring to FIG. 2(d), the masking 5iOz film 10 is then patterned by ordinary photolithography, and the n-type polyS
On the four-layer pattern 37, 5i (h mask patterns 10^, 10B, etc.) covering the gate electrode parts 7A, 7, etc. are formed, and then this SiO□ mask pattern IOA, 10
Using B as a mask, the SiO of the n-type wavy Si pattern 37 and the mask pattern 10A are removed by a normal gas diffusion method.
, arsenic (ΔS) or phosphorus (P) is selectively introduced at a high concentration into the portions that function as wiring that are not covered by IOBs, etc., and the exposed areas of the substrate surface, to form a coating of approximately 10'9 to 10''°. n-type wiring forming portions 7B+, 78z, 7B3, etc., which have a high P concentration of
and first, second, and third n-type S/D jI areas 8A, 8
B, 80 etc. are formed. Here, wiring forming portions 7n, 7B
The first, second, third, and fourth type S/s are deposited on the lower substrate surface of z, 7Bz, etc. by solid phase diffusion from the wiring forming portion.
An n° type region integral with D regions 8A, 8B, 8C, 80, etc. is formed.

Referring to FIG. 1, the above-mentioned polyS
Cut the i-pattern 37 into a desired shape and apply one layer of polyS.
N-type gate electrode portion 7 with low impurity concentration in i-electrode wiring 7
A MIS type semiconductor device according to the present invention is formed which includes a poly-Si electrode wiring having n-type wire portions 7B+, 78z, 7Bs, etc. having a high impurity concentration such as A+, 7Az, etc. and low resistance.

In addition, the second embodiment uses two poly-Si electrode wirings according to the present invention.
This is an example formed using a poly-Si layer.

In this case, as shown in FIG. 3, the n-type poly-Si gate electrodes 11A and IIB, which correspond to the gate electrode parts 7A+ and 7A2 of the first embodiment,
A), and the wiring portions 7B and 7B+ of the first embodiment
, 71h, n0 type poly-Si wiring 1 corresponding to 7B3, etc.
4.14A, 14B, 14C, etc. are formed by the second (upper layer) poly-Si layer (PB), and for example, as shown in the n-type poly-Si gate electrode 11A, both ends of the n-type poly-Si gate electrode N゛゛Poly Si wiring 14A
, 14B, etc. are the contact windows 13 of the insulating film, for example, the 5i02 insulating film 12, formed on the surface of the gate electrode 11A.
A, 13B, etc. are connected to each other, and the other end of the polySt wiring 14B is formed in the region 4B.
OS) One n-type S/D region 8A of the transistor is
SiO□ insulation film 12 formed on the top surface of the S/DmJt region
are connected through the contact window 13C to form a poly-Si electrode wiring according to the present invention.

Refer to FIG. 4(a) When forming this structure, as in the previous embodiment, the first and second transistor formation regions 4A and 4B separated and defined by the field 5in2 film 2 and the p-type channel stopper 3 are formed. After forming a SiO□ film 5 with a thickness of about 50 nm by thermal oxidation, a first polyS layer is formed on the substrate.
Form an i-layer (PA), then form the first poly-Si layer (P
After introducing *(P) into A) at a low concentration similar to the above example, the poly-Si layer (PA) is formed into a resist pattern 15A,
N- made of PA by patterning 15B etc. as a mask
Poly-Si gate electrodes 11A, IIB, etc. are formed, and then, using the resist patterns 15A, 15B, etc. as masks, the transistor formation region 4A is formed through the gate Sin and the film 5.
, Arsenic (As”) is ion-implanted at a high concentration into 4B etc.,
High concentration As” large injection region 108A, 1 which becomes S/D region
08B, (108C), etc. are formed.

Referring to FIG. 4(b), after removing the resist patterns 15A, 15B, etc. and the exposed SiO□ film 5, the surfaces of the gate electrodes 11A, IIB, etc. and the transistor forming regions 4A, 4B, etc. are removed by thermal oxidation or the like. The thickness of the substrate surface exposed to 10
00000 Si02 insulating film 12 is formed, and then the S
The gate electrodes 11A and IIB are formed on the i0g insulating film 12.
etc. and contact windows 13A, 13 for S/D regions.
B, 13C, 113D, etc., and then a second poly-Si (PB) layer 214 with a thickness of about 5000 mm is formed on the substrate.
and then the second poly-Si (PB) layer 214
Phosphorus (Po) is ion-implanted at a high concentration.

16 indicates a Po high concentration implantation region.

Referring to FIG. 4(C), a heat treatment is then performed to activate and redistribute the highly implanted Po to form an n+ type second layer with low sheet resistance.
At the same time as the poly-Si layer (PB) 114 is formed, the heavily implanted ^S' is activated and redistributed to form n' type S/D regions 8A, 8B, (8C), etc.

Refer to FIG. 3. Next, the above n' is formed by ordinary photolithography means.
An n4 type poly-Si wiring 14A is connected to one end of the gate electrode 11A through a contact window 13^ by patterning the second poly-Si type 5i (PB) layer 114.

Gate electrode 11 via contact windows 13B and 13C
n1 type poly-Si wiring 14B connecting the other end of A and the second S/D '1iJt area 8B, and n' type poly St wiring 14C connecting to the first S/D area 8A via the contact window 130. etc., thereby completing the MIS type semiconductor device according to the second embodiment.

Note that this structure seems to require a complicated process because it uses two layers of poly-5III PA and PB, but poly-SiN stacked structures are often used in semiconductor memories, etc., which are the main application of MIS type semiconductor devices. , if these steps are used together, the process will not be particularly complicated.

As shown in the embodiments above, according to the present invention, the poly-Si electrode wiring disposed in a semiconductor device is exposed to extreme conditions where element characteristics are deteriorated due to diffusion of impurities from the electrode wiring such as the gate insulating film. A portion disposed on a thin insulating film that functions as, for example, a gate electrode has a low impurity concentration to suppress the depth of impurity diffusion into the insulating film, thereby reducing device characteristics due to alteration of the thin insulating film. fluctuation deterioration is prevented,
In addition, the portions that extend over thick insulating films such as field sin and film where performance deterioration due to impurity diffusion does not appear significantly and function as interconnects are made to have a high impurity concentration and are made to have low resistance, thereby reducing the interconnect resistance. This will be reduced.

In this way, a highly integrated MIS type semiconductor device having stable transistor characteristics and high operating speed is formed.

Note that the present invention is of course applied to a poly-Si layer used as a lower layer of an electrode wiring having a polycide structure in which a metal silicide layer is laminated on a poly-Si layer to reduce resistance.

Furthermore, the present invention has extremely significant effects on dynamic memory cells that employ stacks and capacitors.
Its reliability can be greatly improved.

FIG. 6 is a cross-sectional view showing the structure of a dynamic memory cell. In the figure, 20 is a p-type semiconductor substrate, 21 is a diffusion region of a transfer gate, 22 is a field insulating film, 23 is a gate electrode of a transfer gate, 24 is a word line, 2
5 is an insulating film such as 5i (h), 26 is a storage electrode of a stacked capacitor, and 27 is a dielectric film of a stacked capacitor (
28 is an insulating film such as Sin2 (which has the smallest film thickness in the device) and a counter electrode (poly-Si film) of the stacked capacitor. Although not shown, the poly-Si film is also used to form transistors, wiring, and fuses in peripheral circuits, and multiple layers of poly-Si may be used in some cases.

The electrodes of such stacked capacitors have many steps,
A short circuit may occur between the storage electrode 26 and the counter electrode 28 due to local mechanical stress applied to the dielectric film 27. The inventors believe that the cause of this is not only the shape and step difference of the storage electrode 26, but also the thickness of the dielectric film 27 and the impurity concentration in the poly-Si film that constitutes the counter electrode 28, which have a large influence on the occurrence of defects. I found out what to do. FIG. 7 is a diagram showing the relationship between the dielectric film thickness and the non-defective rate of memory cells when the impurity concentration in the poly-Si constituting the counter electrode 28 is changed. In the figure, the vertical axis shows the non-defective product rate, and the horizontal axis shows the dielectric film thickness constituting the stacked capacitor. d). Figure 8 is a diagram showing the relationship between the impurity concentration in the poly-Si film 8 constituting the counter electrode 28 and the non-defective rate of memory cells (the thickness of the dielectric film 27 is approximately 60%). ).In the figure,
The vertical axis shows the non-defective product rate, and the horizontal axis shows the impurity concentration. As can be seen from FIG. 7, when the thickness of the dielectric film 27 is approximately 200 Å or more, the impurity concentration in the poly-Si is set to 1022/c4 or more, such as phosphorus or arsenic, as in the case of normal poly-Si wiring. Even so, it has almost no effect on the yield rate of stacked capacitors. However, when the film thickness of the dielectric film 27 is set to 200 Å or less, for example, about 130 Å or less, the influence of impurity concentration begins to appear, and when it becomes about 60 Å or less, the effect becomes even more pronounced, and the impurity concentration becomes about the same as that of ordinary poly-Si wiring. In this case, the rate of non-defective products will drop significantly. This is because the higher the impurity concentration in poly-Si, the higher the dielectric film 2 under the dalein in poly-Si.
This is thought to be due to the increase in local stress applied to 7.

Therefore, when the dielectric film 27 is made to have a thickness of 200 Å or less, especially 100 Å or less, the impurity concentration in the counter electrode 28 may be reduced in other parts (poly-Si wiring, poly-Si electrodes, etc. on an insulating film thicker than the dielectric film 27). ), for example, 1
0" to 1021/CT11. In this way, as shown in FIG. 8, the yield rate of stacked capacitors is greatly improved. In this case, the impurity concentration in the counter electrode 28 is 102
It has been confirmed that a remarkable effect can be obtained when the ratio is set to 0 to 10"/cra. In addition, in order to alleviate the mechanical stress on the dielectric film 27, rounding the shape of the corners of the storage electrode 26 may be considered. However, this requires special processing and is not practical.

On the other hand, since the present invention only requires adjustment of the impurity concentration, it can be easily implemented and has great effects.

The present invention can also be implemented in a dynamic memory cell having a stacked capacitor as shown in FIG. 9th
The figure is a cross-sectional view of a dynamic memory cell. In the diagram, 3
0 is a p-type semiconductor substrate, 31 and 32 are source/drain diffusion regions, 33.34 is an insulating film, 35 is a bit line, 36
37 is a storage electrode, 37 is a field insulating film, 38 is a counter electrode (poly-Si), and 39 is a dielectric film (Sin, Si3N).
4, etc.), WLl is a gate electrode (word line), and WL2 is a word line. In such a dynamic memory cell, since the storage electrode has irregularities, the capacitance value per unit of 1,000 area can be increased, but the mechanical stress applied to the dielectric film 39 also increases, and the impurity concentration in the poly-Si film is lowered than usual. If the wiring is the same as in the above, defects are likely to occur. Therefore, in this embodiment, the bit line 35 on the insulating film 34 of about 1000 people
The impurity (arsenic) concentration in (polySt) is set to 10"/c+f1 or more, for example 10"/c++t, to lower the resistance, and the gate electrode (po'JS) on the gate insulating film of about 150 people is
i) The impurity (phosphorus) concentration in the dielectric film 36 (poly-Si) of approximately 60 people is set to 1020 to 10" ctJ, and the impurity (phosphorus) concentration in the dielectric film 36 (poly-Si)
The phosphorus concentration was set to 1OI9-10"/c++t. By making the impurity concentration in the poly-Si, which is in contact with the thinnest insulating film, relatively lower than in other parts, the stacked capacitor shown in FIG. It has also become possible to manufacture with high yield.

〔Effect of the invention〕

As explained above, according to the present invention, the gate insulating film is formed extremely thin, and the gate electrode is made of poly-Si.
The transistor characteristics of the S-type semiconductor device can be stabilized, and the resistance of the poly-Si electrode wiring can be reduced. In addition, a stacked capacitor in which a polySt counter electrode is laminated on an extremely thin dielectric film can also be formed with a high yield.

Therefore, the present invention is extremely effective in improving the manufacturing yield and increasing the speed of MIS semiconductor devices that are highly integrated such as LSIs.

[Brief explanation of the drawing]

Fig. 1 is a schematic plan view (a) and a schematic cross-sectional view taken along the line A-A of the first embodiment of the present invention, and Fig. 2 (a) to (d) are the same first embodiment. 3 is a schematic plan view (a) and a schematic sectional view taken along the line A-A (b) of the second embodiment of the present invention; FIG. 4 (a) - (d) is a process sectional view showing an example of the manufacturing method of the second embodiment, and FIG. 5 is an impurity concentration profile diagram. FIG. 6 is a cross-sectional view showing the structure of a dynamic memory cell, and FIG. 7 shows the relationship between the dielectric film thickness and the non-defective yield rate of memory cells when the impurity concentration in the polySt constituting the counter electrode 28 is changed. 8 is a diagram showing the relationship between the impurity concentration in the polySt film 28 constituting the counter electrode 28 and the non-defective rate of memory cells, and FIG. 9 is a sectional view showing the structure of the dynamic memory cell. In the figure, 1 is a p-type Si substrate, 2 is a field and doped SiO□ film, 3 is a p-type channel stopper, 4A and 4B are transistor formation regions, 5 is a gate SiO□ film, 6 is a contact window, and 7 is a polyamide Si electrode wiring, 7^1.7^2 is the gate electrode part, 7B, 7B+, 78z, 7B+ is the wiring part, 8A
, 8B, 8C, and 8D, the n1 type S/D region 20 is the p-type semiconductor substrate, 21 is the diffusion region of the transfer gate, 22 is the field insulating film, 23 is the gate electrode of the transfer gate, 24 is the word line, and 25 is the SIN , etc., 26 is a storage electrode of a stacked capacitor, 27 is a dielectric film of a stacked capacitor, 30 is a p-type semiconductor substrate, 31 and 32 are source/drain diffusion regions, 33.34
35 is an insulating film, 35 is a bit line, 36 is a storage electrode, 37 is a field insulating film, 38 is a counter electrode (poly-Si), 39 is a dielectric film (Si02, Si3N4, etc.), WLI
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Claims (2)

[Claims] (1) It has an insulating film having a plurality of thicknesses, and an electrode or wiring of a polycrystalline silicon film extending over the insulating film, and is in contact with an insulating film having at least the minimum thickness among the insulating films. A semiconductor device characterized in that a portion of the polycrystalline silicon film contains impurities at a lower concentration than that of the other portion of the polycrystalline silicon film. (2) A dynamic memory cell having a memory cell capacity in which a dielectric film and a counter electrode are stacked on a storage electrode, the counter electrode is made of a polycrystalline silicon film, and its impurity concentration is higher than that of other electrodes or wiring. 1. A semiconductor device characterized in that the impurity concentration is lower than that of a polycrystalline silicon film constituting the semiconductor device.