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JPH02114639A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JPH02114639A
JPH02114639A JP26852288A JP26852288A JPH02114639A JP H02114639 A JPH02114639 A JP H02114639A JP 26852288 A JP26852288 A JP 26852288A JP 26852288 A JP26852288 A JP 26852288A JP H02114639 A JPH02114639 A JP H02114639A
Authority
JP
Japan
Prior art keywords
film
semiconductor device
trench
electrode
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP26852288A
Other languages
Japanese (ja)
Other versions
JP2808616B2 (en
Inventor
Seiichi Iwamatsu
誠一 岩松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP63268522A priority Critical patent/JP2808616B2/en
Publication of JPH02114639A publication Critical patent/JPH02114639A/en
Application granted granted Critical
Publication of JP2808616B2 publication Critical patent/JP2808616B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野] 本発明は半導体における電極配線構造に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to an electrode wiring structure in a semiconductor.

〔従来の技術1 従来、半導体装置における電極配線は、半導体基板表面
に形成された絶縁膜表面に、スパッタ法等の蒸着法で形
成されたAl1膜をホト・エツチングして、電極配線と
なし、その上にCVD5 iO2膜等の保護膜を形成し
て成るのが通例であった。
[Conventional technology 1] Conventionally, electrode wiring in a semiconductor device is formed by photo-etching an Al1 film formed by a vapor deposition method such as a sputtering method on the surface of an insulating film formed on the surface of a semiconductor substrate. It was customary to form a protective film such as a CVD5 iO2 film thereon.

[発明が解決しようとする課題1 しかし、上記従来技術によると、AI2電極配線が保護
膜等から受けるストレスによりマイグレーションし、い
わゆるストレス・マイグレーションによる断線が発生し
たり、又、エレクトロ・マイグレーションによる断線も
発生し易くなると云う課題があった。
[Problem to be Solved by the Invention 1] However, according to the above-mentioned prior art, the AI2 electrode wiring migrates due to the stress received from the protective film, etc., and disconnection occurs due to so-called stress migration, and disconnection due to electromigration also occurs. There was a problem in that it was more likely to occur.

本発明はかかる従来技術の課題を解決するために半導体
装置における電極配線の新しい構造を提供する事を目的
とする。
An object of the present invention is to provide a new structure of electrode wiring in a semiconductor device in order to solve the problems of the prior art.

[課題を解決するための手段1 上記課題を解決するために、本発明は、半導体装置に関
し、 (1)半導体基板表面に形成された絶縁膜にはトレンチ
を形成し、該トレンチ内に電極を埋め込む手段をとる事
を基本とし、 (2)前記電極の材料をT i W、 T i pJ、
 TiS i、WS i、MoS i又はTi膜とCu
又はAβ膜との多層構造となす手段をとる事、及び(3
)前記絶縁膜の少なくとも電極側壁に接する膜は、有機
膜となす手段をとる事、 等である。
[Means for Solving the Problems 1] In order to solve the above problems, the present invention relates to a semiconductor device, and provides the following features: (1) A trench is formed in an insulating film formed on the surface of a semiconductor substrate, and an electrode is placed in the trench. (2) The material of the electrode is T i W, T i pJ,
TiS i, WS i, MoS i or Ti film and Cu
Or, taking measures to form a multilayer structure with Aβ film, and (3)
) At least the film in contact with the side wall of the electrode of the insulating film is an organic film.

[実 施 例〕 第1図は、本発明の一実施例を示す半導体装置の電極配
線構造の断面図である。すなわち、Si基板lの表面に
はS l 02膜2が形成され、該SiO□膜2にホト
・エツチングによりトレンチ3を形成した表面から、ス
パッタ法により、Cu膜を形成し、エッチ・バック法に
よりトレンチ3部以外のCu膜を除去して、トレンチ3
部内にCu配線4を形成したものである。尚Cu配線4
はAI2であっても良く、5iO−tl!2はポリイミ
ド膜等の有機膜であっても良(、Stow膜とS i 
s N4 IIの2層構造にて、SiSi3N4内にト
レンチ3を形成する等の構造をとる事も出来る。
[Embodiment] FIG. 1 is a sectional view of an electrode wiring structure of a semiconductor device showing an embodiment of the present invention. That is, an S l 02 film 2 is formed on the surface of the Si substrate 1, and a Cu film is formed on the surface of the SiO □ film 2 on which a trench 3 is formed by photo-etching, using a sputtering method, and an etch-back method. The Cu film in areas other than trench 3 is removed by
A Cu wiring 4 is formed inside the portion. Furthermore, Cu wiring 4
may be AI2, and 5iO-tl! 2 may be an organic film such as a polyimide film (Stow film and Si
It is also possible to adopt a structure in which a trench 3 is formed in SiSi3N4 in a two-layer structure of sN4II.

第2図は、本発明の他の実施例を示す半導体装置の要部
の断面図である。すなわち、Si基板11の表面には5
iOa膜12が形成され、次でスパッタ法や、CVD法
等によりTiWli13を形成後、パターン状にホト・
エツチングし、その後、ホトレジストI114を形成し
、該レジスト膜14の露光現象処理により、トレンチ1
5をTiWli13上に形成し、メツキ法やスパッタ膜
のエッチ・バック法等により、Cu膜をトレンチ15内
に埋め込んでCu1i:線16を形成したものである。
FIG. 2 is a sectional view of a main part of a semiconductor device showing another embodiment of the present invention. That is, on the surface of the Si substrate 11, there are 5
After the iOa film 12 is formed, TiWli 13 is formed by sputtering, CVD, etc., and then photolithography is performed in a pattern.
After that, a photoresist I114 is formed, and the trench 1 is etched by an exposure process of the resist film 14.
5 is formed on the TiWli 13, and a Cu film is buried in the trench 15 by a plating method, a sputtered film etch-back method, or the like to form a Cu1i: line 16.

尚TiWli13はTiN、TiSi、WSi、MoS
i又はTi膜であっても良<、 Cu配線16はAβで
あっても良く、ホトレジスト膜14はSiO□膜やSi
3N+膜あるいはポリイミド膜等の他の有機膜をホトリ
ソグラフィーや、ホト・エツチングで形成したものであ
っても良い。
Note that TiWli13 is TiN, TiSi, WSi, MoS
The Cu wiring 16 may be made of Aβ, and the photoresist film 14 may be made of a SiO□ film or a Si film.
It may also be a 3N+ film or another organic film such as a polyimide film formed by photolithography or photo-etching.

第3図は本発明のその他の実施例を示す半導体装置の要
部の断面図である。すなわち、Si基板21の表面には
SiO□膜が形成され、該SiO□膜22にはホト・エ
ツチングによりトレンチ23が形成され、次いでスパッ
ク法等によりTi膜膜とCu1llを形成後、エッチ・
バック法により、トレンチ13内にTiW膜24とCu
0c!It!25から成る電極配線を形成したものであ
る。
FIG. 3 is a sectional view of a main part of a semiconductor device showing another embodiment of the present invention. That is, a SiO□ film is formed on the surface of the Si substrate 21, a trench 23 is formed in the SiO□ film 22 by photo-etching, a Ti film and a Cu1ll are formed by a spuck method, and then etched.
A TiW film 24 and a Cu film are formed in the trench 13 by the back method.
0c! It! 25 electrode wirings are formed.

[発明の効果] 本発明により、半導体装置の電極配線が少なくとも側面
の絶縁膜から来るストレスを緩和でき。
[Effects of the Invention] According to the present invention, the stress caused by the insulating film on at least the side surface of the electrode wiring of a semiconductor device can be alleviated.

ストレス・マイグレーションによる断線を防止出来、ひ
いてはエレクトロ・マイグレーションによる断線も防止
出来る効果がある。
This has the effect of preventing wire breakage due to stress migration and, by extension, preventing wire breakage due to electromigration.

l 、 2. 3. 4゜ l 3. 14 ・ l 1 、2 l ・ l 2、22 ・ l 5、 l 3 ・ l 6、25 ・ 24 ・ ・ ・ ・ Si基板 5iOi膜 トレンチ Cu配線 Ti膜膜 ホトレジスト膜 以上 出願人 セイコーエプソン株式会社 代理人 弁理士 上 柳 雅 誉(他1名)l, 2. 3. 4゜ l 3. 14・ l 1  、2 l ・ l 2,22 ・ l 5  l 3 ・ l 6,25 ・ 24 ・ ・ ・ ・ Si substrate 5iOi film trench Cu wiring Ti film photoresist film that's all Applicant: Seiko Epson Corporation Agent: Patent attorney Homare Kamiyanagi (1 other person)

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図、及び第3図は、本発明の半導体装置に
おける配線構造を示す断面図である。
FIG. 1, FIG. 2, and FIG. 3 are cross-sectional views showing the wiring structure in the semiconductor device of the present invention.

Claims (3)

【特許請求の範囲】[Claims] (1)半導体基板表面に形成された絶縁膜にはトレンチ
(溝)が形成され、該トレンチ内には電極が埋め込まれ
て配線されて成る事を特徴とする半導体装置。
(1) A semiconductor device characterized in that a trench is formed in an insulating film formed on the surface of a semiconductor substrate, and an electrode is embedded and wired in the trench.
(2)電極材料をTiW、TiN、TiSi、WSi、
MoSi又はTi膜とCu又はAl膜との多層構造とな
す事を特徴とする請求項1記載の半導体装置。
(2) The electrode material is TiW, TiN, TiSi, WSi,
2. The semiconductor device according to claim 1, wherein the semiconductor device has a multilayer structure of a MoSi or Ti film and a Cu or Al film.
(3)絶縁膜の少なくとも電極側壁に接する膜は、有機
膜となす事を特徴とする請求項1記載の半導体装置。
(3) The semiconductor device according to claim 1, wherein at least the film in contact with the electrode side wall of the insulating film is an organic film.
JP63268522A 1988-10-25 1988-10-25 Method for manufacturing semiconductor device Expired - Fee Related JP2808616B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63268522A JP2808616B2 (en) 1988-10-25 1988-10-25 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63268522A JP2808616B2 (en) 1988-10-25 1988-10-25 Method for manufacturing semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP11107298A Division JPH10270448A (en) 1998-04-21 1998-04-21 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH02114639A true JPH02114639A (en) 1990-04-26
JP2808616B2 JP2808616B2 (en) 1998-10-08

Family

ID=17459691

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63268522A Expired - Fee Related JP2808616B2 (en) 1988-10-25 1988-10-25 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2808616B2 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0523791A2 (en) * 1991-07-16 1993-01-20 Koninklijke Philips Electronics N.V. Method of providing a copper pattern on a dielectric substrate
JPH05102318A (en) * 1991-04-05 1993-04-23 Internatl Business Mach Corp <Ibm> Method and apparatus for forming conductive copper alloy plug
JPH06168943A (en) * 1991-02-01 1994-06-14 Internatl Business Mach Corp <Ibm> Treatment method of laser-cut wavy pattern
JPH07183299A (en) * 1993-12-22 1995-07-21 Nec Corp Method for forming copper wirings
JPH08236621A (en) * 1995-02-28 1996-09-13 Nec Corp Fabrication of semiconductor device
US6331811B2 (en) 1998-06-12 2001-12-18 Nec Corporation Thin-film resistor, wiring substrate, and method for manufacturing the same
US6482741B1 (en) * 1997-06-25 2002-11-19 Nec Corporation Copper wiring structure comprising a copper material buried in a hollow of an insulating film and a carbon layer between the hollow and the copper material in semiconductor device and method fabricating the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4944797A (en) * 1972-06-19 1974-04-27

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4944797A (en) * 1972-06-19 1974-04-27

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06168943A (en) * 1991-02-01 1994-06-14 Internatl Business Mach Corp <Ibm> Treatment method of laser-cut wavy pattern
JPH05102318A (en) * 1991-04-05 1993-04-23 Internatl Business Mach Corp <Ibm> Method and apparatus for forming conductive copper alloy plug
EP0523791A2 (en) * 1991-07-16 1993-01-20 Koninklijke Philips Electronics N.V. Method of providing a copper pattern on a dielectric substrate
EP0523791A3 (en) * 1991-07-16 1994-03-16 Philips Nv
JPH07183299A (en) * 1993-12-22 1995-07-21 Nec Corp Method for forming copper wirings
JPH08236621A (en) * 1995-02-28 1996-09-13 Nec Corp Fabrication of semiconductor device
US6482741B1 (en) * 1997-06-25 2002-11-19 Nec Corporation Copper wiring structure comprising a copper material buried in a hollow of an insulating film and a carbon layer between the hollow and the copper material in semiconductor device and method fabricating the same
US6486559B1 (en) 1997-06-25 2002-11-26 Nec Corporation Copper wiring structure comprising a copper material buried in a hollow of an insulating film and a carbon layer between the hollow and the copper material in semiconductor device and method of fabricating the same
US6331811B2 (en) 1998-06-12 2001-12-18 Nec Corporation Thin-film resistor, wiring substrate, and method for manufacturing the same

Also Published As

Publication number Publication date
JP2808616B2 (en) 1998-10-08

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