JPH02114520A - Diffusion mask for use in manufacture of semiconductor - Google Patents
Diffusion mask for use in manufacture of semiconductorInfo
- Publication number
- JPH02114520A JPH02114520A JP63267039A JP26703988A JPH02114520A JP H02114520 A JPH02114520 A JP H02114520A JP 63267039 A JP63267039 A JP 63267039A JP 26703988 A JP26703988 A JP 26703988A JP H02114520 A JPH02114520 A JP H02114520A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion
- compound semiconductor
- diffusion mask
- silicon
- silicon film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Junction Field-Effect Transistors (AREA)
- Led Devices (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、化合物半導体を用いた発光ダイオードあるい
は電界効果トランジスタなどの半導体装置の製造に使用
する拡散マスクに関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a diffusion mask used for manufacturing semiconductor devices such as light emitting diodes or field effect transistors using compound semiconductors.
(従来の技術)
化合物半導体への不純物拡散は、m lliなPN接合
の形成法としてだけでなく、抵抗性接触を良好にするた
めの高濃度化技術として、あるいは光半導体素子におい
ては部分的な高濃度化による電流狭窄法としても用いら
れ、さらに、エピタキシャル成長で形成したPN接合を
拡散により部分的に分離し、発光領域を制限するような
素子分離法としても広く利用されている。(Prior art) Impurity diffusion into compound semiconductors is used not only as a method for forming a 100% PN junction, but also as a high concentration technique to improve resistive contact, or as a partial method for optical semiconductor devices. It is also used as a current confinement method by increasing the concentration, and is also widely used as an element isolation method in which a PN junction formed by epitaxial growth is partially separated by diffusion to limit the light emitting region.
以下に、化合物半導体としてGaAGAsのエピタキシ
ャル成長層をとりあげ、予め形成したPNヘテロ接合を
分前する場合について、さらに詳し〈従来技術を説明す
る。In the following, a case where an epitaxially grown layer of GaAGAs is used as a compound semiconductor and a pre-formed PN heterojunction is used will be described in more detail (prior art).
第2図は、従来の拡散マスクの構造を示す。第2図にお
いて、1はP型GaAs基板、2はP型Ga□−xAQ
xAs(x =0.75)、3はP型Ga、−xAGx
As(x=0.:15)、4はN型Ga、−xAllx
As(x = 0.75)である。FIG. 2 shows the structure of a conventional diffusion mask. In Fig. 2, 1 is a P-type GaAs substrate, 2 is a P-type Ga□-xAQ
xAs (x = 0.75), 3 is P-type Ga, -xAGx
As (x=0.:15), 4 is N-type Ga, -xAllx
As (x = 0.75).
6は絶縁膜で、化学的気相成長法(以降、CVD法と記
す)により形成したものであり、代表的には酸化珪素膜
あるいは窒化珪素膜が使用される。Reference numeral 6 denotes an insulating film, which is formed by a chemical vapor deposition method (hereinafter referred to as CVD method), and typically a silicon oxide film or a silicon nitride film is used.
これが従来の拡散マスクである。この拡散マスクを用い
て選択的に不純物をP型Ga、−、A(1,As(x
=0.75) 2まで拡散し、N型領域4の一部をP型
拡散領域7に変える。このようにして作成された発光ダ
イオードでは、N型領域4とP型拡IF1.領域7で構
成されるPN接合のエネルギー帯障壁が高いために、拡
散を行なわないN型領域4とP型Ga、−、AU、As
(x =0.35) 3で構成されるPN接合部に電流
が集中する。これにより1発光領域を拡散を行なわない
領域に制限した発光ダイオードが作成できる。This is a conventional diffusion mask. Using this diffusion mask, selectively impurities are added to P-type Ga, -, A(1, As(x
= 0.75) to change a part of the N-type region 4 into a P-type diffusion region 7. In the light emitting diode thus created, the N-type region 4 and the P-type expanded IF 1. Since the energy band barrier of the PN junction composed of the region 7 is high, the N-type region 4 which does not undergo diffusion and the P-type Ga, -, AU, As
(x = 0.35) Current concentrates at the PN junction composed of 3. This makes it possible to create a light emitting diode in which one light emitting region is limited to a region in which no diffusion is performed.
上記の方法では、平坦な表面上に発光部を複数個備えた
集積化発光半導体装置が実現でき、発光半導体′!AI
Wの応用分野を広げるものとして需要が高まってきてい
る。今後さらに発光領域間の間隔を狭くシ、集積度を増
すことが強く要求されるようになった。With the above method, an integrated light emitting semiconductor device having a plurality of light emitting parts on a flat surface can be realized, and a light emitting semiconductor'! AI
Demand is increasing as a means of expanding the application fields of W. In the future, there will be a strong demand for further narrowing the spacing between light emitting regions and increasing the degree of integration.
(発明が解決しようとする課題)
しかしながら、上記の方法において、従来の拡散マスク
である酸化珪素膜や窒化珪素膜では、GaAsなどの化
合物半導体との界面に変成層、例えば酸化物層が発生し
、緻密な1漠の形成が薙しいために、垂直方向の拡散に
対して化合物半導体と拡散マスクとの界面方向への急速
な拡散が進むという問題があった。界面方向の拡散が大
きいと、複数の発光部間の分離を確実にするために分離
間隔を広くとらねばならず、これでは近年望まれている
半導体装置の微細化は困難である。(Problem to be Solved by the Invention) However, in the above method, in the silicon oxide film or silicon nitride film that is the conventional diffusion mask, a metamorphosed layer, such as an oxide layer, is generated at the interface with a compound semiconductor such as GaAs. However, since the formation of a dense area is slow, there is a problem in that the diffusion progresses rapidly toward the interface between the compound semiconductor and the diffusion mask compared to the diffusion in the vertical direction. If the diffusion in the interface direction is large, the separation interval must be widened to ensure separation between the plurality of light emitting parts, and this makes it difficult to miniaturize semiconductor devices, which has been desired in recent years.
本発明は、上記従来の問題を解決するもので。The present invention solves the above-mentioned conventional problems.
界面方向の拡散を抑え、同時に半導体装置の微細化を行
なうための製造に使用する拡散マスクを提供することを
目的とする。It is an object of the present invention to provide a diffusion mask used in manufacturing for suppressing diffusion in the interface direction and at the same time miniaturizing semiconductor devices.
(課題を解決するための手段)
上記目的を達成するために、本発明は、化合物半導体上
の拡散マスクを一層以上とし、少なくとも化合物半導体
側の一層の主元素をシリコンとするように構成する。(Means for Solving the Problems) In order to achieve the above object, the present invention is configured such that the diffusion mask on the compound semiconductor has one or more layers, and the main element of at least one layer on the compound semiconductor side is silicon.
(作 用)
シリコン膜は、形成時において化合物半導体界面に酸化
物などの変成層が発生しに<<、より緻密な膜となり、
また、シリコン膜とGaAs、InPのような化合物半
導体とは熱膨張係数や格子定数が近い値であるため、昇
降温時での熱的損傷を少なくできる。(Function) When a silicon film is formed, a metamorphic layer such as oxide is generated at the compound semiconductor interface, resulting in a more dense film.
Furthermore, since the silicon film and compound semiconductors such as GaAs and InP have similar thermal expansion coefficients and lattice constants, thermal damage can be reduced when the temperature is raised or lowered.
したがって1本発明のような拡散マスクを半導体装置の
gA造に使用すると、化合物半導体と拡散マスクとの界
面方向への拡散を抑えることができるようになるととも
に、半導体装置の微細化も可能となる。Therefore, when the diffusion mask of the present invention is used in the GA fabrication of semiconductor devices, it becomes possible to suppress the diffusion toward the interface between the compound semiconductor and the diffusion mask, and it also becomes possible to miniaturize the semiconductor device. .
(実施例)
以下に、前述のGa1−xAQxAsエピタキシャルウ
ェハを基体とし、拡散源として亜鉛を用いた本発明の一
実施例について、第1図を参照しながらさらに詳細に説
明する。第1図は本発明における拡散マスクの基本構成
図であり、拡散マスクの第1層にシリコン膜5を設けて
いる点で、従来のものと相違している。まず、液相エピ
タキシャル成長法により、P型GaAs基板1上にP型
Ga、xAllxAs(x=0.75)2. P型Ga
1−x1!、As(x =0.35) :3およびN型
Ga、−xAQxAs(x =0.75) 4をそれぞ
れの厚さが30μ■、 1prm、 l0JJ11とな
るように順次成長した後、N型[’;a1− XAII
XAS (x =O−75) 4上にシリコン膜5を形
成した。シリコン膜5の形成は、光照射を介在した化学
的気相成長法(光CVD法)により行ない。(Example) An example of the present invention in which the above-mentioned Ga1-xAQxAs epitaxial wafer is used as a substrate and zinc is used as a diffusion source will be described in more detail below with reference to FIG. FIG. 1 is a basic configuration diagram of a diffusion mask according to the present invention, which differs from the conventional one in that a silicon film 5 is provided in the first layer of the diffusion mask. First, P-type Ga, xAllxAs (x=0.75)2. P-type Ga
1-x1! , As (x = 0.35): 3 and N-type Ga, -xAQ ';a1-XAII
A silicon film 5 was formed on the XAS (x = O-75) 4. The silicon film 5 is formed by chemical vapor deposition using light irradiation (photo-CVD).
半導体基板温度330℃、圧力400Pa 、ジシラン
(Si、 If、 ) 2 cc /分、窒素(N、)
100oc/分の条件下で厚さを400人とした。本発
明の実施例では、光CVD法でのシリコン膜成長速度が
遅いために、シリコン膜5上にさらに酸化珪素膜6を通
常のCVD法で約4000人成長し、2層が形成された
拡散マスクとした。すなわち、本発明の実施例は、拡散
マスクを2層構造とし、第1層にシリコン膜、第2層に
酸化珪素膜を用いた例である。このようにして作製した
拡散マスクに、写真製版技術により拡散パターンを形成
し、二砒化亜釦を拡散源として温度800℃で1時間の
拡散を行ない、その場合の界面方向への拡散を従来の酸
化珪素膜のみを用いた場合と本発明の方法の場合とで比
較した。比較するにあたって、深さ方向の拡散をX□、
界面方向への拡散をS−X、と表わすことにする。N型
Ga、−xi工As4の厚さ10μIに対し、深さ方向
の拡散をX、==201Jm一定とした場合に、従来法
では5−XJ=15〜20μ調であるのに対し、本発明
ではS−x、=to〜13p@となり、界面方向への拡
散速度を約30%低減でき、パターン幅に換算すると約
20%の縮小が実現できた。Semiconductor substrate temperature: 330°C, pressure: 400 Pa, disilane (Si, If, ) 2 cc/min, nitrogen (N, )
The thickness was set to 400 people under the condition of 100oc/min. In the embodiment of the present invention, since the growth rate of silicon film by photo-CVD method is slow, about 4000 silicon oxide films 6 are further grown on silicon film 5 by normal CVD method, and two layers are formed. I used it as a mask. That is, in the embodiment of the present invention, the diffusion mask has a two-layer structure, and the first layer is a silicon film and the second layer is a silicon oxide film. A diffusion pattern was formed on the diffusion mask thus prepared by photolithography, and diffusion was performed at a temperature of 800°C for 1 hour using a diarsenic subbutton as a diffusion source. A comparison was made between a case using only a silicon oxide film and a case using the method of the present invention. For comparison, the diffusion in the depth direction is
Diffusion in the direction of the interface will be expressed as S−X. When the thickness of N-type Ga, -XI As4 is 10μI, and the diffusion in the depth direction is constant X = = 201Jm, in contrast to the conventional method, which is 5-XJ = 15 to 20μ. In the invention, S-x,=to~13p@, and the diffusion rate toward the interface could be reduced by about 30%, and when converted to pattern width, it was possible to achieve a reduction of about 20%.
実際にLEDプリンタ等に用いられる集積化発光素子の
場合には、発光パターンがその他の理由で既に決められ
ている場合も少なくなく、界面方向拡散の30%の減少
は、fR造歩留で表わすと著しい差となって表われ、本
発明の効果が顕著に確認できた。In the case of integrated light emitting devices actually used in LED printers, etc., the light emitting pattern is often already determined for other reasons, and a 30% reduction in interfacial direction diffusion is expressed in terms of fR manufacturing yield. The effect of the present invention was clearly confirmed.
(発明の効果)
本発明の光半導体装置の製造に使用する拡散マスクによ
れば、拡散マスク材料としてシリコン層を設けたので、
シリコン層を設けなかった従来の拡散マスクに比べかな
り界面方向の拡散を抑え。(Effects of the Invention) According to the diffusion mask used for manufacturing the optical semiconductor device of the present invention, since a silicon layer is provided as the diffusion mask material,
Compared to conventional diffusion masks that do not have a silicon layer, diffusion in the interface direction is significantly suppressed.
発光半導体装置の集積化を進めることができた。We were able to advance the integration of light-emitting semiconductor devices.
第1図はシリコン膜を拡散マスクとした本発明における
拡散マスクの基本構造図、第2図は従来の酸化珪素1摸
を拡散マスクとした拡散マスク構造図を示す。
1 ・P型GaAs基板、 2−P型Ga1−、AQ
xAs(x=0.75)、 3 ・P型Ga、 −x
AllxAs(x =0.35)、 4−N型Ga
1−xAQ、^s(x =0.75)。
5・・・シリコン膜、 6・・・酸化珪素膜、7・・・
P型拡散領域。
特許出願人 松下電器産業株式会社
第1
酸化5L禾月吏
シリコン朕
N −Gal −x Alx As
P−Got−xALxAs
P−Got−xALzAs
P−GaAs基ネ反
(X=0.75)
(X=0.353
(X=0.75)
図FIG. 1 shows a basic structure of a diffusion mask according to the present invention using a silicon film as a diffusion mask, and FIG. 2 shows a structure of a conventional diffusion mask using a piece of silicon oxide as a diffusion mask. 1 ・P-type GaAs substrate, 2-P-type Ga1-, AQ
xAs (x=0.75), 3 ・P-type Ga, -x
AllxAs (x = 0.35), 4-N type Ga
1-xAQ, ^s (x = 0.75). 5... Silicon film, 6... Silicon oxide film, 7...
P-type diffusion region. Patent Applicant: Matsushita Electric Industrial Co., Ltd. No. 1 Oxide 5L Silicone N -Gal -x Alx As P-Got-xALxAs P-Got-xALzAs P-GaAs base anti(X=0.75) (X= 0.353 (X=0.75) Figure
Claims (1)
において、一層以上からなり、少なくとも化合物半導体
側の一層の主元素がシリコンであることを特徴とする半
導体装置の製造に使用する拡散マスク。A diffusion mask for selectively diffusing impurities into a compound semiconductor, comprising one or more layers, and at least one layer on the compound semiconductor side having silicon as the main element, for use in manufacturing a semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63267039A JPH02114520A (en) | 1988-10-25 | 1988-10-25 | Diffusion mask for use in manufacture of semiconductor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63267039A JPH02114520A (en) | 1988-10-25 | 1988-10-25 | Diffusion mask for use in manufacture of semiconductor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02114520A true JPH02114520A (en) | 1990-04-26 |
Family
ID=17439196
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63267039A Pending JPH02114520A (en) | 1988-10-25 | 1988-10-25 | Diffusion mask for use in manufacture of semiconductor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02114520A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003080957A (en) * | 2001-09-11 | 2003-03-19 | Yanmar Agricult Equip Co Ltd | Combine |
JP2007055534A (en) * | 2005-08-26 | 2007-03-08 | Komatsu Ltd | Cooling device |
-
1988
- 1988-10-25 JP JP63267039A patent/JPH02114520A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003080957A (en) * | 2001-09-11 | 2003-03-19 | Yanmar Agricult Equip Co Ltd | Combine |
JP2007055534A (en) * | 2005-08-26 | 2007-03-08 | Komatsu Ltd | Cooling device |
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