JPH02113355A - Cache memory - Google Patents

Abstract

PURPOSE:To use the cache memory efficiently while securing the consistency of data with a main memory by performing address retrieval only with the in-page offset address field of a physical address and invalidating a matching entry. CONSTITUTION:When a 32-bit logical address is converted into a 32-bit physical address, the high-order bits, e.g. 20 bits of the logical address are converted to obtain 20 bits of a physical page on a main memory. Namely, the low-order bits (12 bits in this example) of the logical address mean an offset address in the physical page on the main memory and the field of this in-page offset address is the same address information in the logical address and physical address. For the purpose, the cache memory is retrieved only with the in-pase offset address field of the physical address to be invalidated to detect a relative entry. Consequently, the effective flag of the entry is reset to '0' to secure data on the cache memory.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a cache memory that is incorporated into a microprocessor and accessed using logical addresses, and in particular, a cache memory that easily ensures data consistency in a multiprocessor environment. Regarding cache memory that can be used.

[Conventional technology]

In order to perform high-speed operations on a computer, in addition to the computer's main memory, which serves as a large capacity memory, a cache memory that contains part of the memory data and operates at high speed is installed. , a computer user usually accesses the cache memory via a so-called logical address, and if a so-called cache miss occurs, for example when the required data is not in the cache memory, the required data is further accessed from the main memory via a physical address. There are cases where the cache memory is rewritten by importing the data.

The present invention relates to a cache memory suitable for such computer operations.

One of the recently developed 32-bit microprocessor units (MPUs) is the Motorola MC6.
There is a trend for cache memory to be incorporated on chips to improve performance, as in the case of the 8030, and address translation units to support virtual memory have also begun to be incorporated on chips. This overall configuration is shown in FIG.

In FIG. 4, the MPU chip is composed of an arithmetic execution unit which is a core, a cache memory which temporarily stores instructions or data, and an address translation unit which converts an internal logical address into a physical address in order to access the main memory.

A cache memory built into a chip to allow the arithmetic execution unit to fetch data at high speed is normally accessed using a logical address. On the other hand, if a cache miss occurs, the address conversion unit converts the logical address into a physical address, fetches desired data from the main memory, and stores it in the cache memory. therefore,
The cache memory stores sets of logical addresses and data corresponding to the addresses for the number of entries. An example thereof is shown in FIG.

The example in Figure 5 is a so-called fully associative configuration with a cache capacity of 2 bytes and a block size of 16 bytes, and each of the 128 entries contains a 28-bit logical address that specifies each block and 16-byte data for that address. be remembered.

A valid flag bit is also provided for each entry to identify whether the entry contents are valid or invalid.

By the way, in a system that uses multiple MPUs that incorporate cache memory on the chip that is accessed using logical addresses, that is, in a multiprocessor environment, one MPU can When data is rewritten, it is necessary to ensure the validity of data in cache memories in other MPUs.

With conventional cache memory built into MPU chips, so to speak, on-chip, it is not possible to specify the logical address that corresponds to an external physical address, so when you want to invalidate the data corresponding to the physical address. ensured data validity by invalidating all entries in cache memory. This method ends up invalidating even things that do not need to be invalidated, which significantly reduces the performance improvement achieved by putting the cache memory on-chip, and in effect places a large limit on its use as a multiprocessor.

On the other hand, there are MPUs that access on-chip cache memory using physical addresses, but in this case, address conversion is always required when accessing data, which increases the time required to capture data and reduces performance as a processor. was causing

[Problem M to be solved by the invention] As described above, in the conventional technology, when access is made using a logical address, the logical address corresponding to the physical address cannot be specified, leading to a problem in which performance as a multiprocessor is degraded. Furthermore, there is a problem that the performance of the processor deteriorates even when access is performed using a physical address, which requires a solution.

The object of the present invention is to provide access using logical addresses.

Another object of the present invention is to provide a cache memory that can ensure data consistency in a multiprocessor environment without causing a decrease in processor performance.

[Means for Solving the Problems] In order to achieve the above object, the present invention takes the following measures. That is, in a cache memory accessed by a logical address, a search address input section that inputs at least a part of an in-page offset address common to the logical address and the physical address after address conversion as a search address; Means is added for invalidating an entry in the address tag section in the cache memory that matches the search address input from the search address input section.

[Function] The addition of a search address input section to the cache memory that inputs at least a part of the mutually common in-page offset address between the logical address and the physical address after address conversion as the search address is invalidated. This makes it possible to search the cache memory using the search address in the in-page offset address field of the desired physical address. Moreover, in this case, the performance of the processor does not deteriorate.

Since this search results in a search for a related entry, the additional means of the present invention invalidates the entry that matches the search address input from the search address input section in the address tag section in the cache memory. It will become This brings about a significant performance improvement, for example, compared to the conventional technology in which all entries in the cache memory were invalidated because it was not possible to search the cache memory using a physical address.

That is, the means of the present invention makes it possible to efficiently ensure data consistency in a multiprocessor environment without causing a decrease in processor performance.

〔Example〕

For example, when converting a 32-bit logical address into a 32-bit physical address in an MPU with a fixed page size of 4 KB, the present invention converts the upper bits of the logical address, for example, 20 bits, as shown in FIG. The method of obtaining the physical page number of 20 bits is used.

That is, the lower bits of the logical address (12 bits in this example) mean the offset address within the physical page of the main memory, and the field of this intra-page offset address is the same address information for the logical address and the physical address. Therefore, if you search the cache memory using only the in-page offset address field of the physical address you want to invalidate, the relevant entry will be found, and by resetting the valid flag of that entry to "0", the cache memory data will be will be guaranteed.

FIG. 2(a) shows a first embodiment of the present invention.

This example is an example of a fully associative configuration with a block size of 16 bytes, and each entry stores a 28-bit logical address, a valid flag bit, and 16 bytes of data. In normal cache memory access, the operand address, which is a logical address, is input to the address tag section, and the upper 28 bits are compared in the address tag section of all entries, and if there is a matching entry, its valid flag is set to 41171. If so, select and output 4 bytes from the 16 bytes of data belonging to that entry. On the other hand, when a physical address to be invalidated is input, the upper 20 bits are masked in the search address input section, and all entries are searched using part of the lower 8 bits of the intra-page offset address. If a matching entry exists, its valid flag is set to tt OII
Reset to . In this case, since the address is searched only using the intra-page offset address field, entries other than the entry you want to invalidate may be invalidated, but considering the nature of data locality, the number of entries with the same intra-page offset field It is expected that there will be a small number of entries, and it is thought that the performance will be significantly improved compared to the conventional technology that invalidates all entries in the cache memory.

FIG. 2(b) is a specific example of a circuit that realizes FIG. 2(a). The address tag section is constructed by arranging CAM cells two-dimensionally, and uses the unmasked 8-bit in-page offset address field as the search address for SL, 5L.
(i=1 to 8) and search all entries. In an entry that matches the lower 8 bits of the stored address tag part, the match line ML becomes l#[ighl+, so by raising the reset clock φk,
Reset the valid flag of the entry.

FIG. 3 shows a second embodiment of the present invention, which is an example of a so-called direct mapping configuration with a block size of 16 bytes. In this configuration, the search address input section is composed of an address decoder, which accesses one entry in the address tag section using the set address formed by the lower 5 bits of the input address, and if the contents of that entry match the input address, And when the valid flag is "1", the data of the entry is read. Therefore, in a single configuration, a set address consisting of a part of the intra-page offset address field of the physical address to be invalidated is input, and the valid flag of the entry of the set address is unconditionally invalidated.

Therefore, in a cache memory with this direct mapping configuration, it is only necessary to add a circuit that resets the valid flag in response to an input set address, and even in a cache memory with a 2-way or 4-way set associative configuration, this With a configuration similar to that of the second embodiment, it is possible to easily invalidate only the entry related to the physical address to be invalidated.

〔Effect of the invention〕

As explained above, in order to ensure the compatibility of cache memory data accessed by logical addresses, the present invention is capable of searching for addresses using only the in-page offset address field of a physical address input from the outside. Since a circuit is added to invalidate matching entries, it is possible to invalidate only the entries related to the physical address input from the outside that you want to invalidate, ensuring data consistency with the external main memory and cache. Memory can be used efficiently.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the present invention in detail, Fig. 2(a), (
b) is a first embodiment of the present invention, FIG. 3 is a second embodiment of the present invention, FIG. 4 is a schematic diagram of a microprocessor unit with a conventional cache memory on-chip, and FIG. 5 is a conventional This is an example of the configuration of a cache memory. Patent applicant Nippon Telegraph and Telephone Corporation

Claims (1)

[Claims] In a cache memory accessed by a logical address, a search address input section for inputting at least a part of an offset address in a page common to the logical address and a physical address after address conversion as a search address; A cache memory further comprising means for invalidating an entry in an address tag section in the memory that matches a search address input from the search address input section.