JPH02111223A - Current limiter circuit - Google Patents

Abstract

PURPOSE:To simplify a circuit by limiting a rush current by an input resistor, an input capacitor when a field effect transistor FET is OFF, and operating a FET based on a voltage between the source and the drain of the FET in a suppressing direction at the time of overcurrent, and limiting the overcurrent. CONSTITUTION:A rush current is limited by an input resistor 2 and an input capacitor 3 when a FET 1 is OFF, and the FET 1 is then turned ON to obtain a predetermined current. On the other hand, a voltage between the source and drain terminals (a) and (b) of the FET 1 is raised at the time of overload, the voltage is detected through circuit terminals a', b', and their outputs are supplied to the base of a gate voltage control transistor 8. As a result, the transistor 8 which remains OFF so far is turned ON, the voltage between the gate and the source of the FET 1 is varied, and a current between the source and the drain of the FET 1 is limited. Accordingly, a current to an output side terminal OUT is limited to prevent the overcurrent. Thus, the circuit can be simplified.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an input current limiting circuit in a power supply circuit.
In particular, the present invention relates to a current limiting circuit that limits both inrush current when the input switch is closed and overcurrent during overload.

[Conventional technology]

At -C, turn on the input switch to the power circuit of the electrical equipment.

In order to protect the equipment from inrush currents at times, a limiting circuit is provided to limit the inrush currents. Similarly, a limiting circuit is also provided to protect the device from overcurrent that occurs during overload. For this reason, conventional power supply circuits are provided with both an inrush current limiting circuit and an overcurrent limiting circuit.

[Problem to be solved by the invention]

In the conventional power supply circuit described above, a circuit for limiting inrush current and a circuit for limiting overcurrent are separately configured, and each of these circuits is attached to the original power supply circuit. For this reason, there is a problem that the configuration of the entire power supply circuit becomes complicated, and mutually overlapping parts are mounted, which becomes an obstacle to miniaturization and cost reduction of the power supply circuit.

SUMMARY OF THE INVENTION An object of the present invention is to provide a current limiting circuit that has a simplified configuration, is smaller in size, and can be lowered in cost.

[Means for Solving the Problems] The current limiting circuit of the present invention includes a field effect transistor (hereinafter referred to as FET) whose source and drain are connected between a power supply line connecting an input terminal and an output terminal, and a field effect transistor (hereinafter referred to as FET) whose source
an input resistor connected between the input resistors, an input capacitor connected to the power supply line, a gate voltage control transistor inserted between the source and gate of the FET to control the gate voltage, and a gate voltage control transistor connected between the source and drain of the FET. and a voltage detection/control circuit that detects voltage and outputs a predetermined signal to the gate voltage control transistor.

[Effect]

In the above configuration, when the FET is in the off state, the input resistance,
The input capacitor limits the inrush current, then the FET
is turned on to ensure the required current, and in the event of overcurrent, F is turned on.
The FET is operated in the suppressing direction via the gate voltage control transistor by the action of the voltage detection/control circuit based on the source-drain voltage of the ET, thereby limiting the overcurrent.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

The figure is a circuit diagram of an embodiment of the present invention, in which the source and drain of an FET (field effect transistor) 1 are connected between a power line connecting a power input terminal IN and a power output terminal OUT. An input resistor 2 is connected between the source and drain of this FET 1, and an input capacitor 3 for absorbing rush current is connected to the drain side. Further, a capacitor 4 having a larger capacity than the input capacitor 3 and a resistor 5 are connected between the source and the gate, and a collector of a gate voltage control transistor 8, which is composed of a bipolar transistor and controls the gate voltage of the FET 1, is connected between the source and the gate. , the emitters are connected via a diode 6 and a resistor 7. Furthermore, a constant current diode 9 is connected to the gate of FETI.
are connected.

In addition, resistance 10. and 11 are the input resistance and bias resistance of the gate voltage control transistor 8, respectively.

On the other hand, the source and drain terminals ab of the FETI are composed of an operational amplifier 12 and resistors 13 to 19.
They are respectively connected to circuit ends a' and b' of a voltage detection/control circuit that detects the voltage between the drains. Further, the output terminal C' of this circuit is connected to the base terminal C of the gate voltage control transistor 8.

According to this circuit, immediately after the power switch (not shown) is turned on, the FETI is in the off state, and the current input to the input terminal INK is limited by the input resistor 2 and charged to the input capacitor 3. This prevents inrush current from being output to the output terminal OUT.

After input capacitor 3 is charged, capacitor 4 is also charged with some delay, and this capacitor 4
FETI is turned on by the voltage across it. This results in
A low resistance state is established between the source and drain of F E T 1, and the normal current of the power supply circuit is outputted through this source and drain.

On the other hand, during overload, the current flowing through FETI increases and FE
The voltage between the resource and drain terminals a and b increases due to the product of TI and the source/drain resistance.

This voltage is detected in a voltage detection and control circuit through circuit terminals a'-b', and its output is supplied to the base of the gate voltage control transistor 8. As a result, the gate voltage control transistor 8, which had been in the off state until then, is turned on, changing the gate-source voltage of the FET 1, and limiting the source-drain current of the FETI.

This limits the current to the output terminal 0tJT,
Prevent overcurrent.

Therefore, in this example, one FETI is used for both inrush current limiting and overcurrent limiting, and other circuit components are also used for both current limiting, thereby reducing the number of components and simplifying the circuit. becomes possible.

[Effects of the Invention] As explained above, the present invention limits the inrush current using the input resistor and input capacitor when the FET is in the OFF state, and when overcurrent occurs, the voltage detection/control circuit based on the source-drain voltage of the FET limits the inrush current. This action causes the FET to operate in the suppressing direction via the gate voltage control transistor to limit overcurrent, so the FET and other components can be used for both the inrush current limiting circuit and the overcurrent limiting circuit, reducing the number of components. , it is possible to simplify the circuit and achieve miniaturization and cost reduction.

[Brief explanation of the drawing]

The figure is a circuit diagram of an embodiment of the present invention. 1... Field effect transistor (FET), 2... Input resistance, 3... Input capacitor, 4... Capacitor, 5... Resistor, 6... Diode, 7... Resistor,
8... Gate voltage control transistor, 9... Constant current diode, 10.11... Resistor, 12... Operational amplifier, 13-19... Resistor. Procedures (Method) % Formula % Display of the case 1986 Patent Application No. 75920 Name of the invention Person who amends the current limiting circuit Related to the case Patent applicant Name NEC Co., Ltd. Rijinsho 103 Tokyo Nagatani Building, 3-1-6 Nihonbashi Honmachi, Chuo-ku
907 amendment target drawing riden β search and $ tumor? , 0芹＠gdan 工抽j等口路

Claims (1)

[Claims] 1. A field effect transistor whose source and drain are connected between the power supply lines connecting the input terminal and the output terminal, an input resistor connected between the source and drain, an input capacitor connected to the power supply line, and the field effect transistor. a gate voltage control transistor that is inserted between the source and gate of the transistor to control the gate voltage; and a voltage that detects the voltage between the source and drain of the field effect transistor and outputs a predetermined signal to the gate voltage control transistor. A current limiting circuit comprising a detection/control circuit.