JPH02110752A - Cache memory control system - Google Patents

Abstract

PURPOSE:To speed up a memory access by reading an ineffective word, reflecting to a cache memory and reading an effective word from the cache memory when one effective bit shows the ineffectiveness at the time of being a cache error. CONSTITUTION:The result of the access of an address array (AA) 5 by an address register (AAG) 3 is classified, and stored into a status register (SBR) 10. Here, when the effective bit to show the ineffectiveness is one at the time of being the cache error, a word corresponding to the effective bit is read from a cache memory, only the ineffective word is read from a main memory, and therefore, it is not necessary to re-register the effective word to the cache memory. Thus, the action time of the memory access is shortened and the processing speed can be made larger.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a cache memory control method, and in particular to a cache memory control method that maintains a copy of data in a main memory in units of blocks each consisting of a plurality of words, and checks the validity of data within these blocks. A control method for a cache memory that has valid bits for management in word units.The control method for a cache memory is to store a block address and the valid bits for this block address in the data section in the directory section of the cache memory device. There is a method in which data is registered in a book and managed on a book-by-book basis.

In such a control method, when a read request is sent to the cache memory device, if a cache miss occurs by determining the block address and valid bit, the block is read from the main memory device. It has become.

On the other hand, in some types of information processing systems, a cache memory device manages the correspondence between the contents of a block and the contents of a main storage device using a plurality of valid bits. That is, in order to manage the contents of a block within a cache memory device in units of words constituting this block, there are devices in which a valid bit is provided for each word.

In this method, a valid bit corresponding to a word that is a partial area within a block is reset and invalidated by a store operation or a store operation by another processor. Therefore, a case may arise where only one valid bit in a block indicates invalidity at a certain moment. Even in such a case, when a cache miss occurs due to a read request, the block for which five read requests were made is read from the main memory.

In this way, in the conventional method, even when there is a cache miss that occurs because only one valid bit in a block is invalid even though there are multiple valid bits in the block, the main memory Since five reading blocks are read out for each block, it takes too much time to access the memory, resulting in a reduction in operating speed.

Furthermore, in the conventional method, there may be a case where one or more (at least one) valid bit in a block indicates invalidity at a certain moment. Even in such a case, when a cache hit occurs due to a read request, no block read is performed from the main memory. Therefore, valid data cannot be reflected in the cache memory device until a cache miss occurs.

Considering the fact that the accessed block generally has a relatively high access frequency thereafter, the cache hit rate decreases in the above-mentioned case, which again results in a decrease in processing speed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a cache memory control method that shortens memory access operation time and increases processing speed.

Another object of the present invention is to provide a cache memory control method that reduces the memory access time that occurs when a cache miss occurs when there is one valid bit.

Still another object of the present invention is to improve the cache hit rate by reading block data from the main memory and reflecting the data in the cache memory even when there is a cache miss when there is one or more valid bits. An object of the present invention is to provide a cache memory control method.

According to the present invention, a copy of data in the main memory is maintained in blocks each consisting of a plurality of words, and valid bits for managing the validity of data in these blocks are stored in units of words. A control method for a cache memory having:
Means for determining whether a cache hit or a cache miss occurs in response to a read request to the cache memory, and means for detecting an invalidation state of a valid bit in a word unit in a block to be read when a cache miss is determined. , when the detection result indicates that only one word is invalid, the invalid word is not read from the main memory and the other words are read from the cache memory, and the detection result indicates that only one word is invalid. A cache memory control method is obtained, characterized in that when the cache memory indicates invalidity, the block of the read request is read from the main storage device.

Further, according to the present invention, there is provided a cache memory that holds a copy of data in the main memory in units of blocks each consisting of a plurality of words, and has valid bits in units of words for managing the validity of data in these blocks. The control method includes means for determining whether a cache hit or a cache miss occurs in response to a read request to the cache memory, and when a cache hit is determined, an invalidation state of a valid bit in a word unit in a block to be read. When the detection result indicates that at least one word is invalid, the corresponding block is read out from the cache memory and sent to the read request source, and the corresponding block is sent to the main storage device. A cache memory control method is obtained, which is characterized in that reading of blocks is performed.

Example 1 Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a detailed diagram of a group of gates 8 for comparing successively requested addresses and addresses registered in the address array (AA) 5. Here, one set of set associative cache will be explained, and it is assumed that a valid bit exists for each word.

First, an operation related to a read request from a host device (not shown) will be explained. The read request and its address are sent to the address selector (S) through signal lines 51 and 52.
AX)1. It is selected by the status selector (SSX) 2 and stored in the address register (AAR) 3 and status register (SAR) 4, respectively.

When the request is decoded by 5AR4 to be a read request, address array (AA)5 and A
Part 59 of the output of AR3 is addressed by A
The output of A5 and another part of the output of AAR3 are compared by comparator 7. The lower two bits of AARl are input to a read/write decoder (R, WDEC) 6 through a signal line 60, and each output is decoded by this decoder 6 so as to represent a word position within the block. In this case, 2 bits become 4. Each section from VO to ■3 of AA5 indicates the validity of each magazine in the block, and the validity is compared by the gate group 8 in vO to V3 with respect to the word in the block of the address held in AARI.

The results of access to AA5 by AAR3 are classified into the following three categories and stored in the status register (SBR) 10.

a, -'r Yash hit (condition + IIIT); requested data exists in cache storage.

b. Cache miss (condition: old S-HULTFHIS
).

The requested data is not in cache storage, which means that only one word in the block has its valid bit invalidated.

c,'r yiz Yumis (Condition: 813- HULT
IHIS) ; The requested data is not present in cache storage, which means that the valid bits of two or more words in the block are invalid.

The operation of the next cycle is determined from the state of 5BRIO.

In the case of a, old ■, the data array (DA) 13 is addressed by a partial output 73 of the near address register (ABR) 9, the output is selected by the data selector (SDX) 14 by the signal line 75, and the data register (OCR) )
15 and returned to the requester in the next cycle.

b, Hls, 14uLTIH1s: A request to read data from the main memory is issued. The request address is indicated by the output of ABR9. 5 at the same time
BRIO output 80 is status decoder (SDEC)
16, and block reading is indicated through signal line 81. The contents of ABR9 and 5BRIO are stored in AAR3 and 5AR4, respectively, via signal lines 71.74 and 5AXI and 5SX2.

AA5 is addressed by AAR3 as in the case of a read request, but in this case AA5's AA
The upper part of AAR3 is written in the signal line 57.

■0 to ■3 are set to 0 (invalid).

In the case of C1 old s, m: A request to read data to the main memory is issued. The request address is indicated by the output of ABR9. At the same time, the output 80 of 5BR10 is 5DE
It is decoded by C16 and an instruction is given through signal line 82 to read one word.

Next, the operation of reading data from the main memory will be described.

Data is transferred to the data register (DAR) via signal line 77.
11. At the same time, the corresponding address is signal line 5
It is stored in AAR3 via 2 and 5AX1. Further, information indicating that data is being read is stored in 5AR4. Here, there are two states depending on the contents of 5AR4.

a. For block read: AA5 is output 5 of AAR3
Addressed by 9. 3 is selected from VO by another output 60 of AARl13 and the word position in the block read by the decoder 6, and “
In the fourth cycle when 1'' (valid) is written, DA
The contents of RII, that is, the read data is stored in the data register (D
BR) moved to 12.

Also, AAR3 and 5AR4 are also ABR9 and S B RL O
Move to. DA13 is addressed by ABR9, and data in DBR,12 is written in accordance with the instruction from 5BRIO. In reading data, the above operation is performed four times in this example. It is assumed that the order in which data arrives from the main memory starts from the address where the gear miss occurred and is sent around the addresses within the block. In the first load operation, when writing the contents of DBR12 to DA13, the input of DCR15 is input to D by 5DX14.
The output cuff 9 of the BR 12 is selected by the signal line 76, and the read data is sent back to the host device in the next cycle.

b. For 1 word read: Enter the next cycle and DAR
The contents of II (read data) are moved to DBR12. At the same time, AAR3 and 5AR4 are also moved to ABR9 and 5BRIO, and in the next cycle, the data selected by the signal line 76 in 5DX14 is stored in DCR15. Thereafter, the read data is returned to the host device.

FIG. 2 shows a specific example of the gate group 8 of the block in FIG. Each bit output 66-6 of bit vO~■3
In the access result of AA5, using
813- This is a gate circuit for determining MULTIHIS and old S.

In this way, when a cache miss occurs and there is one valid hit indicating invalidity, the word corresponding to the valid bit is read from the cache memory, and only the invalid word is read from the main memory. Since there is no need to re-register the data in the cache memory, the time required to access the main memory is shortened, and the cache memory can be used for other processing by that amount (3 words).

FIG. 3 is a block diagram of another embodiment of the present invention.
Portions equivalent to those in the figure are shown by Shogetsu. In this embodiment as well, one set of set associative cache will be explained, and it is assumed that each word has a valid bit.

First, an operation related to a read request from a host device (not shown) will be explained. The read request and its address are sent to the address selector (S) through signal lines 51 and 53.
AX)1. It is selected by the status selector (SSX) 2 and stored in the address register (AAR) 3 and status register (SAR) 4. When it is decoded as a read request by 5AR4, it is addressed by address array (AA) 5 and part 59 of the output of AAR3, and the output of AA5 and another part of the output of AAR3 are compared by comparator 7. Ru. The lower two bits of AARl are sent to a read/write decoder (Il) through a signal line 60.
14DEC) 6 decodes each output to represent a word position within the block. In this case, 2 bits become 4 trees. Each part of AA5 from ■0 to ■3 displays the validity of each magazine in the block, and gate group 8 allows AAR
The validity of the words in the block of addresses held in 1 is examined from 0 to 3.

The results of access to AA5 by AA unit 3 can be classified into the following three types: status register (SBR)1.
Stored at 0.

a, Cash Hiller 1~ (Condition: IIIT/VAI
ID) ; The requested data is present in cache storage and no valid bits in the block are invalidated.

b. Cash hit (condition: old ■/blood): The requested data exists in the cache memory, and one or more valid bits in the block are invalid.

C. Cache miss (condition: old S): The requested data does not exist in the cache memory.

The operation of the next cycle is determined from the state of 5BRIO.

a, old ■・V^11[If 1, near address register (A
The data array (DA) 13 is addressed by the output 3 of the BR) 9, and its output is sent to the data selector (SD).
X) 14 by the signal line 75, stored in the data register (DCR>15), and returned to the request source in the next cycle.

b, HIT-VALID) case: 110 ・
The data is returned to the requestor as in the VAIID case. At the same time, a request to read data to the main memory is issued.

The request address is indicated by output cuff 2 of ABR9. The contents of ABR9 and 5BRIO are signal lines 71.7
4 via SAX and SSX, respectively to AA section 3.
and stored in 5AR4. AA5 is addressed by the AA section 3 as in the case of a read request, but
In this case, the AA section of AA5 is connected to the signal line 57.
The upper part of part 3 is written. (2) 0 is set from 0 to v3.

In the case of C1 old S: A data read request is issued to the main memory, and the following operations are performed in the same way as in the case of old ■ VALID.

Next, the operation of reading data from the main memory will be described.

Data is signal fl! 77 to the data register (DA
R) 11, and the corresponding address is stored in the signal line 102.
and is stored in the AA section 3 via 5AX1. Also, information indicating that data is being read is stored in the SAR. AA5 is A
It is addressed by the output 59 of the A section 3. Based on another output 60 of the AA section 3 and the word position within the block read by the decoder (RHEC) 6, v3 is selected from 0 and "1" is written.

In the next cycle, the contents of DARII, ie, read data, are moved to the data register (DBR>12.DA1
3 is addressed by ABR9, and data in DBR12 is written in accordance with an instruction from 5BRIO. In reading data, the above operation is performed four times in this example.

The order in which data arrives from main memory is
HIT / VALID) or cache miss (old S)
The data is sent to the addresses in the block, starting from the address where the block was created. The following operations are cache hits (old ■・VALID) and cache misses (old S)
It is done in the same way. However, in the case of a cache miss, the first load operation is when writing the contents of DBR12 to DA13, the input of DCRI5 is D by 5DX14.
B F (12 output cuffs 9 are selected by the signal line 76, and read data is returned to the host device in the next cycle.

FIG. 4 shows a concrete example of the gate group 8 connected to the block of FIG. Outputs 61 to 64 and valid bits ■0 to ■
This is a gate circuit for determining IIIT, HIS, and VALID, which are the access results of AA5, using the respective bit outputs 66 to 69 of AA5. In this way, when at least 1 valid bit indicates invalid when caching is booted, the data is read from the main memory in the same way as a cache miss, and the data in the main memory is reflected in the cache memory. Therefore, we can expect an improvement in the cache and boot rate.

Fish friend! According to the present invention, when one valid bit indicates invalidity at the time of a cache miss, the invalid word is read from the main memory and reflected in the cache memory, and the valid word is read from the cache memory. This has the effect of reducing the operating time when data is reflected in the cache memory, thereby speeding up memory access.

Furthermore, when at least one valid bit indicates invalid during a cache hit, the corresponding block data is read from the main memory and the invalid word is reflected in the cache memory, similar to a cache miss, improving the cache hit rate. This has the effect of speeding up memory access.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a specific example circuit diagram of the gate group of the block in FIG. 1, FIG. 3 is a block diagram of another practical example of the present invention, and FIG. FIG. 4 is a specific example circuit diagram of a gate group of the block of FIG. 3; Description of symbols of main parts 5 Address array 7 Comparator 8 Gate group 13 Data array Applicant: NEC Corporation 1 person)

Claims (2)

[Claims] (1) A cache memory control method in which copies of data in the main memory are held in blocks consisting of multiple words, and each word has a valid bit for managing the validity of the data in these blocks. means for determining whether it is a cache hit or a cache miss in response to a read request to the cache memory; and when a cache miss is determined, detecting an invalidation state of a valid bit in a word unit in a block to be read. means is provided, and when the detection result indicates that only one word is invalid, the invalid word is read from the main memory and the other words are read from the cache memory, and the detection result is read from the cache memory. 1. A cache memory control method, characterized in that when a plurality of words are invalid, a block of a read request is read from the main storage device. (2) A cache memory control method in which copies of data in the main memory are held in blocks consisting of multiple words, and each word has a valid bit for managing the validity of data within these blocks. means for determining whether it is a cache hit or a cache miss in response to a read request to the cache memory; and when a cache hit is determined, detecting an invalidation state of a valid bit in a word unit in a block to be read. means is provided, and when the detection result indicates that at least one word is invalid, the corresponding block is read and sent from the cache memory to the read request source, and the corresponding block is read from the main storage device. A cache memory control method characterized by: