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JPH0211032B2 - - Google Patents

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Publication number
JPH0211032B2
JPH0211032B2 JP58165936A JP16593683A JPH0211032B2 JP H0211032 B2 JPH0211032 B2 JP H0211032B2 JP 58165936 A JP58165936 A JP 58165936A JP 16593683 A JP16593683 A JP 16593683A JP H0211032 B2 JPH0211032 B2 JP H0211032B2
Authority
JP
Japan
Prior art keywords
wiring board
layer
conductive pattern
multilayer wiring
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58165936A
Other languages
Japanese (ja)
Other versions
JPS6057999A (en
Inventor
Masafumi Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP58165936A priority Critical patent/JPS6057999A/en
Publication of JPS6057999A publication Critical patent/JPS6057999A/en
Publication of JPH0211032B2 publication Critical patent/JPH0211032B2/ja
Granted legal-status Critical Current

Links

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】 本発明は多層配線板に関し、とくにフラツトパ
ツケージ、ピングリツドIC等の密接した多数の
接続ピンをもつた多端子電子部品(以後部品と略
称)を実装する印刷配線板の導電パツドに関す
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multilayer wiring board, and in particular to a printed wiring board on which multi-terminal electronic components (hereinafter referred to as components) having a large number of closely spaced connection pins such as flat packages and pin grid ICs are mounted. Regarding conductive pads.

従来、多層配線板上に設けられた導電パツドは
多層配線板の最外層に設けてあるため、接続ピン
は3列以上の配列を有する部品を実装する場合に
は、最外層の部分に回路パターンが集中する。そ
のため一部の回路パターンを内部層に通過して集
中を回避させても、最外層上にランドのみの導電
パツドを有する層を設ける等の対策が必要であつ
た。
Conventionally, conductive pads provided on multilayer wiring boards are provided on the outermost layer of the multilayer wiring board, so when mounting components with connection pins arranged in three or more rows, the circuit pattern is placed on the outermost layer. is concentrated. Therefore, even if part of the circuit pattern is passed through the inner layer to avoid concentration, countermeasures such as providing a layer having conductive pads only as lands on the outermost layer are required.

また、これと同時に内部の回路パターンと外部
の導電パツドとの接続をするためのスルホールめ
つき等を必要としていた。
At the same time, through-hole plating and the like were required to connect the internal circuit pattern to the external conductive pad.

本発明の目的は、かかる内部の回路パターンと
外部の導電パツドとの接続を不要にした導電パツ
ドを有する多層配線板を提供することにある。
An object of the present invention is to provide a multilayer wiring board having conductive pads that eliminates the need for connection between such internal circuit patterns and external conductive pads.

本発明によれば絶縁板上に導電パターンを設け
て積層する配線基板の各面の一部を階段状に露出
させ、かつ露出させた部分に導電パターンを接続
する導電パツドを設けたことを特徴とする多層配
線板が得られる。
According to the present invention, a conductive pattern is provided on an insulating plate to expose a part of each side of the laminated wiring board in a stepwise manner, and a conductive pad is provided on the exposed part to connect the conductive pattern. A multilayer wiring board is obtained.

以下、本発明の実施例を第1図a,bおよび第
2図a,bを参照して説明する。
Embodiments of the present invention will be described below with reference to FIGS. 1a and 2b and FIGS. 2a and 2b.

実施例 1 第1図a,bは本発明の一実施例を示すもの
で、特にフラツトパツケージやチツプキヤリア等
の端子を圧接や溶接、もしくは半田付け等により
実装するのに適した導電パツドを表面に有する多
層配線板である。
Embodiment 1 Figures 1a and 1b show an embodiment of the present invention, in which a conductive pad suitable for mounting terminals of flat packages, chip carriers, etc. by pressure welding, welding, soldering, etc. is used on the surface. This is a multilayer wiring board with

第2絶縁層3の矩形状の切除部から露出するよ
うに配設する。従つてフラツトパツケージやチツ
プキヤリア等の部品のピンの一部と接続できるよ
うに対応させて第3層の導電パツド4を第3絶縁
層1上の導電パツド4と接続した回路パターン2
は第2絶縁層3により外部に露出しない構造とな
るる。同じく部品の残りの端子の一部と接続でき
るように対応させて第2層の導電パツド4を第1
絶縁層5に第3絶縁層より大きく設けた切除部か
ら露出するように同位置に配設する。
It is disposed so as to be exposed from the rectangular cutout of the second insulating layer 3. Therefore, the circuit pattern 2 connects the conductive pads 4 of the third layer to the conductive pads 4 on the third insulating layer 1 in such a way that they can be connected to some of the pins of components such as flat packages and chip carriers.
is not exposed to the outside due to the second insulating layer 3. Similarly, the second layer conductive pad 4 is connected to the first layer so that it can be connected to some of the remaining terminals of the component.
The insulating layer 5 is disposed at the same position so as to be exposed from a cutout portion that is larger than the third insulating layer.

従つて第2絶縁層3上の回路パターン2も表面
の第1絶縁層5に隠された構造となり、このため
第1から第3の各絶縁層上の導電パツドは階段状
の窪みの周囲に沿つて各階段面上に露出した形状
に設けられる。
Therefore, the circuit pattern 2 on the second insulating layer 3 also has a structure hidden by the first insulating layer 5 on the surface, and therefore the conductive pads on each of the first to third insulating layers are placed around the step-like recess. It is provided in an exposed shape on each staircase surface along the line.

なお、更に層数を増した場合にも、これと同様
に階段状に設けることができる。
Note that even when the number of layers is further increased, they can be provided in a stepwise manner in the same way.

実施例 2 同様に第2図a,bはピングリツドアレイ等の
プラグインタイプの部品の実装が可能なように部
品端子の実装や貫通した実装孔を導電パツドに設
けた場合の多層配線板の実施例を示すものであ
る。
Embodiment 2 Similarly, Figures 2a and 2b show multilayer wiring boards in which component terminals are mounted and through mounting holes are provided in the conductive pads so that plug-in type components such as pin grid arrays can be mounted. This is an example of the following.

第2図の実施例の場合にも導電パツド4の部分
が階段状を呈して設けられるのは第1図の実施例
1と全く同様であるが、第1図と大きく異なる点
は、導電パツド4に裏面まで貫通しない部品実装
穴6や、裏面まで貫通する部品実装孔6を設けた
ことである。裏面まで貫通しない部品実装孔6
は、各層を積層する前にあらかじめ必要な層のパ
ツド中心に実装穴を設けておくことで容易に得る
ことができる。さらにこの場合ブラインドスルホ
ールにする事も同様に可能である。
In the case of the embodiment shown in FIG. 2, the part of the conductive pad 4 is provided in a step-like manner, which is exactly the same as in the embodiment 1 shown in FIG. 4 is provided with component mounting holes 6 that do not penetrate to the back surface and component mounting holes 6 that penetrate to the back surface. Component mounting hole 6 that does not penetrate to the back side
can be easily obtained by providing a mounting hole at the center of the pad of the required layer before stacking each layer. Furthermore, in this case, it is also possible to use a blind through hole.

以上、本発明により次の効果がある。 As described above, the present invention has the following effects.

(i) 内部の導電層パターンに接続して形成された
導電パツドが直接外部に露出しているため、ス
ルホールめつき等により外部の導電パツドへ接
続部分を設ける必要がない。
(i) Since the conductive pad formed in connection with the internal conductive layer pattern is directly exposed to the outside, there is no need to provide a connection part to the external conductive pad by through-hole plating or the like.

(ii) 多層配線板の表面に窪みができるので、実装
する部品の突出を少なくし、かつ固定を強固に
行なうことができる利点がある。
(ii) Since depressions are formed on the surface of the multilayer wiring board, there is an advantage that the protrusion of the mounted components can be reduced and the components can be firmly fixed.

なお、いづれの実施例においてもICの実装だ
けでなく同様な接続ピンの形状を有する電子部品
の接続実装にも対応できる。
It should be noted that any of the embodiments can be used not only for mounting ICs but also for connecting and mounting electronic components having similar connection pin shapes.

また単一の部品のみでなく、複数個の部品を同
時に実装できることは勿論である。
Moreover, it goes without saying that not only a single component but also a plurality of components can be mounted simultaneously.

【図面の簡単な説明】[Brief explanation of drawings]

第1図a,bは本発明多層配線板の第1の実施
例主要部を拡大して示したそれぞれ平面図および
断面図。第2図a,bは本発明の第2の実施例主
要部のそれぞれ平面図および断面図。 1……第3絶縁層、2……回路パターン、3…
…第2絶縁層、4……導電パツド、5……第1絶
縁層、6……部品実装穴(孔)。
FIGS. 1a and 1b are a plan view and a sectional view, respectively, showing enlarged main parts of a first embodiment of the multilayer wiring board of the present invention. FIGS. 2a and 2b are a plan view and a sectional view, respectively, of the main parts of a second embodiment of the present invention. 1...Third insulating layer, 2...Circuit pattern, 3...
...second insulating layer, 4...conductive pad, 5...first insulating layer, 6...component mounting hole (hole).

Claims (1)

【特許請求の範囲】[Claims] 1 絶縁板上に導電パターンを設けて積層した配
線基板が階段状の窪みを有し、各階段面上に前記
導電パターンの一部が露出され、かつ前記導電パ
ターンの幅より広い幅を有する導電パツドが前記
階段状の窪みの周囲に沿つて前記導電パターンと
接続されて設けられていることを特徴とする多層
配線板。
1. A wiring board laminated with a conductive pattern provided on an insulating plate has a step-like recess, a part of the conductive pattern is exposed on each step surface, and the conductive pattern has a width wider than the width of the conductive pattern. A multilayer wiring board characterized in that a pad is provided along the periphery of the stepped recess and connected to the conductive pattern.
JP58165936A 1983-09-09 1983-09-09 Multilayer circuit board Granted JPS6057999A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58165936A JPS6057999A (en) 1983-09-09 1983-09-09 Multilayer circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58165936A JPS6057999A (en) 1983-09-09 1983-09-09 Multilayer circuit board

Publications (2)

Publication Number Publication Date
JPS6057999A JPS6057999A (en) 1985-04-03
JPH0211032B2 true JPH0211032B2 (en) 1990-03-12

Family

ID=15821825

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58165936A Granted JPS6057999A (en) 1983-09-09 1983-09-09 Multilayer circuit board

Country Status (1)

Country Link
JP (1) JPS6057999A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0540128U (en) * 1991-10-29 1993-05-28 昭和電工株式会社 Folding container

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62156847A (en) * 1985-12-28 1987-07-11 Ibiden Co Ltd Multilayer printed circuit board and manufacture thereof
JPH02106874U (en) * 1989-02-10 1990-08-24
EP0774888B1 (en) 1995-11-16 2003-03-19 Matsushita Electric Industrial Co., Ltd Printed wiring board and assembly of the same

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943026Y2 (en) * 1976-10-25 1984-12-18 シャープ株式会社 Electric washing machine with towel rack
JPS58640Y2 (en) * 1977-10-13 1983-01-07 ヤンマーディーゼル株式会社 Misoperation prevention device for trolling equipment
JPS57187998A (en) * 1981-05-14 1982-11-18 Nippon Electric Co High density multilayer circuit board
JPS5868952A (en) * 1981-10-20 1983-04-25 Citizen Watch Co Ltd Electrode terminal for wiring connection
JPS59107139U (en) * 1983-01-07 1984-07-19 セイコーエプソン株式会社 IC chip mounting structure on circuit board
US4630172A (en) * 1983-03-09 1986-12-16 Printed Circuits International Semiconductor chip carrier package with a heat sink

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0540128U (en) * 1991-10-29 1993-05-28 昭和電工株式会社 Folding container

Also Published As

Publication number Publication date
JPS6057999A (en) 1985-04-03

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