JPH0210871A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0210871A JPH0210871A JP16284088A JP16284088A JPH0210871A JP H0210871 A JPH0210871 A JP H0210871A JP 16284088 A JP16284088 A JP 16284088A JP 16284088 A JP16284088 A JP 16284088A JP H0210871 A JPH0210871 A JP H0210871A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- metal
- wiring
- semiconductor device
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 239000002184 metal Substances 0.000 claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 22
- 230000004888 barrier function Effects 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims description 10
- 238000010030 laminating Methods 0.000 abstract 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、主としてＡｕ等を配線金属材料として用い
ている金属配線の信頼性を向上させた半導体装置に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device that mainly uses Au or the like as a metal wiring material and has improved reliability of metal wiring.
〔従来の技術）
第２図に従来のＭｏ層をバリアメタルとして使用してい
る配線金属の層構造を示す。[Prior Art] FIG. 2 shows the layer structure of a conventional wiring metal using a Mo layer as a barrier metal.
通常、配線金属の層構造は、第２図に示すように、Ｔ
ｉ ／ Ｍ ｏ ／ Ａ ｕ構造になっている。すなわ
ち、第２図において、１は半導体基板、例えばＧａＡｓ
基板、２は付着力を増すためのＴｉ層、３はバリアメタ
ルとなるＭｏ層、４は配線層であるＡｕ層であり、最下
層のＴｉ層２は、下地のＧａＡｓ基板１ないしは絶縁膜
との付着力を増すために形成され、第２層のＭｏ層３は
、Ａｕ層４がＧａＡｓ基板１に拡散するのを防ぐバリア
メタルとして用いている。Normally, the layer structure of wiring metal is as shown in FIG.
It has an i/Mo/Au structure. That is, in FIG. 2, 1 is a semiconductor substrate, for example, GaAs.
In the substrate, 2 is a Ti layer to increase adhesion, 3 is a Mo layer as a barrier metal, 4 is an Au layer as a wiring layer, and the bottom Ti layer 2 is connected to the underlying GaAs substrate 1 or an insulating film. The second Mo layer 3 is used as a barrier metal to prevent the Au layer 4 from diffusing into the GaAs substrate 1.
（発明が解決しようとする課題）
従来の半導体装置の配線金属は、上記のような層構造に
なっているため、半導体装置のプロセス過程でＡｕ層４
を形成後、高温炉などで処理する場合、Ｍｏ層層上上Ａ
ｕが横方向に拡散し、Ｍｏ層３の側壁を通って、下地の
ＧａＡｓ基板１あるいは最下層のＴｉ層２と反応してし
まうという問題点が明らかとなった。特に下地がＧａＡ
ｓ基板１の場合、ＡｕがＧａＡｓ中に拡散し、ＦＥＴな
どへの悪影響が懸念される。(Problems to be Solved by the Invention) Since the wiring metal of conventional semiconductor devices has a layered structure as described above, the Au layer 4 is formed during the process of semiconductor devices.
After forming, when processing in a high temperature furnace etc.,
It has become clear that u diffuses in the lateral direction, passes through the sidewalls of the Mo layer 3, and reacts with the underlying GaAs substrate 1 or the lowermost Ti layer 2. Especially the base is GaA.
In the case of the s-substrate 1, there is concern that Au will diffuse into GaAs and have an adverse effect on FETs and the like.
この発明は、上記のような問題点を解消するためになさ
れたもので、バリアメタル上での金属配線の横方向の拡
散を防止した半導体装置を得ることを目的とする。The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor device in which lateral diffusion of metal wiring on a barrier metal is prevented.
この発明に係る半導体装置は、基板上に少なくともバリ
アメタルとなるＭｏ層、Ｔｉ層、Ａｕ層を順次積層した
金属配線を備えたものである。A semiconductor device according to the present invention includes a metal wiring in which at least a Mo layer, a Ti layer, and an Au layer, which serve as barrier metals, are sequentially laminated on a substrate.
（作用） この発明においては、バリアメタルとなるＭ。(effect) In this invention, M serves as a barrier metal.
層と配線層であるＡｕ層の間にＴｉ層を設けたことによ
り、ＭＯ層上で見られるようにＡｕの横方向の拡散が防
止される。By providing the Ti layer between the wiring layer and the Au layer, lateral diffusion of Au as seen on the MO layer is prevented.
（実施例） この発明の一実施例を第１図について説明する。(Example) An embodiment of the invention will be described with reference to FIG.
第１図に示すように、この実施例においては、Ｎｏ層３
とＡｕ層４の間にＴｉ層２を設け、Ｔｉ、／ Ｍ ｏ
／ Ｔ ｉ ／ Ａ ｕの４層構造になっている。As shown in FIG. 1, in this embodiment, the No layer 3
A Ti layer 2 is provided between the and Au layer 4, and Ti,/Mo
It has a four-layer structure of / T i / A u.
なお、下地との付着力に問題がない場合は、Ｍ Ｏ／
Ｔ ｉ ／ Ａ ｕの３層構造でも良く、最下層のＴｉ
層２については設けなくてもよい。In addition, if there is no problem with the adhesion to the base, M O/
A three-layer structure of Ti/Au may also be used, with the lowest layer of Ti
Layer 2 may not be provided.
以上説明したように、この発明は、基板上に少なくとも
バリアメタルとなるＭｏ層、Ｔｉ層、Ａ１層を順次積層
した金属配線を備えたので、たとえ配線金属形成後、高
温炉などで処理を行っても、配線層であるＡｕ層が下地
などと反応することなく、信頼性が向上する効果がある
。As explained above, the present invention includes a metal wiring in which at least a Mo layer, a Ti layer, and an A1 layer, which serve as barrier metals, are sequentially laminated on a substrate. However, the Au layer, which is a wiring layer, does not react with the underlying layer, thereby improving reliability.
第１図はこの発明の半導体装置の配線構造の一実施例を
示す配線金属の層構造の断面図、第２図は従来の配線金
属層構造を示す断面図である。
図において、１はＧａＡｓ基板、２はＴｉ層、３はＭｏ
層、４はＡｕ層である。
なお、各図中の同一符号は同一または相当部分を示す。FIG. 1 is a cross-sectional view of a metal wiring layer structure showing an embodiment of the wiring structure of a semiconductor device according to the present invention, and FIG. 2 is a cross-sectional view showing a conventional metal wiring layer structure. In the figure, 1 is a GaAs substrate, 2 is a Ti layer, and 3 is a Mo layer.
Layer 4 is an Au layer. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
、Ａｕ層を順次積層した金属配線を備えたことを特徴と
する半導体装置。1. A semiconductor device comprising a metal wiring in which at least a Mo layer, a Ti layer, and an Au layer serving as a barrier metal are sequentially laminated on a substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16284088A JPH0210871A (en) | 1988-06-29 | 1988-06-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16284088A JPH0210871A (en) | 1988-06-29 | 1988-06-29 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0210871A true JPH0210871A (en) | 1990-01-16 |
Family
ID=15762244
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16284088A Pending JPH0210871A (en) | 1988-06-29 | 1988-06-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0210871A (en) |
-
1988
- 1988-06-29 JP JP16284088A patent/JPH0210871A/en active Pending
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