JPH0210746A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PURPOSE:To elevate the operation noise allowance of a circuit by forming first, second and third semiconductor layers on a substrate, and forming the first and the second semiconductor devices on the second and the third semiconductor layers after selectively removing a part of the third semiconductor layer. CONSTITUTION:A first N-type semiconductor layer 2 of high impurity density having the electron affinity greater than a second semiconductor layer 3, the second semiconductor layer 3 of low impurity density, and a third semiconductor layer 4 of low impurity density are made to crystal-grow in order on a semiinsulating substrate 9, and the third semiconductor layer 4 of a part of the crystals is selectively removed, and a control electrode 6 and plural ohmic electrodes 5 connected electrically with the first semiconductor layer 2 are provided on the second semiconductor layer 3 at the removed part so as to form the first semiconductor device. Also, a control electrode 7 and plural ohmic electrodes 5 connected electrically with the first semiconductor layer 2 are provided on the third semiconductor layer 4 except the removed part so as to form the second semiconductor device. By this constitution, the apparent Schottky barrier becomes high, and the operation noise allowance of an integrated circuit is elevated.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an ultra-high speed and low power consumption semiconductor integrated device and a method for manufacturing the same.

(Prior Art) In recent years, from the viewpoint of speeding up, research and development of integrated circuits using compound semiconductors such as GaAs have been actively conducted. In general, enhancement mode FETs (E-F
ET) and depletion mode FET (D-FE
A so-called E/D configuration DCFL (
Direct Coupled FET Logic)
It is known that it has low power consumption, is suitable for high integration, and is fast. In fact, GaAs MESFET
Technological developments are actively being carried out to realize this DCFL circuit using . However, since the conventional GaAs MESFET has a relatively low Schottky barrier height of approximately 0.75V, there is a problem in that the circuit cannot actually have sufficient operating noise margin. Furthermore, since ion implantation is generally used to form E-FETs and D-FETs, there are large variations in threshold voltage, and there is also the problem that the circuit does not have sufficient operating noise margin.

(Problems to be Solved by the Invention) An object of the present invention is to solve such problems and provide an ultra-high speed, low power consumption semiconductor integrated device having a sufficiently large circuit operating noise margin, and a method for manufacturing the same. It's about doing.

(Means for solving the problem) The present invention has a second semiconductor layer with a low impurity density provided on a first semiconductor layer with a high impurity density, and the first semiconductor layer is of N type. a control electrode having a larger electron affinity than the second semiconductor layer and provided on the second semiconductor layer;
a first semiconductor device comprising at least two ohmic electrodes electrically connected to the first semiconductor layer on both sides of the control electrode; A third semiconductor layer with a low impurity density provided on the semiconductor layer, a control electrode provided on the third semiconductor layer, and the first semiconductor layer on both sides of the control electrode. The present invention provides a semiconductor integrated device characterized in that a second semiconductor device including at least two electrically connected ohmic electrodes is provided on the same substrate.

Furthermore, if the first semiconductor layer is a P-type semiconductor having a sum of electron affinity and energy gap smaller than the sum of electron affinity and energy gap of the second semiconductor layer, a semiconductor integrated device using holes as carriers can be used. is obtained.

In the semiconductor integrated device described above, if part of the third semiconductor layer with a low impurity density is made of the same conductivity type as the first semiconductor layer, the characteristics of the device are improved as described later.

In order to manufacture the above semiconductor device, a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer are sequentially crystal-grown on a substrate, and a third semiconductor layer of a part of the crystal is grown. and forming a first semiconductor device on a second semiconductor layer in the removed portion, and forming a second semiconductor device on a third semiconductor layer other than the removed portion. All you have to do is

(Function) The basic semiconductor element in the semiconductor integrated device of the present invention is:
As shown in Japanese Patent Application No. 61-052873 and Japanese Patent Application No. 61-092639 filed by the present inventors, a semiconductor material including a Peter junction between the control electrode and the channel and directly under the control electrode Since it has a high resistance in principle, the operation mode can have both a depletion layer modulation mode and a charge accumulation mode. Therefore, the amount of channel charge that can be controlled can be increased, the current driving capability of the device is improved, and as a result, the speed of the device can be increased. In addition, the current rise voltage (Vr) between the control electrode and the ohmic electrode is high, and therefore the apparent Schottky barrier becomes high, for example, D
The operating noise margin of an integrated circuit using a CFL circuit or the like can be increased. Furthermore, since the channel aspect ratio can be increased, a high-performance short channel device can be easily realized. The semiconductor integrated device of the present invention uses the fact that, in principle, the current threshold voltage of the element can be controlled by increasing or decreasing the thickness of the high-resistance semiconductor layer on the surface of the element. The integration of depletion type elements can provide unique functions and effects. Further, in the case of the E/D configuration, it is also possible to add impurities to a part of the high-resistance semiconductor layer on the surface on the D-FET side to substantially increase the mutual conductance of the D-FET. The principle 0 action explained above is common to both electrons and holes as carriers.

Furthermore, in the manufacturing method of the present invention, epitaxially grown crystals with high uniformity are used, and the fifth semiconductor layer is selectively removed using a wet or dry etching method, so that variations in the threshold voltage of the device can be avoided. can also be made smaller. Therefore, for example, it is possible to easily form a DCFL circuit having an E/D configuration with extremely strict noise margin limitations, and to obtain a high-speed semiconductor integrated device with a high circuit operational noise margin.

(Example 1) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a cross-sectional view of a main part structure of a semiconductor integrated device according to an embodiment of the present invention. In FIG. 1, the semiconductor layer 1 on the semi-insulating substrate 9 is undoped GaAs, the first semiconductor layer 2 is N-type GaAs, and the second semiconductor layer 3 is undoped Alo, 3Gao, 7AS, and the third semiconductor layer 3. Undoped GaAs is used as the semiconductor layer 4, AuGe/Ni is used as the ohmic electrode 5, and WSi is used as the control electrodes 6 and 7, respectively. Further, the N-type high impurity density region 8 is S
The dose of i ions is about 5 x 1013 cm-2,
After ion implantation at an accelerating voltage of approximately 50 keV, 9
It is formed by short-time heat treatment at 00°C. Typical examples of the film thickness and impurity density of each semiconductor layer in this example are as follows: Graphical symbol Film thickness (A) Impurity density (X 101810l8 Undoped, undoped, undoped.E with the control electrode 6 in this example) -FE
Typical figures of merit of a D-FET having T and control electrode 7 are as follows: Figure of merit E-FET D-FETI,
g(llrri) 1 1V yield V) 0.2 -0.6gm(m
s/mm) 350 300Vr(V
) 1.15 1BY-■)8
It is 8. Here, Lg is the length of the control electrode (gate length),
Vt is threshold voltage, gm is mutual conductance, Vr
represents the gate forward rising voltage, and BVg represents the gate breakdown voltage. In particular, Vr is both about 1v, which is an improvement of about 0.4v compared to the conventional GaAs MESFET. Furthermore, the gate breakdown voltage is approximately twice that of the conventional GaAs MESFET. Furthermore, gm, which is an index of high speed of a semiconductor integrated device, was also sufficiently large.

Using the semiconductor integrated device of this example, an inverter with a DCFL circuit configuration and a ring oscillator using the same were fabricated. Power consumption 0.6mW
and obtained good results. Furthermore, the semiconductor integrated device according to the present invention operates well even at high temperatures around 100°C.
It has been found that the circuit has sufficient operating noise margin, is high-speed, and has low power consumption.

In this example, the N-type high impurity density region 8 was formed by ion implantation, but for example, the N-type high impurity density semiconductor layer ( For example, other methods such as selective epitaxial growth of N-GaAs can also be used.

(Embodiment 2) FIG. 2 is a cross-sectional view of the main part structure of a semiconductor integrated device according to another embodiment of the present invention. In FIG. 2, the semiconductor layer 21 on the semi-insulating substrate 9 is undoped GaAs, the semiconductor layer 22 is undoped Alo, 3Gao, 7As, the semiconductor layer 23 is undoped GaAs, and the first semiconductor layer 2 is N-type GaAs. GaAs, undoped AIo3Gao as second semiconductor layer 3, 7As, third semiconductor layer 4
Of these, 24 is N-type GaAs, 25 is undoped GaAs, and ohmic electrode 5 is AuGe/Ni.
, WSi is used as the control electrodes 6 and 7, respectively. Furthermore, the N-type high impurity density region 8 has a Si ion dose of approximately 5×1013 cm−2 and an acceleration voltage of approximately 50 ke.
After ion implantation under the condition of V, the N-type intermediate impurity density region 26 has a Si ion dose of approximately I×101.
It is formed by ion implantation at 3 cm -2 and acceleration voltage of about 30 keV, followed by short-time heat treatment at 900°C. In addition, the film strength of each semiconductor layer in this example is
War (A) Impurity density (X 101810l8 Undoped undoped undoped undoped undoped. E-FE with control electrode 6 in this example
Typical figures of merit of a D-FET having T and control electrode 7 are as follows: Figure of merit Lg (pm) ■Ken■) gm (ms/mm) Vr (V) BVg (V) -FET 0.2 1. 15-FET 10,6 0.9. In this example, N on the D-FET side is
Since the type GaAs layer 24 is provided, the distance between the control electrode 7 and the channel layers 2 and 24 is shortened, and the gm of the D-FET is increased, which is advantageous for higher speed. Also,
N-type intermediate impurity density region 2 near control electrodes 6 and 7
6, so-called LDD (Lightly Dope
dDrain) structure, the gate breakdown voltage is also increased. Furthermore, since the hetero buffer layer 22 made of AlGaAs is provided, the short channel effect is small.
Good characteristics could be obtained even in devices with short channel lengths. Furthermore, using the semiconductor integrated device of this example,
When we created an inverter with a DCFL circuit configuration and a ring oscillator using it, we obtained good results with a noise margin of approximately 0.4 V, a gate delay time of 25 ps/s with no load, and a power consumption of 0.6 mW per gate. Ta. Also, 100°
The semiconductor integrated device according to the present invention operates well even at high temperatures near C, and has sufficient circuit operation noise margin,
Moreover, it was found to be high speed and low power consumption.

In the above embodiments, a semiconductor integrated device using electrons as carriers has been described, but the principle of the present invention is similarly applicable when holes are used as carriers. Next, an example of a semiconductor integrated device using holes as carriers will be described.

(Embodiment 3) A cross-sectional view of the main structure of the semiconductor integrated device of this embodiment is the same as that in FIG. In FIG. 1, the semiconductor layer 1 on the semi-insulating substrate 9 is undoped GaAs, the first semiconductor layer 2 is P-type Ge, the second semiconductor layer 3 is undoped Alo, 3Gao, 7As, and the third semiconductor layer 3. Undoped Ge as the semiconductor layer 4 and AuZn as the ohmic electrode 5
, WSi is used as the control electrodes 6 and 7, respectively. In addition, the P-type high impurity density region 8 has a Be ion dose of about 5 x 1013 cm-2 and an acceleration voltage of about 50 cm.
After ion implantation under keV conditions, it is formed by short-time heat treatment at 900°C. In addition, typical examples of the film thickness and impurity density of each semiconductor layer in this example are as follows: Graphical symbols: Moon tankyo (A) Impurity density (X I
Q"cm-3) 1 5000 Undoped 3250 Undoped 4250 Undoped. In this example as well, as in the case where electrons are used as carriers, in particular with respect to Vr, conventional GaAs MES
Improvement was seen compared to FET. It has also been found that the semiconductor integrated device according to the present invention has sufficient circuit operation noise margin, is high-speed, and has low power consumption.

Embodiment 3 is a pair with Embodiment 1 of a semiconductor integrated device using electrons as carriers, but if compared with the principle of the present invention, a semiconductor integrated device using hole carriers corresponding to Embodiment 2 is applicable. It is clear that this is possible.

In Examples 1 to 3 above, GaAs, Al
Although GaAs and Ge were used as semiconductor materials, InGa
As, InAlAs, InP, GaSb, InSb, S
It is also possible to use other semiconductor materials such as i.

Next, an embodiment of the method of manufacturing a semiconductor integrated device of the present invention will be described.

(Embodiment 4) FIGS. 3(a) to 3(C) show the main manufacturing steps of a method for manufacturing a semiconductor integrated device according to an embodiment of the present invention. FIG. 3(a) is a cross-sectional view of a semiconductor crystal. In Figure 3(a),
Undoped Ga as the semiconductor layer 1 on the semi-insulating substrate 9
As, N-type GaAs as the first semiconductor layer 2, undoped Alo, 5Gao, 5A as the second semiconductor layer 3
s, undoped GaAs as the third semiconductor layer 4,
Each layer is successively grown using a molecular beam epitaxial (MBE) method. Next, as shown in FIG. 3(b), D-
The region that will become the FET is masked with a photoresist (PR) 31 and dry etched with a mixed gas 32 of CCL2F2 and He to form the undoped GaAs of the third semiconductor layer 4.
is selectively removed to form a region that will become an E-FET.

Next, as shown in FIG. 3(c), after removing the PR, W
Si is deposited by sputtering and processed by dry etching. After that, Si ions 33 are added at a dose of about 5
After ion implantation at 1013 cm-2 and an acceleration voltage of about 50 keV, a short-time heat treatment at 900°C is performed.

Thereafter, AuGe/Ni is deposited as the ohmic electrode 5 and alloyed by heat treatment. Finally, wiring between the elements is completed. In addition, typical examples of the film thickness and impurity density of each semiconductor layer in this example are as follows: Graphical symbol Film thickness (A) Impurity density (X 10
18c10l8 5000 Undoped 3250 Undoped 4250 Undoped. The standard deviation σVt of the threshold voltage Vt of the device obtained in this example was about 20 mV, which was good.

Further, when a circuit was fabricated using the DCFL circuit configuration, good performance similar to that shown in Example 1 was confirmed. Furthermore, the uniformity and reproducibility of device characteristics were also good.

In this example, the dry etching gas 3
2, 0□, C12, CCl4. CBrF3. C.F.
4,5iC14°SF6. It is also possible to use a mixed gas consisting of a combination of gases such as HCl and HBr. Furthermore, tartaric acid, ammonium fluoride liquid, or the like may be used instead of the dry etching gas 32.

Furthermore, although this fourth embodiment is a method for manufacturing a semiconductor integrated device using electrons as carriers, in principle it can also be used as a method for manufacturing a semiconductor integrated device using holes as carriers when compared with the principles of the present invention. It is clear that the same is applicable.

(Effects of the Invention) As described above, according to the present invention, it is possible to realize a semiconductor integrated device that has a large circuit operating noise margin and is excellent in high speed and low power consumption. Furthermore, since the yield can be improved by a manufacturing method with good uniformity and reproducibility, it is also very effective in reducing costs.

[Brief explanation of the drawing]

1 and 2 are schematic structural cross-sectional views in an embodiment of the semiconductor integrated device of the present invention, and FIGS. FIG. 3 is a schematic cross-sectional view of the structure showing the manufacturing process. DESCRIPTION OF SYMBOLS 1... Undoped GaAs layer, 2... First semiconductor layer (N-type GaAs or P-type Ge), 3... Second semiconductor layer (undoped AIGaAs), 4... Third semiconductor layer (Undoped GaAs), 5... Ohmic electrode, 6, 7... Control electrode, 8... N-type high impurity density region, 9... Substrate, 21... Undoped GaA
s layer, 22-... undoped AlGaAs, 23-...
undoped GaAs, 24... third semiconductor layer (N-type GaAs or Ge), 25... third semiconductor layer (
undoped GaAs), 26... N-type intermediate impurity density region, 31... photoresist, 32... mixed gas for dry etching, 33... implanted ions.

Claims (4)

[Claims] (1) A second semiconductor layer with a low impurity density is provided on a first semiconductor layer with a high impurity density, and the first semiconductor layer is N-type and has a larger electron affinity than the second semiconductor layer. a control electrode provided on the second semiconductor layer; and at least two ohmic electrodes electrically connected to the first semiconductor layer on both sides of the control electrode. 1 semiconductor device, and the second semiconductor device on the first semiconductor layer.
a third semiconductor layer with a low impurity density provided on the semiconductor layer, a control electrode provided on the third semiconductor layer, and the first semiconductor layer on both sides of the control electrode. and a second semiconductor device including at least two electrically connected ohmic electrodes, provided on the same substrate. (2) In the semiconductor integrated device according to claim 1, the first semiconductor layer is a P type having a sum of electron affinity and energy gap smaller than the sum of electron affinity and energy gap of the second semiconductor layer. A semiconductor integrated device characterized by being a semiconductor. (3) In the semiconductor integrated device according to claims 1 and 2, an impurity of the same conductivity type as the first semiconductor layer is added to a part of the third semiconductor layer having a low impurity density. Features of semiconductor integrated devices. (4) A step of sequentially crystal-growing a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer on the substrate, and a step of selectively removing a portion of the third semiconductor layer from the crystal. and forming a first semiconductor device on the second semiconductor layer of the removed portion,
4. The method of manufacturing a semiconductor integrated device according to claim 1, further comprising the step of forming a second semiconductor device on a third semiconductor layer other than the removed portion.