JPH02105529A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02105529A JPH02105529A JP25851488A JP25851488A JPH02105529A JP H02105529 A JPH02105529 A JP H02105529A JP 25851488 A JP25851488 A JP 25851488A JP 25851488 A JP25851488 A JP 25851488A JP H02105529 A JPH02105529 A JP H02105529A
- Authority
- JP
- Japan
- Prior art keywords
- layer wiring
- silicon oxide
- oxide film
- hole
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 abstract description 8
- 239000002184 metal Substances 0.000 abstract description 8
- 238000000992 sputter etching Methods 0.000 abstract description 5
- 238000000206 photolithography Methods 0.000 abstract description 3
- 238000001312 dry etching Methods 0.000 abstract description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 23
- 230000000694 effects Effects 0.000 description 2
- 229910018949 PtAu Inorganic materials 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device.
従来、多層配線におけるそれぞれの配線の電気的接触は
、スルーホール構造が用いられている。Conventionally, a through-hole structure has been used for electrical contact between each wiring in a multilayer wiring.
第３図は従来の半導体装置の一例を説明するための半導
体チップの断面図である。第３図に示すように、半導体
基板１上に第１層配線１を形成した後、シリコン酸化膜
３を形成する。次に、第１層配線と電気的接触をとりた
い領域のシリコン酸化膜３を第１層配線に達するまでエ
ツチングすることにより、スルーホール７を形成する。FIG. 3 is a cross-sectional view of a semiconductor chip for explaining an example of a conventional semiconductor device. As shown in FIG. 3, after first layer wiring 1 is formed on semiconductor substrate 1, silicon oxide film 3 is formed. Next, a through hole 7 is formed by etching the silicon oxide film 3 in a region where it is desired to make electrical contact with the first layer wiring until it reaches the first layer wiring.
次に、第２層配線６をスルーホールを介して形成するこ
とにより、第１層配線２と第２層配線６との電気的接触
を行なっていた。Next, electrical contact between the first layer wiring 2 and the second layer wiring 6 was established by forming the second layer wiring 6 through a through hole.
上述した従来の半導体装置の製造方法では、第１層配線
２と第２層配線６のスルーホール７以外での電気的絶縁
を充分にとり、配線間の交差容量を押さえるために、シ
リコン酸化膜等の絶縁膜３の膜厚を厚く成長させるので
、スルーホール７の凹部段差が大きくなり、第２層配線
６のステップ・カバレジが悪くなる。これにより、第１
層配線２との接触抵抗の増大及び配線の断線等が発生す
る欠点があった。In the conventional semiconductor device manufacturing method described above, a silicon oxide film or the like is used to ensure sufficient electrical insulation between the first layer wiring 2 and the second layer wiring 6 other than the through hole 7, and to suppress cross capacitance between the wirings. Since the thickness of the insulating film 3 is grown thick, the step difference in the recessed portion of the through hole 7 becomes large, and the step coverage of the second layer wiring 6 deteriorates. This allows the first
There were drawbacks such as an increase in contact resistance with the layer wiring 2 and disconnection of the wiring.
本発明の目的は、第１層配線と第２層配線との電気的接
触において、第２層配線のステップ・カバレジを良くす
ることにより、接触抵抗を下げ、配線の段切れをなくす
ことができる半導体装置の製造方法を提供することにあ
る。An object of the present invention is to improve the step coverage of the second layer wiring in electrical contact between the first layer wiring and the second layer wiring, thereby reducing contact resistance and eliminating disconnections in the wiring. An object of the present invention is to provide a method for manufacturing a semiconductor device.
本発明の半導体装置の製造方法は、半導体基板上に第１
の配線を形成する工程と、前記第１の配線上に絶縁膜を
形成する工程と、前記絶縁膜に前記第１の配線に達する
開孔部を形成する工程と、基板全面にシリコン酸化膜を
形成する工程と、前記開孔部の側壁部以外の前記シリコ
ン酸化膜を除去する工程と、前記開孔部上に第２の配線
を形成する工程とを含んで構成される。In the method for manufacturing a semiconductor device of the present invention, a first
forming an insulating film on the first wiring; forming an opening in the insulating film to reach the first wiring; and forming a silicon oxide film on the entire surface of the substrate. The method includes a step of forming a second wiring, a step of removing the silicon oxide film other than a side wall portion of the opening, and a step of forming a second wiring on the opening.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｅ）は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図である。第１
図（ａ）に示すように、半導体基板１上にタングステン
シリサイドを全面にスパッタした後、第１層配線２を形
成する領域をレジストで覆い、ドライエツチングを行う
ことにより第１層配線２を形成する。次に、基板全面に
シリコン酸化膜３を形成して、更にＴｉの金属膜４を蒸
着する。次に、第１図（ｂ）に示すように、スルーホー
ル開孔用のレジストを形成し、金属膜４及びシリコン酸
化膜３をイオンエツチングすることにより、スルーホー
ル７を形成する０次に、第１図（ｃ）に示すように、基
板全面にシリコン酸化膜５を形成する０次に、第１図（
ｄ）に示すように、イオンエツチングによりスルーホー
ル側壁部以外のシリコン酸化膜５を除去する。これによ
り、スルーホール７の段部がなめらかになる。次に、第
１図（ｅ）に示すように、金属膜４をイオンエツチング
により除去した後、Ｔｉ−ＰｔＡｕを全面にスパッタし
て、写真蝕刻法により、第２層配線６を形成し、第１層
配線２と第２層配線６との電気的接触を行なう。FIGS. 1A to 1E are cross-sectional views of a semiconductor chip shown in order of steps for explaining an embodiment of the present invention. 1st
As shown in Figure (a), after sputtering tungsten silicide over the entire surface of the semiconductor substrate 1, the area where the first layer wiring 2 is to be formed is covered with resist, and dry etching is performed to form the first layer wiring 2. do. Next, a silicon oxide film 3 is formed on the entire surface of the substrate, and a Ti metal film 4 is further deposited. Next, as shown in FIG. 1(b), a resist for opening a through hole is formed, and the metal film 4 and silicon oxide film 3 are ion-etched to form a through hole 7. As shown in FIG. 1(c), a silicon oxide film 5 is formed on the entire surface of the substrate.
As shown in d), the silicon oxide film 5 other than the side wall portion of the through hole is removed by ion etching. This makes the stepped portion of the through hole 7 smooth. Next, as shown in FIG. 1(e), after removing the metal film 4 by ion etching, Ti-PtAu is sputtered on the entire surface, and a second layer wiring 6 is formed by photolithography. Electrical contact is made between the first layer wiring 2 and the second layer wiring 6.
第２図（ａ）〜（ｄ）は本発明の詳細な説明するための
工程順に示した半導体チップの断面図である。第２図（
ａ）に示すように、半導体基板１上にシリコン酸化膜３
を形成し、次に、ＴＬの金属膜４を蒸着する。次に、第
２図（ｂ）に示すように、基板全面にシリコン酸化膜３
を形成する。次に、第２図（Ｃ）に示すように、段差部
以外のシリコン酸化膜５を除去する。これにより、段差
部がなめらかになる。次に、第２図（ｄ）に示すように
、金属膜４をイオンエツチングにより除去した後、Ｔｉ
−Ｐｔ−Ａｕを全面にスパッタして、写真蝕刻法により
、配線６を形成する。FIGS. 2(a) to 2(d) are cross-sectional views of a semiconductor chip shown in order of steps to explain the present invention in detail. Figure 2 (
As shown in a), a silicon oxide film 3 is formed on a semiconductor substrate 1.
is formed, and then a metal film 4 of the TL is deposited. Next, as shown in FIG. 2(b), a silicon oxide film 3 is formed on the entire surface of the substrate.
form. Next, as shown in FIG. 2(C), the silicon oxide film 5 other than the stepped portion is removed. This makes the stepped portion smooth. Next, as shown in FIG. 2(d), after removing the metal film 4 by ion etching, the Ti
-Pt--Au is sputtered over the entire surface and the wiring 6 is formed by photolithography.
以上説明したように、本発明は、スルーホール側壁部に
シリコン酸化膜を残すことにより、スルーホール７の段
部をなめらかにすることができ、第１層配線と第２層配
線とをスルーホールにより電気的接触する場合、第２層
配線のステップ・カバレジが良くなり、接触抵抗を下げ
、配線の段切れをなくすことができる効果がある。As explained above, in the present invention, by leaving a silicon oxide film on the side wall of the through hole, the stepped portion of the through hole 7 can be made smooth, and the first layer wiring and the second layer wiring can be connected through the through hole. When electrical contact is made, the step coverage of the second layer wiring is improved, the contact resistance is reduced, and there is an effect that disconnections in the wiring can be eliminated.
第１図（ａ）〜（ｅ）は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図、第２図（ａ
）〜（ｄ）は本発明の詳細な説明するための工程順に示
した半導体チップの断面図、第３図は従来の半導体装置
の一例を説明するための半導体チップの断面図である。
１・・・半導体基板、２・・・第１層配線、３・・・シ
リコン酸化膜、４・・・金属薄膜、５・・・シリコン酸
化膜、６・・・第２層配線、７・・・スルーホール。1(a) to 1(e) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention, and FIG. 2(a)
) to (d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the present invention in detail, and FIG. 3 is a cross-sectional view of a semiconductor chip for explaining an example of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... First layer wiring, 3... Silicon oxide film, 4... Metal thin film, 5... Silicon oxide film, 6... Second layer wiring, 7... ...Through hole.
Claims (1)
の配線上に絶縁膜を形成する工程と、前記絶縁膜に前記
第１の配線に達する開孔部を形成する工程と、基板全面
にシリコン酸化膜を形成する工程と、前記開孔部の側壁
部以外の前記シリコン酸化膜を除去する工程と、前記開
孔部上に第２の配線を形成する工程とを含むことを特徴
とする半導体装置の製造方法。a step of forming a first wiring on a semiconductor substrate;
a step of forming an insulating film on the wiring, a step of forming an opening in the insulating film reaching the first wiring, a step of forming a silicon oxide film on the entire surface of the substrate, and a step of forming a silicon oxide film on the sidewall of the opening. A method for manufacturing a semiconductor device, comprising the steps of: removing the silicon oxide film other than the opening; and forming a second wiring over the opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25851488A JPH02105529A (en) | 1988-10-14 | 1988-10-14 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25851488A JPH02105529A (en) | 1988-10-14 | 1988-10-14 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02105529A true JPH02105529A (en) | 1990-04-18 |
Family
ID=17321268
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25851488A Pending JPH02105529A (en) | 1988-10-14 | 1988-10-14 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02105529A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5498572A (en) * | 1993-06-25 | 1996-03-12 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing semiconductor device |
-
1988
- 1988-10-14 JP JP25851488A patent/JPH02105529A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5498572A (en) * | 1993-06-25 | 1996-03-12 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing semiconductor device |
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