JPH0199138A - Information history storage - Google Patents

Abstract

PURPOSE:To prevent the condition information from being lost without increasing a hardware by being equipped with an information history storing means to switch and control the internal storing area of an information history storing means. CONSTITUTION:When an abnormality occurs at a system, by an abnormality detecting signal from respective devices 1-6 excluding an information history memory device 7, an information history memory control circuit 21 changes over a writing address circuit 16 to a second memory area of an information history memory circuit 18 and continues to store the condition information from a common bus 10 to a signal line 12. For an information history memory reading circuit 24, an information history signal is read and sent onto a signal line 29 from the memory area of the information history memory circuit 18 designated by a reading signal on a signal line 25, a reading selecting signal on a signal line 26 and a reading address signal from a reading address circuit 27 onto a signal line 28. Thus, when the abnormality occurs at the system, the condition information of the common bus during the reading can be traced and therefore, the condition history information during this is not lost.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an information history storage device connected to an arithmetic processing unit via a common bus, and in particular to a control method for collecting information history on a common bus when a failure occurs. Regarding.

(Prior Art) Conventionally, in this type of information history storage device, when a failure occurs in the system, writing of information to the information history storage device is stopped and history information is collected, or information history storage is stopped. The device was configured to have dual buffers for storing internal state information, so that when one buffer stopped, the state information was stored in the other buffer.

(Problems to be Solved by the Invention) In the conventional information history storage device described above, when a failure occurs in the system, writing of status information from the common bus is stopped, and status information is collected by reading the history information. was. In such a case, writing of status information on the common bus is prohibited while history information is being collected, so there is a drawback that the status information will be lost.

Furthermore, duplication of the buffer serving as the state information storage means has the disadvantage of increasing hardware and complicating control.

An object of the present invention is to provide an information history storage means that stores state information of a common bus and can read it out asynchronously with writing of the state information, and to write/read by specifying a storage area inside the information history storage means. To provide an information history storage device which eliminates the above-mentioned drawbacks and is configured so that the hardware is not increased and the state information is not lost by executing the switching management of the state information. The information history storage device according to the present invention includes a plurality of arithmetic processing units,
It is configured by connecting multiple main storage devices and multiple input/output control devices to a common bus.

The information history storage device according to the present invention includes information history storage means;
The apparatus is comprised of information history storage/writing means, write address holding means, information history storage/management means, information history storage/reading means, and readout address holding means.

The information history storage means stores state information of the common bus and is capable of reading out the state information asynchronously with writing of the state information.

The information history storage and writing means is for writing status information into the information history storage means.

The write address holding means is for specifying an internal storage area of the information history storage means.

The information history storage management means is for switching and managing the storage areas.

The information history storage/reading means is for reading the status information stored in the information history storage means.

The read address holding means is for specifying the storage area where the state information is stored.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a system using an information history storage device according to the present invention.

In FIG. 1, 1 and 2 are arithmetic processing units, 3,
4 is a main storage device, 5 and 6 are input/output control devices, 7 is an information history storage device, and 8 is a common bus, and each device is connected to the common bus 8.

FIG. 2 is a block diagram showing an embodiment of the information history storage device according to the present invention. In FIG. 2, 10 is a common bus, 11 is an information history storage device, 13 is an information history storage write circuit, 16 is a write address circuit, 1B is an information history storage circuit, 21 is an information history storage management circuit, and 22 is an abnormality detection circuit. 24 is an information history storage/readout circuit; 2T is a readout address circuit;

In FIG. 2, the information history storage device 11 is connected to a common bus 10.
There is a connection type. An information history storage circuit specified by a write enable signal from the information history storage write circuit 13 on the signal line 14, a write selection signal on the signal line 15, and a write address signal from the write address circuit 16 on the signal a1r. Common bus 1o for 18 storage areas
Status information from the signal 1s12 to the signal 1s12 is stored. A write address control signal is transmitted from the information history storage/write circuit 13 to the write address circuit 16 via the signal line 19, and +1 is added to the write address signal on the signal line 1T.

FIG. 3 is a conceptual diagram showing a storage area of the information history storage circuit 18 shown in FIG. The information history storage circuit 18 has the first to nth
It consists of storage areas, and each area has a start address and an end address defined.

When an abnormality occurs in the system, the information history storage management circuit 21 receives an abnormality detection signal from each device other than the information history storage device T shown in FIG. The write address circuit 16 is switched to the storage area No. 2, and storage of status information from the common bus 10 to the signal line 12 is continued. At this time, the abnormality detection holding register 22 indicates that the information history is stored in the first storage area.
to hold.

On the other hand, in response to the history information read request signal on the signal line 23, the information history storage/read circuit 24 receives the read signal on the signal line 25, the read selection signal on the signal line 26, and the signal ! from the read address circuit 2T. The information history signal is read out from the storage area of the information history storage circuit 18 designated by the read address signal onto the 2B and sent onto the signal line 29. The information history storage/readout circuit 24 reads out a readout address control signal via the signal line 30 and outputs the readout address control signal to the readout address circuit 27 .
When the read address signal on signal line 28 is sent to +
Only 1 is added.

Before starting reading, the reading start/end address is sent from the information history storage management circuit 21 according to the abnormality detection and holding circuit 22.
The data is stored in the read address circuit 27 by the read control signal on the signal line 31. When the readout of the information history at the readout end address is completed, the readout address circuit z7 transmits a readout completion signal to the information history storage management circuit 21 via the signal line 32, and reads the information history held in the abnormality detection and holding circuit 22. Release the hold.

If an abnormality is detected while tracing the state information of the common bus using the final storage area, the information history storage management circuit 21 returns to the first storage area and continues tracing.

(Effects of the Invention) As described above, the present invention includes an information history storage means that stores state information of a common bus and can read out the state information asynchronously with writing of the state information, and stores information inside the information history storage means. By specifying areas for writing/reading and managing state information switching, information can be saved when an error occurs in a system configured using multiple information processing devices connected to a common bus. Since the status information stored in the information history storage means can be read without stopping the tracing of the history storage device, and the status information of the common bus that is being read can be traced, the status history information during this time can be It has the effect of not being lost.

Another advantage is that an increase in the amount of hardware can be minimized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating one embodiment of a system using an information history storage device according to the present invention. FIG. 2 is a block diagram showing an embodiment of the information history storage device according to the present invention. FIG. 3 is a conceptual diagram showing a storage area of the information history storage circuit of FIG. 2. 1.2... Arithmetic processing unit 3.4... Main storage device 5.6... Input/output control device 7.11... Information history storage device 8.10... Common bus 13... Information history storage and writing circuit 16...Write address circuit 18...Information history storage circuit 21...Information history storage management circuit 22...Abnormality detection and holding circuit 24...Information history storage and readout circuit 27... Read address circuit 12.14, 15, 17, 19, 20, 23°25.2
6,28-32...Signal line patent applicant NEC Co., Ltd. agent Patent attorney Inoro Jusai 1 @ Piece 2 figure') r'3 [:a

Claims (1)

[Claims] information history storage means for storing state information of a common bus and capable of reading out asynchronously with writing of the state information; information history storage and writing means for writing the state information in the information history storage means; write address holding means for specifying a storage area within the information history storage means; information history storage management means for switching and managing the storage area; and the status information stored in the information history storage means. information history storage/reading means for reading out the state information; and readout address holding means for specifying the storage area in which the state information is stored; An information history storage device configured to be commonly connected to the common bus together with an input/output control device.