JPH0198198A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce consumption power and to attain a low voltage action by constituting a program circuit by means of the serial circuit of a fuse element, an MOSFET and a resistance circuit element. CONSTITUTION:At the time of selecting chips when the fuse element 1 is not disconnected, a contact point A shows '1' by the resistant rate of the element 1, the P channel MOSFET 2 and the high resistant element 3, and an output OUT shows '0'. At the time of the non-selection of the chips, the FET 2 is turned off, the point A shows '0', and the output OUT shows '1'. When the element 1 is disconnected, the point A shows '0' by the high resistant element 3 irrespective of the selection and non-selection of the chips, and '1' is outputted in the OUT.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to semiconductor memory, and in particular, to a semiconductor memory having a redundancy function that replaces a defective memory cell with a spare memory cell when a defect occurs in a normal memory cell. The present invention relates to a semiconductor memory provided with a semiconductor memory.

[Conventional technology]

Traditionally, semiconductor memory consists of regular memory cells and spare memory cells.
Some memory cells are manufactured on the same chip, and have a redundancy function in which if a defective normal memory cell occurs during manufacturing, it is replaced with the spare memory cell for relief.

This redundant function consists of multiple units (
For example, even if one memory cell out of approximately 64,000 memory cells is defective and all the other memory cells are good, the product will still be defective. This is a function to improve retention. The probability that a product will fail due to one or a few such defective memory cells increases as memory capacity increases. Therefore,
If such defective products are replaced with spare memory cells instead of being discarded, manufacturing yields can be improved and product costs can be reduced.

By the way, in a semiconductor memory equipped with such a redundant function, regular memory cells are used as spare memory.

A spare memory cell selection circuit is required to replace the defective memory cell and select a spare memory cell in place of the defective memory cell. In particular, the spare memory cell selection circuit includes a programming circuit including a fuse element or the like for programming the address of a defective memory cell.

FIG. 4 is a diagram of a spare memory cell selection circuit in a conventional semiconductor memory.

As shown in FIG. 4, in such a selection circuit 1, an address signal switch circuit 13 composed of a transfer gate is used to convert the output of a program circuit 11 and its output into an inverter signal obtained through an inverter 12.
is driven, and the desired address information 15 is sent to the preliminary decoder 1.
6 input. On the other hand, a spare decoder enable signal 14 is also supplied from the program circuit 11 to select the spare decoder 16 and replace the defective memory cell with the spare memory cell.

FIG. 5 is a specific circuit diagram showing an example of the program circuit in FIG. 4.

As shown in FIG.
A fuse element 1 and a resistor 3 are connected in series between the fuse element 1 and the ground, and the output OUT is taken out from their connection point. In this programming circuit, programming is performed depending on whether or not fuse element 1 is blown, so if the ratio of the resistance values between fuse element 1 and resistor 3 is sufficiently small, the output OUT will be 11" before blowing, and 00″ after cutting
I'm trying to make it happen.

Next, FIG. 6 is a specific circuit diagram showing another example of the program circuit, similar to FIG. 5.

As shown in FIG. 6, this program circuit
and ground, a fuse element 1 and an N-channel WMOS transistor 2' whose source electrode is grounded and whose gate electrode is connected to a reset signal PR are connected in series,
Also, one of the clip-flops 5, which is composed of two CMOS inverters 4 and 4' connected in opposite directions, connects the fuse element 1 and the NMO transistor 2' at the connection point C.
The reset signal PR used here is connected to the output terminal OUT, and the other end is connected to the output terminal OUT, so that the program output is taken out from the output terminal OUT.

This is a pulse signal generated by sensing the rising edge and falling edge of 0.

In such a program circuit, since the reset signal PR is a pulse signal that is generated by sensing the rise and fall of the power supply, if the fuse element 1 is not disconnected, the output terminal OUT will show that PR is at the @"0" level. After returning to (after the power is turned on), the fuse element 1 and the 7-lip/70-tube 5 output a signal @02 level and hold this information. On the other hand, if fuse element 1 is blown, PR
Since the signal connection point C is set to ground potential, flip
The flop 5 fixes the output OUT to @1'' level and holds this information.

[Problem that the invention seeks to solve]

The above-described first conventional programming circuit (FIG. 5) has a drawback in that, if the fuse element is not blown, direct current flows from the power supply through the fuse element toward ground.

In addition, since the second program circuit (Fig. 6) uses a pulse signal PR that is generated by sensing the rise and fall of the power supply, operation at a low power supply (low voltage) is performed by the PR signal. The disadvantage is that it is regulated. That is, the reset signal PR is within a certain voltage range (for example, between Ov and 3V).
Since it is designed to look like a pulse signal generated by , if the voltage reaches a certain voltage below 3V, it will remain in the @1# state.

An object of the present invention is to provide a semiconductor memory that enables low consumption and low voltage operation as described above.

[Means for solving problems]

The present invention provides a regular memory cell and a spare memory cell on the same chip, and provides information necessary to replace the defective memory cell with the spare memory cell when a defect occurs in the normal memory cell. In a semiconductor memory equipped with a program circuit for storing , the program circuit is configured by connecting in series a fuse element, an M08 transistor whose gate electrode receives a signal generated from a chip enable signal, and a resistor circuit element. Ru.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a programming circuit diagram of a semiconductor memory showing a first embodiment of the present invention.

As shown in FIG. 1, this program circuit has a power supply vc
A signal made from a chip select signal (U]) is input to the gate electrode of a heater element 1, one of which is connected to VCC, and the ground, and the drain is connected to the heater element 1. A connected P-channel MOS transistor 2 and a transistor 2 (one of which is grounded and the other is a MOS transistor)
A high resistance element (for example, several MΩ) connected to the source Km 3
are connected in series. On the other hand, this program circuit connects a clip-flop 5 consisting of AK CMOS inverters 4 and 4' at the connection point between the P-channel fiMO transistor 2 and the high resistance element 3, and the output OUT is taken out. Furthermore, C8' generated from the chip select signal n
The signal is 1# when the chips are not selected together.

This is a signal that becomes 10'' when both are selected.

In the above-mentioned program circuit, when the toe element 1 is not disconnected and the chips are randomly selected (in other words,
When the C8' signal is @0#), the Hiez element 1. P-channel MOS transistor 2. The resistance ratio of high resistance element 3 is 11", and the output 0UTK is "0".
is output. Also, when chip is not selected, P channel M
O8) Since transistor 2 is turned off, the connection black is 1o
”, @1# is output to the output OUT.In other words, this state is a state in which programming has been performed, but since the chip is in a non-defective state, there is a high risk of malfunction. , when the heating element 1 is disconnected, whether the chip is in the competitive or non-competitive state, the high resistance element 3 will not connect the black wire to "O", so the output OUT will have "1#". is output.

FIG. 2 is a waveform diagram showing the input/output voltage characteristics of the program circuit in FIG. 1.

As mentioned above, in the program circuit that does not disconnect the Hiez element 1, each time the chip selects g or mouse, the output OUT is
It changes from 0" to @1" and from @1' to 10",
As shown in the timing chart in Figure 2, the timing when the chip changes from non-select to select is designed so that the address information Ai, Ai' is output to the output OUT before the switch changes. If you do this, it will not malfunction.

In this way, according to this embodiment, regardless of the presence or absence of the Hiez element, if the chip is not selected, it is not necessary to flow a direct current of ゛ from the power supply, and it is possible to achieve low power consumption of the program circuit. . Also, even when selecting chips,
Since a high resistance element is used, direct current can be ignored. Furthermore, since this embodiment does not require a reset signal, low voltage operation is possible.

FIG. 3 is a programming circuit diagram of a semiconductor memory showing a second embodiment of the present invention.

As shown in FIG.
A high-resistance element 3 whose one end is connected to vccK between cc and ground, and an N-channel MOS whose gate electrode receives a C12 signal generated from a chip select signal C8 and whose drain is connected to the high-resistance element 3. ) The transistor 2' and the Hiase element 1, one of which is grounded and the other connected to the transistor 2/, are connected in series, and the 7-lip flop 5 is connected to the connection point B as in FIG. . Here, signal C8' generated from chip select signal C8
is a signal that becomes 1cm0' when the chip is not selected, and becomes @''1' when the chip is selected.

The operation of such a program circuit is omitted because the logic is reversed to that in FIG. 1, but as in FIG. 1, when the chip changes from unselected to selected, address information A The circuit is designed so that the output OUT is output first before 'vAs' changes.

Similar to the first embodiment described above, this embodiment also uses a reset signal frequently, so that operation with a low voltage power supply is not restricted and operation with a low voltage is possible. Additionally, lower power consumption of the program circuit can be achieved in the same way.

In the above-described embodiments, an example in which only a resistor element is used as a resistor circuit element has been described, but in addition to this, a resistor circuit made up of transistors, etc. can be similarly used.

〔Effect of the invention〕

As explained above, in the semiconductor memory of the present invention, a program circuit is configured by a series connection circuit of a fuse element, a MOS transistor whose gate electrode receives a signal generated from a chip enable signal, and a resistor circuit element. However, regardless of whether the fuse element is disconnected or not, if the chip is not selected, the direct current from the power supply can be eliminated. Also, when selecting a chip, a DC current flows, but in order to make the resistance circuit element high in resistance (assuming that the current consumed by the programming circuit is on the order of μ), if this DC current is ignored, tl is 7. (Conventionally, the current during chip selection is on the order of fn people). Therefore, the present invention has the advantage that it is possible to realize a program circuit with extremely low power consumption.

Furthermore, since the present invention does not use a reset signal that was necessary in the past, operation with a low voltage power supply is not restricted. In other words, the present invention has the effect that it is possible to operate with a lower voltage than in the past. There is.

[Brief Description of the Drawings] Fig. 1 is a programming circuit diagram of a semiconductor memory showing a first embodiment of the present invention, Fig. 2 is a waveform diagram showing input and output voltages of the programming circuit in Fig. 1, and Fig. 3 4 is a programming circuit diagram of a semiconductor memory showing a second embodiment of the present invention, FIG. 4 is a spare memory cell selection circuit diagram of a conventional semiconductor memory, and FIGS. It is a program circuit diagram. 1...Fuse element, 2...P channel type MO8
Transistor, 2'...N-channel mMOS transistor, 3...High resistance element, 4.4'...CMOS
Inverter S5...Flip-flop. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] A program that includes a regular memory cell and a spare memory cell on the same chip, and stores information necessary for replacing the defective memory cell with the spare memory cell when a defect occurs in the regular memory cell. In the semiconductor memory equipped with a circuit, the program circuit is configured by connecting in series a fuse element, a MOS transistor whose gate electrode receives a signal generated from a chip enable signal, and a resistor circuit element. A semiconductor memory characterized by