JPH0196954A - Resistance trimming method for semiconductor integrated circuits - Google Patents
Resistance trimming method for semiconductor integrated circuitsInfo
- Publication number
- JPH0196954A JPH0196954A JP62255963A JP25596387A JPH0196954A JP H0196954 A JPH0196954 A JP H0196954A JP 62255963 A JP62255963 A JP 62255963A JP 25596387 A JP25596387 A JP 25596387A JP H0196954 A JPH0196954 A JP H0196954A
- Authority
- JP
- Japan
- Prior art keywords
- resistance
- resistance value
- semiconductor integrated
- metal wiring
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
- H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
- H10D84/209—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only resistors
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体基板上に形成された半導体集積回路の
抵抗トリミング方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for trimming the resistance of a semiconductor integrated circuit formed on a semiconductor substrate.
（従来の技術〕
従来の半導体集積回路の抵抗トリミング方法について第
４図をもとに説明する。第４図は従来の抵抗トリミング
方法によりトリミングが施された半導体集積回路の部分
平面図である。同図において、１８〜１ｅは抵抗領域で
あり、これら抵抗領域１ａ〜１ｅは一直線上に配置され
るとともに、接合端子２を介して直列接続用配線３によ
り直列に接続されている。また、トリミング前には抵抗
値１ａｉｂ〜１ｅはそれぞれ接合端子２を介して短絡用
金属配線４ｂ〜４ｅにより短絡されており、したがって
同図に示した区１７ｊｌＹ−Ｙのトリミング前の合成抵
抗値は抵抗領域１ａのみによる抵抗値となる。この抵抗
領域１ａの抵抗値は本来、設計上この区間Ｙ−Ｙで得よ
うとしている抵抗値（以下「設計値」という）よりもは
るかに小さなものに設定されており、また抵抗領域１ａ
〜１ｅの抵抗値の総和は、設計値に比してかなり大きく
設定されている。(Prior Art) A conventional resistor trimming method for a semiconductor integrated circuit will be described with reference to FIG. 4. FIG. 4 is a partial plan view of a semiconductor integrated circuit trimmed by the conventional resistor trimming method. In the figure, 18 to 1e are resistance regions, and these resistance regions 1a to 1e are arranged in a straight line and are connected in series by a series connection wiring 3 via a bonding terminal 2. Previously, the resistance values 1aib to 1e were short-circuited by the short-circuiting metal wirings 4b to 4e via the bonding terminals 2, respectively, so the combined resistance value before trimming of the section 17jlY-Y shown in the same figure is the resistance area 1a. The resistance value of this resistance region 1a is originally set to be much smaller than the resistance value (hereinafter referred to as "design value") that is intended to be obtained in this section Y-Y in design. , and the resistance region 1a
The sum of the resistance values of ~1e is set to be considerably larger than the design value.
次に、区間Ｙ−Ｙの合成抵抗値が設ａｉ値となるように
抵抗トリミングを行なう手順について説明する。まず最
初に、区間Ｙ−Ｙの合成抵抗値もしくはこの区間Ｙ−Ｙ
の合成抵抗と関わりを持ちこの区間Ｙ−Ｙを含む半導体
集積回路の電気的特性を測定し、その測定結果により短
絡用金属配線４ｂ〜４Ｃのうち適当な抵抗値をもつ短絡
用金属配線をレーザーにより溶断して断線さける。この
ような一連の操作により区間Ｙ−Ｙにおける合成抵抗値
はレーザーにより溶断された短絡用金属配線に対応する
抵抗領域の抵抗値が加すされたものとなる。例えば、第
４図においては、短絡用金属配線４ｄ、４ｅが溶断され
ているので、区間Ｙ−Ｙにおける合成抵抗値は抵抗領域
１ａ、１ｄ、１ｅのそれぞれの抵抗値を加算したものと
なる。Next, a procedure for performing resistance trimming so that the combined resistance value of the section Y-Y becomes the set ai value will be described. First, the combined resistance value of the interval Y-Y or this interval Y-Y
The electrical characteristics of the semiconductor integrated circuit including this section Y-Y are measured in relation to the combined resistance of Avoid melting and disconnection. By performing such a series of operations, the combined resistance value in the section Y-Y is obtained by adding the resistance value of the resistance region corresponding to the shorting metal wiring cut by the laser. For example, in FIG. 4, the shorting metal wirings 4d and 4e are fused, so the combined resistance value in the section Y-Y is the sum of the resistance values of the resistance regions 1a, 1d, and 1e.
〔発明が解決しようとする問題点〕
従来の抵抗トリミング方法は、以上のように短絡用金属
配線４ｂ〜４ｅを溶断して区間Ｙ−Ｙにお【ノる合成抵
抗値が設甜値となるように調整していたため、合成抵抗
ｊ直を増大する方向にしか調整作業を行なえず、そのた
め合成ＩＩ（抗値が設訂（１「Ｉを上回らないように合
成抵抗値等の測定Ｊ３よび短絡用金属配線の溶断という
一連の手順を数多く繰り返して行う必要があり、トリミ
ングにかなりの時間を要するという問題があった。[Problems to be Solved by the Invention] In the conventional resistance trimming method, as described above, the shorting metal wirings 4b to 4e are fused and the combined resistance value in the section Y-Y becomes the set value. Because the adjustment was made in the same way, it was only possible to make adjustments in the direction of increasing the combined resistance J3. There was a problem in that it was necessary to repeat a series of procedures for cutting out the metal wiring many times, and trimming took a considerable amount of time.
この発明は上記のような問題点を解消するためになされ
たもので、合成抵抗値を減少する方向に調整できてトリ
ミング時間を短絡することができる″ｆ−導体集積回路
の抵抗トリミング方法を提供することを目的とする。This invention has been made to solve the above-mentioned problems, and provides a resistance trimming method for an F-conductor integrated circuit that can adjust the combined resistance value in a direction that reduces it and shorten the trimming time. The purpose is to
両端に接合端子がそれぞれ設けられた複数の抵抗領域と
、前記各抵抗領域のいずれか一方の前記接合端子にそれ
ぞれ接続された段数の第１金属配線と、前記各抵抗領域
の他方の前記接合端子に接続され絶縁膜を介して前記第
１金属配線と重ね合わされるように配置された第２金属
配線とを備えた半導体集積回路の抵抗トリミング方法で
あって、前記第１および第２金属配線が前記絶縁膜を介
して重ね合わされた部分にレーザー照射を行うことによ
り、前記絶縁膜を破壊するとと６に、前記第１および第
２金属配線を溶融し短絡させて前記゛ 複数の抵抗領域
の合成抵抗値を制御する。a plurality of resistance regions each provided with a bonding terminal at both ends; a number of stages of first metal wiring each connected to the bonding terminal of one of the resistance regions; and the bonding terminal of the other of the resistance regions; A method for trimming a resistance of a semiconductor integrated circuit, comprising a second metal wiring connected to the first metal wiring and arranged to overlap the first metal wiring with an insulating film interposed therebetween, the first metal wiring and the second metal wiring The insulating film is destroyed by irradiating the overlapped portion with the insulating film interposed therebetween, and 6) the first and second metal wirings are melted and short-circuited to form a composite of the plurality of resistance regions. Control the resistance value.
この発明における゛Ｖ導体集積回路、の抵抗トリミング
方法によれば、レーザー照射により、第１および第２金
属配線を短絡させて、合成抵抗値を減少、する方向にト
リミングが行なわれる。According to the resistance trimming method for a V-conductor integrated circuit according to the present invention, laser irradiation is used to short-circuit the first and second metal interconnects, thereby reducing the combined resistance value.
第１図はこの発明に係る半導体集積回路の抵抗トリミン
グ方法を説明するための部分平面図である。同図におい
て、従来と異なる点は、新たに抵抗領域１ｆ〜１ｈが抵
抗領域１８〜１ｅに続いて一直線上に配置されるととも
に、これら抵抗領域１ｒ〜１ｈが接合＋ａ ７！−２を
介して第１あるいは第２金属配線５，６により直列に接
続されており、さらに抵抗領域１ｅ、１ｆが接合端子２
および直列接続用配線３により直列に接続されている点
である。FIG. 1 is a partial plan view for explaining a resistor trimming method for a semiconductor integrated circuit according to the present invention. In the figure, the difference from the conventional one is that the resistance regions 1f to 1h are newly arranged in a straight line following the resistance regions 18 to 1e, and these resistance regions 1r to 1h are connected to the junction +a7! -2, and are connected in series by the first or second metal wiring 5, 6, and the resistance regions 1e, 1f are further connected to the junction terminal 2.
and that they are connected in series by series connection wiring 3.
次に、抵抗領域１ｆ、直列接続用配線３．第１金属配線
５および第２金属配線６の構造を第２図をもとに説明す
る。ただし第２図の断面図は、叩解を容易にするために
、上部領域と下部領域とで異なる位置の断面を示してい
る。同図において、７は半導体基板である。この半導体
基板７の上層部には抵抗領ＶＡ１ｆ＃設けられており、
この抵抗領域１ｒの両端部分に設けられている接合端子
２を除いて、抵抗領域１ｆおよび半導体基板７上に第１
絶縁膜８が形成されている。そして、この第１絶縁膜８
上に第１金属配線５が形成され、この第１金属配線５の
一方端は第１絶縁膜８上に形成された直列接続用配線３
と電気的に接続されている。さらに、接合端子２を除い
て、直列接続用配線３．第１金属配線５および第１絶縁
膜８上に第２絶縁膜９が形成されている。そして、この
第２絶縁膜９を介して第１金属配線５と部分的に小ね合
わされるように第２金属配線６が第２絶縁膜９上に形成
され、さらに、第２金属配線６および第２絶縁膜９上に
ガラスコート１０が形成されている。Next, the resistance region 1f, the series connection wiring 3. The structures of the first metal wiring 5 and the second metal wiring 6 will be explained based on FIG. 2. However, the cross-sectional view of FIG. 2 shows the cross-sections at different positions in the upper region and the lower region in order to facilitate beating. In the figure, 7 is a semiconductor substrate. A resistance region VA1f# is provided in the upper layer of this semiconductor substrate 7,
Except for the bonding terminals 2 provided at both end portions of this resistance region 1r, the first
An insulating film 8 is formed. Then, this first insulating film 8
A first metal wiring 5 is formed thereon, and one end of the first metal wiring 5 is connected to the series connection wiring 3 formed on the first insulating film 8.
electrically connected to. Furthermore, excluding the bonding terminal 2, the series connection wiring 3. A second insulating film 9 is formed on the first metal wiring 5 and the first insulating film 8. Then, a second metal wiring 6 is formed on the second insulating film 9 so as to be partially matched with the first metal wiring 5 through the second insulating film 9, and further, the second metal wiring 6 and A glass coat 10 is formed on the second insulating film 9.
抵抗トリミングを行う曲は、上記のように構成されてい
るので、第１および第２金属配線５．６は電気的に遮断
されており、また、抵抗領１１ｂ〜１０はそれぞれ短絡
用金属配線４ｂ〜４Ｃにより電気的に短絡されている。Since the song for resistance trimming is configured as described above, the first and second metal wirings 5.6 are electrically cut off, and the resistance regions 11b to 10 are each connected to the shorting metal wiring 4b. ~4C is electrically short-circuited.
したがって、区間Ｘ−Ｘにおける合成抵抗値は抵抗領ｔ
ｉｌａ、ｌｆ〜１ｈのそれぞれの厄抗圃を合計したもの
となる。Therefore, the combined resistance value in the section XX is the resistance area t
It is the sum of the damage fields of ila, lf to 1h.
設３１上、この合成抵抗値は設語値に一致するように設
定されてるのが一般的であるが、実際に半導体集積回路
を製造した場合には、製造時におけるバラツ１やその他
の要因により合成抵抗値が設計値と異なる餡となること
が多い。またときには、合成抵抗値を設甜圃と異なる値
にしておかなければならない場合も生じる。Generally speaking, this composite resistance value is set to match the design value, but when semiconductor integrated circuits are actually manufactured, due to manufacturing variations1 and other factors, The combined resistance value often differs from the designed value. In addition, sometimes it is necessary to set the combined resistance value to a value different from the value in the installation field.
そこで、合成抵抗値若しくは合成抵抗値と係りを持つ区
間Ｘ−Ｘを含む半導体集積回路の電気的特性を測定して
、所望の合成抵抗値となるように合成抵抗値を調整する
必要が生じる。従来においては、この調整は合成抵抗値
を大きくする方向でのみ行なわれていたが、本実施例で
は上記のように構成しているので、合成抵抗値を小さく
する方向での調整も可能となった。ここで合成抵抗値を
大きくする方法ならびに合成抵抗値を小さくする方法に
ついて以下に詳説する。Therefore, it is necessary to measure the electrical characteristics of the semiconductor integrated circuit including the composite resistance value or the section XX that has a relationship with the composite resistance value, and adjust the composite resistance value so as to obtain a desired composite resistance value. Conventionally, this adjustment was performed only in the direction of increasing the combined resistance value, but since this embodiment is configured as described above, it is also possible to make adjustments in the direction of decreasing the combined resistance value. Ta. Here, a method for increasing the combined resistance value and a method for decreasing the combined resistance value will be explained in detail below.
まず、上記のような測定の結果、合成抵抗値を大きくし
たい場合には、従来と同様、抵抗領域４ｂ〜４ｅのうち
適当な抵抗圃をｂつ抵抗領域に対応する短絡用金属配線
４ｂ〜４Ｃをレーザーによって溶断することにより行な
われる。First, as a result of the above measurements, if you want to increase the combined resistance value, as in the past, connect an appropriate resistance field among the resistance regions 4b to 4e to b and short-circuiting metal wirings 4b to 4C corresponding to the resistance regions. This is done by fusing it with a laser.
逆に、合成抵抗値を小さくしたい場合には、抵抗領域１
ｆ〜１ｈのうち適当な抵抗値をもつ抵抗領域に対応して
設けられている第１および第２金属配線５．６の重ね合
わされた部分にレーザーを照射する。上記部分にレーザ
ーが照射されると、第３図に示すように、ガラスコート
１０および第２絶縁膜９が破壊されるとともに、第１お
よび第２金属配線５．６が溶融される。そして、レーザ
ーの照射を中止した後、上記溶融部分が冷却され、第１
および第２金屈配線５．６が接合されて電気的に接続さ
れる。これにより、抵抗領域１ｆ〜１ｈのうちレーザ照
射位置に対応する抵抗領域の両端が短絡されたことにな
るので、合成抵抗値がその分だけ低下することとなる。Conversely, if you want to reduce the combined resistance value, select resistance region 1.
A laser beam is irradiated onto the overlapped portions of the first and second metal wirings 5.6 provided corresponding to resistance regions having appropriate resistance values among f to 1h. When the above-mentioned portion is irradiated with the laser, the glass coat 10 and the second insulating film 9 are destroyed, and the first and second metal wirings 5.6 are melted, as shown in FIG. After stopping the laser irradiation, the melted portion is cooled and the first
And the second metal wiring 5.6 is joined and electrically connected. As a result, both ends of the resistive region corresponding to the laser irradiation position among the resistive regions 1f to 1h are short-circuited, and the combined resistance value decreases by that amount.
以上のように、第１および第２金属配線５，６の重ね合
ゼ部分をレーザ照射することにより合成抵抗値を減少す
る方向でトリミングを行なえるので、従来の合成抵抗値
を増加する方向でトリミングを行う方法と兼用させるこ
とによって、合成抵抗値の加減による調整が可能となる
。その結束、合成抵抗１直を予め設翳１値に定めておく
ことが可能となり、合成抵抗値を加算のみによって調整
する従来の方法に比べて上記測定やレーザーの照射の回
数を減少でき、トリミング時間を短縮できる。As described above, trimming can be performed in the direction of decreasing the combined resistance value by irradiating the overlapping part of the first and second metal wirings 5 and 6 with the laser, so that trimming can be performed in the direction of decreasing the combined resistance value, which is not the case in the conventional direction of increasing the combined resistance value. By using this method in combination with the trimming method, it becomes possible to adjust the combined resistance value by adding or subtracting it. It is now possible to set the combined resistance value to one value in advance, and the number of measurements and laser irradiations can be reduced compared to the conventional method of adjusting the combined resistance value only by addition. It can save time.
また、合成抵抗値を目標圃以上に増やし過ぎたり、逆に
減らし過ぎた場合でも、両調整できるので、トリミング
作業も容易となる。Furthermore, even if the combined resistance value is increased too much or decreased too much beyond the target field, both adjustments can be made, making trimming work easier.
以上のようにこの発明によれば、第１および第２金属配
線が絶縁膜を介しで重ね合わされた部分にレーザー照射
を行うことにより、合成抵抗値を減少する方向でトリミ
ングでき、トリミング時間の短縮を図れる。As described above, according to the present invention, by laser irradiating the portion where the first and second metal wirings are overlapped with each other via the insulating film, trimming can be performed in a direction that reduces the combined resistance value, and the trimming time can be shortened. can be achieved.
第１、図はこの発明の一実施例に係る半導体集積回路の
部分平面図、第２図は抵抗トリミングを行う前の゛ト導
体集積回路の要部断面図、第３図は第２図の抵抗トリミ
ング後の状態を示す断面図、第４図は従来の半導体集積
回路の部分平面図である。
図において、１ｆないし１ｈは抵抗領域、２は接合端子
、５は第１金属配線、６は第２金属配線、８は第１絶縁
膜、９は第２絶縁膜である。
なお、各図中同一符号は同一・または相当部分を示す。Fig. 1 is a partial plan view of a semiconductor integrated circuit according to an embodiment of the present invention, Fig. 2 is a sectional view of a main part of a conductor integrated circuit before resistor trimming, and Fig. 3 is a partial plan view of a semiconductor integrated circuit according to an embodiment of the present invention. FIG. 4 is a cross-sectional view showing the state after resistor trimming, and FIG. 4 is a partial plan view of a conventional semiconductor integrated circuit. In the figure, 1f to 1h are resistance regions, 2 is a bonding terminal, 5 is a first metal wiring, 6 is a second metal wiring, 8 is a first insulating film, and 9 is a second insulating film. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
領域と、 前記各抵抗領域のいずれか一方の前記接合端子にそれぞ
れ接続された複数の第１金属配線と、前記各抵抗領域の
他方の前記接合端子に接続され絶縁膜を介して前記第１
金属配線と重ね合わされるように配置された第２金属配
線とを備えた半導体集積回路の抵抗トリミング方法であ
つて、前記第１および第２金属配線が前記絶縁膜を介し
て重ね合された部分にレーザー照射を行うことにより、
前記絶縁膜を破壊するとともに、前記第１および第２金
属配線を溶融し短絡させて前記複数の抵抗領域の合成抵
抗値を制御することを特徴とする半導体集積回路の抵抗
トリミング方法。(1) A plurality of resistance regions each having a bonding terminal provided at both ends, a plurality of first metal wirings respectively connected to the bonding terminal of one of the resistance regions, and a plurality of first metal wirings each connected to the bonding terminal of one of the resistance regions; The first terminal is connected to the bonding terminal through an insulating film.
A resistor trimming method for a semiconductor integrated circuit comprising a metal wiring and a second metal wiring arranged to be overlapped with each other, wherein the first and second metal wiring are overlapped with each other with the insulating film interposed therebetween. By applying laser irradiation to
A method for trimming resistance of a semiconductor integrated circuit, comprising destroying the insulating film and melting and short-circuiting the first and second metal wirings to control a combined resistance value of the plurality of resistance regions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62255963A JPH0196954A (en) | 1987-10-08 | 1987-10-08 | Resistance trimming method for semiconductor integrated circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62255963A JPH0196954A (en) | 1987-10-08 | 1987-10-08 | Resistance trimming method for semiconductor integrated circuits |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0196954A true JPH0196954A (en) | 1989-04-14 |
Family
ID=17286009
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62255963A Pending JPH0196954A (en) | 1987-10-08 | 1987-10-08 | Resistance trimming method for semiconductor integrated circuits |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0196954A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0346256A (en) * | 1989-07-14 | 1991-02-27 | Toshiba Corp | Semiconductor device |
| CN111446173A (en) * | 2020-03-16 | 2020-07-24 | 林杰 | Wiring broken wire repairing process |
| WO2022118517A1 (en) * | 2020-12-01 | 2022-06-09 | 株式会社ブイ・テクノロジー | Production method for conductive part, production method for electronic component including conductive part, production method for product made from electronic component including conductive part, conductive part, electronic component including conductive part, and product incorporating electronic component including conductive part |
-
1987
- 1987-10-08 JP JP62255963A patent/JPH0196954A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0346256A (en) * | 1989-07-14 | 1991-02-27 | Toshiba Corp | Semiconductor device |
| CN111446173A (en) * | 2020-03-16 | 2020-07-24 | 林杰 | Wiring broken wire repairing process |
| WO2022118517A1 (en) * | 2020-12-01 | 2022-06-09 | 株式会社ブイ・テクノロジー | Production method for conductive part, production method for electronic component including conductive part, production method for product made from electronic component including conductive part, conductive part, electronic component including conductive part, and product incorporating electronic component including conductive part |
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