JPH0196895A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To transit a row address at high speed by transiting the row address by a word line and a transfer gate, disposing plural groups, sharing a data line pair between the groups and having the input of a differential amplifier. CONSTITUTION:A latch type differential amplifier 5 having a bit line 2 and a complementary bit line 3 having plural memory cells 1 as an input is provided to connect the bit line 2 and the complementary bit line 3 to the data line 8 and a complementary data line 9, respectively through the transfer gate 4. In case two constitutions mentioned above are disposed to form the group 14, the plural groups 14 are provided and the row address is sequentially transited, when the word line 6 is selected and booted, the word line 12 is simultaneously booted, thereby, the row address is sequentially transited at high speed. Namely, when the word line 6 and the gate 4 are selected and the row address is sequentially transited, the gate is not selected but the transfer gate 11 is selected. Further, the row address is transited, the line 12 and the transfer gate 13 are respectively selected, the gate is not selected but the row address is transited.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a semiconductor memory device.

BACKGROUND ART Dynamic RAM (hereinafter referred to as DRAM) is used as a semiconductor memory device with the largest storage capacity, but in recent years there has been a demand for not only an improvement in the degree of integration but also an increase in speed. In the column-related parts of DRAM that are controlled by column addresses, the speed has been significantly increased using methods such as the Nutatic column method, but in the row-related parts controlled by row addresses, The speed has not been increased, which is a problem, especially when used in image processing. FIG. 2 shows a conventional technique. 1 is a memory cell, 2 is a pit line, 3 is a complementary bit line, 6 is a Senne amplifier, and 6 is a word line. As shown in Figure 2, a word line controlled by a row address has a large capacity because a large number of memory cells are connected to it, and it takes time to raise and lower the word line. It is difficult to make a high-speed transition, and this problem is solved by using a complicated control method in which the next address is input in advance in the sequential transition of row addresses used in image processing.

Problems to be Solved by the Invention As stated above, it is difficult to transition row addresses at high speed in DRAMs due to their high degree of integration and structural reasons. In other words, since a large number of memory cells are connected to a word line controlled by a row address, it has a large capacity, takes time to control, and requires a large capacity DRA.
This is because the capacitance of the word line increases as the number of M increases.

In the sequential transition of row addresses used in image processing, etc., it takes time to control the word line, so by inputting the next address in advance, it is possible to transition seemingly at high speed, but this is extremely complicated. The problem is that the circuitry required for this control is complex and takes up a large area.

Means for Solving the Problems The present invention has the following configuration to solve the above problems. That is, a plurality of launch-type differential amplifiers each having a plurality of memory cells and each inputting a pair of bit lines connected to a pair of data lines via a transfer gate are provided to form one group. M pairs of pins in the group intersect with a common word line, and a row address is divided by the word line and the transfer gate, and a plurality of groups are provided, and the data line pairs is common within a group and between groups, and the data line pair is connected as an input of a differential amplifier.

Effects According to the configuration described above, high-speed sequential transition of row addresses is easily possible, and circuit design is easy because no complicated circuit is required. Also, the increase in area is small, and the high speed of DRAM can be reduced. This does not pose any particular problem for integration.

Embodiment FIG. 1 shows a configuration diagram of an embodiment of a semiconductor memory device according to the present invention. As shown in FIG. 1, a latch type differential amplifier 5 is provided which receives a bit line 2 and a complementary bit line 3 having a plurality of memory cells 1, and the bit line 2 and complementary bit line 3 each have a transfer gate 4. via the data line 8. It is connected to the supplementary data line 9. By providing two such configurations, one
The bit lines 2 and complementary bit lines 3 in each group 14 intersect with a common word line 6.

A plurality of groups 14 having the above configuration are provided, and the data lines 8. The auxiliary data line 9 is an input to the differential amplifier 1o, and the transfer gate 4 is controlled by a row response. Allocate row addresses to word line 6. The word line 6 and transfer gate 4.11 are used to create two consecutive row addresses. In addition, when the row address changes sequentially, the next rising word line 12 is set to the word line 6.
By arranging the word line A so that it does not intersect with the bit line pair that intersects the bit line pair, and so that when the word line 6 is selected and rises, the word line 12 also rises at the same time, high-speed sequential transition of row addresses becomes possible.

In other words, when word line 6 and transfer gate 4 are selected and the row addresses are sequentially transitioned, transfer gate 4 is not selected and transfer gate 1 is
1 is selected. Furthermore, when the row address sequentially transitions, the transfer gate 13 that forms the address together with the word line 12 is selected, and the transfer gate 11 is unselected.

At this time, the word line θ falls and a new word line 12 is added.
The word line selected next rises, and the row addresses sequentially transition at high speed.

Effects of the Invention As described above, the present invention enables high-speed sequential transition of shallow addresses easily, and at the same time, does not require a very complicated circuit, which simplifies circuit design and reduces area. It is small and does not pose a particular problem for higher integration of DRAM.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a memory device according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional memory device. 1... Memory cell, 2... Bit line, 3... Compensation line, 4... Transfer gate, 5... Latch type Differential amplifier, 6
...Word line, 7...Transfer gate control line, 8...Data line, 9...
・Supplementary data line, 10...Differential amplifier, 11...
...Transfer gate, 12...Word line, 13...Transfer gate, 149
6000. group. Name of agent: Patent attorney Toshio Nakao and one other name
2 Figure

Claims (1)

[Claims] A group is configured by providing a plurality of latch-type differential amplifiers each having a plurality of memory cells and each inputting a pair of bit lines connected to a pair of data lines via a transfer gate. , the bit line pairs in the group are:
A configuration is adopted in which a row address is divided by the word line and the transfer gate, intersecting a common word line, a plurality of the groups are provided, the data line pair is common within a group and between groups, and the data line pair The pair is a semiconductor memory device connected as an input to a differential amplifier.