JPH0191534A - Pwm/nrz converting circuit - Google Patents

Abstract

PURPOSE:To attain correct conversion without being affected by periodic fluctuation by discriminating logical '0', '1' by a time difference between high and low times of a PWM signal. CONSTITUTION:A PWM signal is inputted to an edge detecting circuit 11, every time a start edge of each bit is detected, an up-down counter 12 is reset, which counts a clock pulse till the next reset. In such a case, however, the up-count is implemented when a PWM signal is at a high level and down-count is implemented at a low level, and a logical output is supplied from logic circuits 24, 25 in response to the count output at the time of resetting. For example, '1' is outputted when the count is a prescribed value or below and '0' is outputted when the count is a prescribed value or over. They are stored respectively in a storage circuit 14, outputted as an NRZ signal and the difference between the high and low level is counted. Thus, even when the period of the PWM signal is fluctuated, the logical state is distinguished clearly depending on the count and the conversion with high accuracy is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial application field This invention uses a pulse width modulated signal (PWM signal) to
The present invention relates to a PWM/NRZ conversion circuit that converts into an NRZ signal.

(B) Conventional technology Conventional PWM/NRZ conversion circuits start a counter at the start of one bit of the PWM signal (rising or falling of the signal), and latch the PWM signal from the count-up output. A circuit that converts the PWM signal into an NRZ signal, and a monostable bi-break instead of a counter, latches the PWM signal with its output signal and converts it to an NRZ signal.
There is something that converts it into a signal.

Generally, as shown in FIG. 3, for a predetermined bit period T, a PWM signal, for example, a logic "0" is at a high level for 1/2 Tb or more from the bit start, and
The logic 1 pin is kept at a high level for a shorter period of 1/2T from the start of the bit (the correspondence between logic and level may be reversed).

In the above-mentioned conventional conversion circuit using a counter, a PWM signal is input to the rising edge detection circuit 1 as shown in FIG. It is being The rising edge detection pulse of the rising edge detection circuit 1 is applied as a reset input to the counter 2, and the counter 2 counts the clock signal of a constant period and applies a count-up output to the CK terminal of the D-type flip-flop 3.

In this conversion circuit, every time the input PWM signal rises, a rising detection pulse is output from the rising detection circuit 1 (see b in Figure 3), which resets the counter 2, and then the counter 2 outputs a clock pulse. When you count up and count up, the count up output (
(see c in FIG. 3), the level of the PWM signal is latched in the D-type flip-flop 3. Since the count-up point of the counter 2 is set in advance to 1/2Tb, for example, in a bit where the PWM signal is "0", the PWM signal is at a high level at the time of count-up, and this high level is the D-type flip-flop 3. The low level signal, that is, the NRZ signal "'0" is output from the summer output terminal of the flip-flop 3 (see d in FIG. 3). On the other hand, P
In the bit where the WM signal is "1", the PWM signal is at a low level at the time of count-up, this low level is stored in the D-type flip-flop 3, and the -q- output terminal of the flip-flop 3 outputs a high level. Signal, completely NR
The Z signal "1" is output (see d in FIG. 3).

In this way, signal change IQ from PWM to NRZ is performed.

As shown in Figure 7, the conventional conversion circuit using a monostable multivibrator uses a monostable multivibrator 4 in place of the counter 2 shown in Figure 6, and converts the monostable multivibrator using the rising edge detection pulse of the PWM signal. The D-type flip-flop 3 stores the PWM signal at the timing when the break 4 is triggered and its output becomes low. The one-shot period of the monostable multi-by-break 4 is preset to 1/2T, and the other operations are almost the same as the circuit shown in FIG.

(C) Problems to be Solved by the Invention In the conventional PWM/NRZ conversion circuits described above, whether they use a counter or a monostable multi-by-break, the timing of latching the PWM signal to the D-type flip-flop is is determined by the count value or one-shot period, and is fixed from the bit start point. Therefore, for example, A of the PWM signal in Fig. 4,
As shown in , there is no problem if the duty ratio that defines '0' and '1' is clearly different, but due to the influence of disturbance etc.
If the period of the PWM signal changes, for example, the PW in Fig. 4
When the period becomes short as shown by D8 of the M signal, the PWM
Even though the duty ratio of the signal is 50% or more, it may be incorrectly converted to logic "11" (see d in Figure 4), or conversely, the period may be changed as shown by Db of the PWM signal in Figure 4. When the length increases, there is a problem in that the PWM signal is erroneously converted to logic "0'' even though the duty ratio is within 50% (see d in FIG. 4), lowering the conversion accuracy. In addition, in the monomulti system, the element that determines the monostable time is an analog circuit, so even if the period of the PWM signal is normal, the monostable time fluctuates due to environmental changes such as temperature and atrophy, causing the same type of erroneous conversion as above. There was a problem that occurred.

This invention was made focusing on the above problems, and
Due to the time difference between the high time and low time of the WM signal, the logic “
The purpose of the present invention is to provide a PWM/NRZ conversion circuit that can distinguish between "0" and "1" and perform correct conversion without being affected by period fluctuations of PWM signals.

(d) Means and operation for solving the problem The PWM/NRZ conversion circuit of the present invention receives a PWM signal,
An edge detection circuit that detects the start edge of each bit of the signal and an edge detection output of this edge detection circuit,
an up-down counter that is reset and counts up in response to a clock pulse when the PWM signal is at a first level, and counts down in response to a clock pulse when the PWM signal is at a second level; and a count output value of this up-down counter. Accordingly, it is comprised of a logic circuit that outputs logic, and a storage circuit that stores the logic output of the logic circuit in response to the edge detection output.

In this PWM/NRZ conversion circuit, the PWM signal is input to the edge detection circuit, and each time the start edge of each bit of the PWM signal is detected, the up/down counter is reset by the edge detection pulse. The up/down counter then counts clock pulses until it is next reset. However, when the PWM signal is at the first level (eg, high level), the clock pulses are counted up, and when the PWM signal is at the second level (eg, low level), the clock pulses are counted down. When the up/down counter is reset, the logic circuit outputs a logic value according to the count output value.

For example, if the count value is greater than or equal to a predetermined value, a first logic output is output, and if the count value is less than or equal to a predetermined value, a second logic output is output. This first or second logical output is
Each is stored in a storage circuit and output as an NRZ signal. The up/down counter counts up or down depending on the level state of the PWM signal, so the difference between the widths of the high level and the low level is counted. Logic states such as "0", "1", etc. can be clearly distinguished from the count value of the down counter.

(E) Examples The present invention will be explained in more detail with reference to Examples below.

FIG. 1 is a block diagram of a PWM/NRZ conversion circuit showing one embodiment of the present invention. In the figure, a PWM signal is input to a rising edge detection circuit 11. Also, PW
The M signal is input as an up/down switching signal for the up/down counter. The rising edge detection circuit 11 is functionally the same as the rising edge detection circuit 1 shown in FIGS. It is also input to the CK terminal of the D-type flip-flop I3.14.15.

The up/down counter 12 counts clock pulses upon receiving them. The manner of counting is to count up when the PWM signal is high, and to count down when the PWM signal is low.

The amplifier down counter 12 has QA, QB, ,Qc,...
・Has output terminals 0, Q, and output terminals Q, , Qc, Qn,
Qy is connected to the input terminals of the AND circuit 16 and the NOR circuit 17, and the output terminal Q is further connected to the D input terminal of the D-type flip-flop 14, and the inverter 1
9 to one of the input terminals of the AND circuit 20 and via the inverter 21 to one of the input terminals of the NOR circuit 22. Further, output terminals Q, , Q, , Q, are connected to input terminals of an AND circuit 20 and a NOR circuit 22, respectively. the output terminal of the AND circuit 16 and N.

The output terminal of the R circuit 17 is connected to the input terminal of the OR circuit 18, and the output terminal of the OR circuit 1 is connected to the D-type flip-flop 13.
is connected to the D input terminal of This AND circuit 16 and N
The OR circuit 17 and the OR circuit 18 constitute a logic circuit 24 for detecting that the duty of the PWM signal, that is, the high-to-low ratio is 1, and that high and low are approximately equal.

The output terminal of the AND circuit 20 and the output terminal of the NOR circuit 22 are O.
It is connected to the input end of the R circuit 23, and the output end of the OR circuit 23 is connected to the D input end of the D-type flip-flop 15. This AND circuit 20, NOR circuit 22, and OR circuit 2
3. The inverter 21 constitutes a logic circuit 25 for detecting that the duty of the PWM signal, that is, the ratio of high and low levels is extreme, resulting in an error. Note that the converted N
A logic signal indicating whether the RZ signal is "1°" or "0" is output.

A non-call signal is output from the Q output terminal of the D-type flip-flop 13, and an NRZ signal is output from the page output terminal of the D-type flip-flop 14.
The Q output terminal error signal of the D-type flip-flop 15 is output as a signal.

Next, the operation of the embodiment PWM/NRZ conversion circuit will be explained. When a PWM signal as shown in a in FIG. 4 is applied to the rising edge detection circuit 11, an edge detection pulse signal is output from the rising edge detection circuit 11 every time the PWM signal reaches the start point of each bit, that is, the rising point. (See b in Figure 4), this causes the up/down counter 1
2 is activated at the same time as it is reset and starts counting clock pulses. A clock pulse with a cycle sufficiently shorter than that of the PWM signal is applied.

The more accurate a conversion operation is required in a system, the shorter the period of the clock pulse is. Since the PWM signal counts up while the PWM signal is at a high level, the count value of the up/down counter 12 increases as time passes at the beginning of startup. Eventually, when the PWM signal becomes low level, the up/down counter 12 starts counting down, and decreases the count value as time passes from the count value that was counted up until then. Eventually,
When the next edge detection pulse arrives, the up/down counter 12 is reset, but at the same time, the output of the output terminal Q is sent to the D-type flip-flop 14, and the output of the OR circuit 18 is sent to the D-type flip-flop 3. The output of circuit 23 is D
They are latched by type flip-flops 15, respectively.

Now, if the high and low periods of the PWM signal are normal, and the high period > the low period (for example, period A in Figure 4 a)
In this case, the count contents of each bit of the up/down counter 12 are as shown by S in FIG. is stored in the output terminal Q until the next reset.
As a result, an NRZ signal of "O" is output.

In contrast, the high and low periods are normal, and the high period <
In the case of a low period (period Ab of the fourth a), the count contents of each bit of the up/down counter 12 become as shown by 9 in FIG. 5, and in this case, the output terminal Q,
Since it is "1", this bit is stored in the D-type flip-flop 14, and an NRZ signal of "1" is outputted from the output terminal Q until the next reset (see e in FIG. 4).

When the high and low periods of the PWM signal are equal to each other (period C in a of FIG. 4), each bit output is
As shown in r in Figure 5, Q= , Q-, Q-, Q
Since all bits of E are “1” or “0”, AN
Since the output of the D circuit 16 or the output of the NOR circuit 17 becomes high, the output of the OR circuit 18 also becomes high, and with the next edge detection pulse, the high of the OR circuit 18 is stored in the D-type flip-flop 13, and the output of the NOR circuit 17 becomes high. , that is, 7 completed: ■ becomes low (see f in Figure 4). In the case of equality, the output of the flip-flop 14 is “0” or “1” (the fourth
(see e in the figure) can obtain an equal output, so it is normal.
0" and "'1" can be distinguished. This PWM/N
In addition to II OII and “1” logic, the RZ conversion circuit has “
"Equal" logical discrimination is possible, and by actively utilizing this equal area, three states can be changed.

If the ratio of the high and low periods of the PWM signal is abnormal, and the high period is less than the low period (period B of a in FIG. 4), the contents of each bit of the up/down counter 12 are as shown in FIG. , QF is “0”, Q, , QG,
Since QH becomes "1", the output of the AND circuit 20 becomes high, the output of the OR circuit 23 becomes high, this high is stored in the D-type flip-flop 15, and the output becomes low. Next (see g in Figure 4), PWM
A signal indicating that the signal is abnormal is output.

Similarly, the high and low period ratio of the PWM signal is abnormal,
High period) Low period (period Bb of a in Figure 4)
, Q, bit is °“1°”, Qv , QGSQH
is "0"', so in this case, the output of the N0R circuit 22 becomes high, the output of δ23 becomes high in OR@, and the D-type flip-flop 15 stores the high value.
Output goes low.

As described above, in this PWM/NRZ conversion circuit, it is possible to clearly distinguish between a normal PWM signal and a signal in which the high and low widths are abnormal. Also, during the period a in Figure 4,
Even if the period is shortened as in , or extended as in , the output of the NRZ signal is based on the contents of the up/down counter 12, that is, the difference in width between high and low in one period of the PWM signal. Therefore, accurate ``1'', ``0'', etc. can be obtained.

In addition, in the above embodiment, in addition to determining 11' and '0°'', the logic circuit 24.2 is used to determine an equal error.
5. A D-type flip-flop 13.15 is provided,
If the system is based on the assumption that the up/down counter does not stop in the equal area r or error areas p and t, the logic circuits 24 and 25 and the D-type flip-flops 13 and 15 may not be provided. Good too.

Furthermore, even when a logic circuit 24 or 25 is provided, the internal logic pattern configuration differs depending on the period of the clock pulse and the extent of the P% q, r, and s regions. The configuration is not limited to the embodiment.

(f) Effects of the invention According to this invention, an up/down counter is provided and the PW
In the period of 1 bit of the M signal, in the first level (low) state, the clock pulse is counted up, and the clock pulse is counted up in the second level (low) state.
In the level (high) state, the clock pulse is counted down, and the count value corresponding to the difference between the high period and the low period is used to obtain the NRZ “bi” or “0”, so even if the period of the PWM signal Even if the value changes, the difference value will not change that much, but it will definitely be 1″, 40
” and perform conversion with high accuracy.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a PWM/NRZ conversion circuit showing an embodiment of the present invention, and FIGS. 2(A) and 2(B) are
A block diagram of the edge detection circuit used in the PWM/NRZ conversion circuit, FIG. 3, shows the PWM of the conventional and the above embodiments.
FIG. 4 is a time chart for explaining the general operation of the /NRZ conversion circuit.
/N Figure 5 is a time chart for explaining the operation of the RZ conversion circuit during abnormal conditions.
In order to explain the operation of the RZ conversion circuit, a truth table of an up-down counter and a diagram to explain the relationship between logical outputs, and FIGS. 6 and 7 are block diagrams showing a conventional PWM/NRZ conversion circuit. be. 11: Rising detection circuit, 12 near-tube down counter, 13/14/15: D-type flip-flop, 24/25
:Logic circuit. Patent Applicant Tateishi Electric Co., Ltd. Agent Patent Attorney Shigeru Nakamura Figure 2 (A) (MSBI QHQcQ, Q, QQQcQ9Q, (L
SB) Take a look at Figure 5.

Claims (3)

[Claims] (1) An edge detection circuit that receives the PWM signal and detects the start edge of each bit of the PWM signal, and is reset by the edge detection output of this edge detection circuit, and the
an up/down counter that receives a clock pulse when the WM signal is at a first level and counts up, and receives a clock pulse when the WM signal is at a second level and counts down;
Depending on the count output value of this up/down counter,
A PWM/NRZ conversion circuit comprising a logic circuit that outputs logic, and a storage circuit that stores the logic output of the logic circuit in response to the edge detection output. (2) The logic circuit provides different logic outputs in response to count output values of the up-down counter being within different first, second, and third predetermined regions. PWM/NRZ conversion circuit according to item 1. (3) The logic circuit includes an error storage circuit that includes a logic output portion in response to being outside the first, second, and third predetermined areas, and stores this logic output as an error. PWM/NR according to claim 2
Z conversion circuit.