JPH0160970B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field The present invention relates to an analog switch circuit that uses insulated gate field effect transistors to control the transmission of analog signals. (B) Background Art In general, as shown in FIG. 1, an analog switch circuit is a transmission circuit composed of P-type and N-type field effect transistors 1 and 2 whose first and second electrodes are commonly connected, respectively. It has gate 3 ,
Each common electrode is connected to an input terminal 4 and an output terminal 5. Then, a rapidly changing control signal Vc and its inverted signal as shown in FIG . On/off control is performed. In addition, in order to lower the on-resistance and improve the distortion factor, the P-type substrate (P
The potential of the well region) is set to the input voltage Vi when the transmission gate 3 is on, and to the power supply potential when the transmission gate 3 is off.
A device with a switching circuit 6 added for switching to Vss is also widely used, and this switching circuit 6 has the same configuration as the transmission gate 3 , and is connected to the gate connected between the input terminal 4 and the P-type board. It consists of a circuit 7 and an N-type field effect transistor 8 connected between a P-type substrate and a power supply terminal Vss. An inverted signal of the control signal Vc is applied to the gates of the P-type field effect transistor 9 and the N-type field effect transistor 8 that constitute this gate circuit 7.
The N-type field effect transistor 10 receives a control signal Vc.
is applied. However, in order to reduce the impedance of a transmission gate that transmits an analog signal, the field effect transistor that constitutes the transmission gate is usually larger in size than a general transistor, and the gate insulating film is also thinner. For this reason, the gate-source capacitance and gate-drain capacitance also increase, and as in the past,
When a rapidly changing control signal is applied to the gate, the differential waveform of its rising or falling edge appears as noise in the output signal. Therefore, the applicant of the present application considered preventing the generation of noise by gradually raising and lowering the gate potentials of the field effect transistors 1 and 2 that constitute the transmission gate 3. However, in the conventional circuit, the transmission Since the gate of the field effect transistor forming the switching circuit 6 was controlled by the signal controlling the gate of the field effect transistor forming the gate 3 , the P-type and N-type field effect transistors 9 and 8 of the switching circuit 6 Both are turned on for a certain period of time, and as a result, the input analog voltage Vi falls below the power supply potential.
A problem has arisen in which the voltage drops for a certain period of time to near Vss. (c) Purpose of the Invention The present invention focuses on the fact that there is a relatively large gate capacitance between the gate and substrate of a field effect transistor that constitutes the transmission gate of an analog switch, and charges this gate capacitance with a constant current. By discharging, the generation of noise during switching is prevented, and a signal different from the signal that controls the gate of the field effect transistor forming the transmission gate is applied to the gate of the field effect transistor forming the switching circuit. This provides a novel analog switch circuit that prevents the input analog voltage from dropping to near the power supply voltage for a certain period of time. (D) Embodiment FIG. 3 is a circuit diagram showing an embodiment of an analog switch circuit according to the present invention constructed using MOS field effect transistors, and the transmission gate 11 is similar to the conventional example shown in FIG. A P-type MOS field effect transistor 14 (hereinafter referred to as PMOST) and an N-type MOS field effect transistor 15 have first and second electrodes connected in common, and this common electrode is connected to an input terminal 12 and an output terminal 13, respectively. (hereinafter referred to as NMOST).
The N-type substrate of PMOST 14 is connected to one power supply terminal _VDD . Also, PMOST16 and NMOST
The switching circuit 20 consisting of the gate circuit 18 consisting of the gate circuit 17 and the NMOST 19 is also configured in the same manner as shown in FIG.
The P-type substrate of the NMOST 15 of the transmission gate 11 is connected to the connection point with the NMOST 15 of the transmission gate 11. Here transmission gate 1
1, the gate capacitance of PMOST14 and NMOST15, that is, the capacitance ratio between the gate capacitance CGP between the gate of _PMOST14 and the N-type substrate and the gate capacitance _CGN between the gate of NMOST15 and the P-type substrate is approximately 2. :1, and in this embodiment it is also assumed to be 2:1. Note that each gate capacitance has little voltage dependence and is almost constant. In addition, in FIG. 3, 21 and 22 are NMOSTs connected to PMOST 23 whose gate and drain are connected.
A predetermined bias is applied to the gate from a bias circuit 25 in which 24 are connected in series, and the source is connected to the power supply terminal.
The constant current PMOSTs 26 and 27, which operate as constant current circuits connected to V _DD , have a predetermined bias applied to their gates from a bias circuit 30 in which a PMOST 29 is connected in series to an NMOST 28 whose gate and drain are connected, and the source is Constant current that operates as a constant current circuit connected to the power supply terminal Vss
NMOST, constant current PMOST22 and constant current
The constant current value of NMOST27 is the constant current PMOST21
The constant current value Io of the constant current NMOST 26 is set to approximately one half, that is, Io/2. The gate of the PMOST 14 that constitutes the transmission gate 11 is
Constant current PMOST 21 and constant current NMOST 26 through the conductive paths of PMOST 31 and NMOST 32, respectively.
The gate of NMOST15 is connected to the drain of constant current PMOST22 and constant current through conductive paths of PMOST33 and NMOST34, respectively.
Connected to the drain of NMOST27. A rapidly changing control signal Vc as shown in FIG . NMOST1
9, the control signal Vc is connected to the inverter 35.
and 36, inverted signals are applied. Therefore, the control signal Vc becomes "L" as shown in Figure 2 A.
When the level is reversed to "H" level, the change is steep, so almost at the same time, the switching circuit 20
NMOST19 turns off, PMOST16 and
NMOST17 is turned on, and therefore the P-type substrate of NMOST15 of transmission gate 11 and input terminal 12
is connected. Furthermore, when the control signal Vc becomes "H" level, NMOST32 and PMOST33 are turned on and PMOST31 and NMOST34 are turned off, so that the gate of PMOST14 that constitutes the transmission gate 11 receives a constant current NMOST via NMOST32.
The gate of NMOST15 is connected to the drain of PMOST26, and the gate of NMOST15 is connected to the drain of PMOST26 through PMOST33.
Connected to the drain of 2. For this reason, PMOST
Gate capacitance C _GP between the gate of 14 and the N-type substrate
The gate capacitance _CGN between the gate of NMOST15 and the P-type substrate is charged with constant currents Io and Io/2, respectively, and the potentials _VGP and _VGN of each gate are as shown in Figure 2 B and C. , it gradually descends and rises along a straight line with an almost constant slope. Then, when the gate potential V _GP falls below the threshold voltage Vp and the gate potential V _GN becomes higher than the threshold voltage V _N , PMOST14 and NMOST15 are turned on, the transmission gate is turned on, and the input analog signal Vi is transferred to the output terminal 13. transmitted. Moreover, when the control signal Vc is inverted from the "H" level to the "L" level, the change is steep, so that the switching circuit 20 PMOST16 and NMOST1 are switched almost simultaneously.
7 is turned off and NMOST19 is turned on, so that
The P-type substrate of NMOST15 of transmission gate 11 is
Connected to power supply terminal Vss via NMOST19,
The input terminal 12 is not connected to the P-type substrate or to the power supply terminal Vss. Also, NMOST32 and PMOST33
is turned off and PMOST31 and NMOST34 are turned on, so the gate of PMOST14 is connected to PMOST31.
The gate of the NMOST 15 is connected to the drain of the constant current NMOST 27 via the NMOST 34. Therefore, the charges of the gate capacitance C _GP between the gate of PMOST 14 and the N-type substrate and the gate capacitance C _GN between the gate of NMOST 15 and the P-type substrate are as follows.
The potentials V _GP and V _GN of each gate discharged with constant currents Io and Io/2, respectively, gradually rise and fall along a straight line with a substantially constant slope. And the gate potential
When V _GP becomes higher than the threshold voltage Vp and the gate potential V _GN becomes lower than the threshold voltage V _N ,
The PMOST 14 and the NMOST 15 are turned off, the transmission gate 11 is turned off, and the input analog signal Vi is no longer transmitted to the output terminal 13. In this way, the transmission gate 11 is configured.
Since the gate capacitors of PMOST 14 and NMOST 15 are charged and discharged at a constant current to control on/off of the transmission gate 11 , a steep signal is not applied to the gate, and the gate potential rises and falls along a straight line with an almost constant slope. Therefore, transmission gate 1
The generation of noise during on/off switching of 1 is prevented. Furthermore, the PMOST 16 that constitutes the switching circuit 20 and
Since the gates of NMOSTs 17 and 19 are applied with a rapidly changing control signal Vc and its inverted signal, which is different from the signal controlling the gates of PMOST 14 and NMOST 15 of the transmission gate 11 ,
PMOST16 and NMOST19 are no longer turned on at the same time, so the input terminal 12 is no longer connected to the power supply terminal Vss, and the input voltage Vi
This prevents the power supply voltage from dropping to Vss. In the embodiment shown in FIG . 3, since the gate capacitances C _GP and C _GN of the transmission gate 11 are different, charging and discharging are performed using different constant current circuits.
Constant current PMOST2
1 and 22 in common, and constant current NMOST
Even if 26 and 27 are used in common, almost the same operation can be performed. In the embodiment shown in FIG. 3, first, the gate circuit 18 of the switching circuit 20 is turned on by the control signal Vc, the P-type substrate of the NMOST 15 is connected to the input terminal 12, and at the same time, the gate capacitance of the NMOST 15 is determined. Start current charging, then transfer gate 1
1 was turned on. For this reason, NMOST15
The gate capacitance between the gate and the P-type substrate has little voltage dependence and is almost constant, so it does not pose much of a problem in practice, but it changes slightly during constant current charging due to changes in the input voltage. Therefore, the control signal Vc
A delay circuit is provided to delay the control signal Vc and input the delayed signal to the switching circuit 20 , and as shown in FIG . to the gate of NMOST 17, and the inverted signal to each of the switching circuits 20 .
Apply to the gates of MOST16 and 19,
The potential of the P-type substrate of the NMOST 15 is kept at the power supply potential Vss at least until the transmission gate 11 is turned on.
The gate capacitance may be kept constant to ensure that the gate capacitance remains constant. (e) Effect The analog switch circuit according to the present invention performs on/off control of the transmission gate by constant current charging and constant current discharging of the gate capacitance of the field effect transistor constituting the transmission gate. Along a straight line with a constant slope,
can be gradually raised and lowered, thus
It is possible to reliably prevent noise from being generated due to application of a steep voltage to the gate. Furthermore, the gate of the field effect transistor constituting the switching circuit is supplied with a rapidly changing control signal and its inverted signal, or
Since control is performed by applying a delayed signal of the control signal and its inverted signal, it is possible to prevent the input analog voltage from decreasing at the time of switching, and therefore the input analog signal can be transmitted without distortion.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing a conventional analog switch circuit, Fig. 2 is a waveform diagram for explaining the operation of the analog switch circuit of the present invention, and Fig. 3 is a circuit diagram showing an embodiment of the analog switch circuit according to the present invention. be. Explanation of main drawing numbers, 3 , 11 ...transmission gate,
4, 12... Input terminal, 5, 13... Output terminal,
7, 18... Gate circuit, 6 , 20 ... Switching circuit, 19... NMOST, 14... PMOST forming a transmission gate, 15... NMOST forming a transmission gate, 21, 22... Constant current PMOST, 2
6, 27...constant current NMOST, 25 , 30 ...
Bias circuit, 35, 36...inverter.

Claims (1)

[Claims] 1 P in which the first and second electrodes are each commonly connected
The transmission gate is composed of a transmission gate having a common electrode connected to an input terminal and an output terminal, respectively, a gate circuit having the same configuration as the transmission gate, and an N-type field effect transistor. a switching circuit for switchingly connecting a P-type substrate of an N-type field effect transistor to either the input terminal or a first power supply terminal; first and second constant current circuits;
Third and fourth constant current circuits connected to the second power supply terminal and the gates of the P-type field effect transistors constituting the transmission gate are connected to the first and third constant current circuits in accordance with a control signal. a first changeover switch for selectively connecting a gate of an N-type field effect transistor constituting the transmission gate; and a second changeover switch for selectively connecting a gate of an N-type field effect transistor constituting the transmission gate to the fourth and second constant current circuits in accordance with a control signal. By charging and discharging each gate capacitance of the field effect transistor constituting the transmission gate with a constant current according to the control signal, the transmission gate is controlled on and off, and the control signal or a delay signal of the control signal is controlled. An analog switch circuit characterized in that the gate of each field effect transistor of the switching circuit is controlled by: 2. In claim 1, the first and second constant current circuits are common, and the third
and a fourth constant current circuit.