JPH0156536B2 - - Google Patents

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a method for manufacturing a semiconductor device.

[Technical background of the invention and its problems]

Conventionally, a semiconductor device called a GaAsFET has been manufactured in the following manner when a high concentration impurity region is formed in a gate electrode or an automix electrode is formed. First, second
As shown in FIG. A, after forming a low concentration region 2 of N-type conductivity in a predetermined region of a GaAs semiconductor substrate 1, a gate electrode of a refractory metal in a predetermined pattern is formed on the low concentration region 2. Next, as shown in FIG. 3B, after an insulating film 4 with good step coverage is deposited, a resist film 5 in a predetermined pattern is formed on the insulating film 4. Next, using this as a mask, ions of N-type high concentration impurity are implanted to form N-type high concentration impurity region 6 in low concentration region 2, which is activated by heat treatment. Thereafter, as shown in the figure C, a predetermined pattern of ohmic electrodes 7 is formed on the high concentration region 6, and then, as shown in the figure D, unnecessary ohmic electrode forming members are lifted off together with the resist film 5, and gate self-alignment is performed. Semiconductor layer 10 of the structure
get.

In this manufacturing method, the high concentration impurity region 6 is automatically determined for the gate electrode 3, but in order to form the ohmic electrode 7, lithography technology is used to form the gate/source electrode, gate - Drain electrode spacing must be determined accurately. However, there is a limit to this accuracy,
Misalignment is likely to occur. In the case of GaAsFETs in particular, the source series resistance has a large effect on the high frequency characteristics, so any misalignment in the set positions of the gate electrode 3 and the automic electrode 7 poses a problem as it deteriorates the high frequency characteristics.

In order to solve this problem, a method has been developed in which the automix electrode 7 is manufactured with a cell-aligned structure. In this method, first, as shown in FIG. 3A, a low concentration region 2 of N conductivity type is formed in a predetermined region of a semiconductor substrate 1. Next, this low concentration region 2
A gate electrode 3 is formed thereon using a low resistance metal such as A. Next, as shown in Figure B, the main surface of the semiconductor substrate 1 including the gate electrode 3 is subjected to thermal CVD
Oxide film 1 is formed by chemical vapor deposition method.
form 1. Next, as shown in FIG.
The oxide film 11 is left. Next, as shown in FIG. 1D, an automic electrode forming member 12 and a resist film 13 are sequentially laminated on the main surface of the semiconductor substrate 1 including the oxide film 11 which has become the sidewall portion and the gate electrode 3. Next, as shown in Figure E, the resist film 13 on the gate electrode 3 and the automic electrode forming member 12 are removed by the RIE method. Thereafter, as shown in FIG. F, the remaining resist film 13 is removed by ion milling to obtain a semiconductor device 20 on which an automix electrode 14 of a predetermined pattern is formed.

In this method, in order to form the automatic electrodes 14, which are source and drain electrodes,
The process becomes complicated because the ion milling method is used instead of the RIE method. Furthermore, it is difficult to detect the end point of etching when removing the ohmic electrode forming member 12 on the gate electrode 3. Therefore, there is a problem that source and drain electrodes cannot be uniformly separated within one wafer.

[Purpose of the invention]

According to the present invention, high-concentration impurity regions that will become sources and drains and automatic electrodes that will become these electrodes can be easily formed using self-alignment technology in a simple process, and a highly reliable element with high shape accuracy can be obtained. A method for manufacturing a semiconductor device is provided.

[Summary of the invention]

The present invention uses the insulating layer on the top and side surfaces of the gate electrode as a mask for implanting high-concentration impurities, and forms an insulating layer with poor step coverage on the shoulder of the gate electrode to create an overhang structure. By using this method, the ohmic electrodes can be completely separated, and the highly concentrated impurity regions that will become the source and drain, as well as the ohmic electrodes that will become these electrodes, can be easily formed using self-alignment technology in a simple process, resulting in high shape accuracy and reliability. This is a method of manufacturing a semiconductor device that can obtain a device with high performance.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to FIGS. 1A to 1G.

First, as shown in FIG. 1A, ions of Si, for example, are implanted into a semiconductor substrate 21 made of GaAs and annealed to form a predetermined low concentration region 22. Next, on the semiconductor substrate 21 including the low concentration region 22, a high melting point metal layer 23 having a thickness of 0.1 μm and serving as a gate electrode,
A barrier metal layer 24 and a low-resistance metal layer 25 having a thickness of about 0.5 μm, for example, made of Tiw, Mo, and Au are sequentially laminated. Next, a silicon oxide film, for example, is formed as an insulating film 26 on the low resistance metal layer 25 to a thickness of approximately
After estimating the thickness of 0.6 μm, a resist film 27 with a predetermined pattern is formed thereon. It is desirable that the resist film thickness be as thin as possible in order to reduce pattern conversion differences.

Next, as shown in FIG. B, using the resist film 27 as a mask, a resist pattern is transferred onto the insulating film 26 using, for example, RIE. Next, resist film 2
7 is removed, and the pattern of the insulating film 26 is transferred to the low resistance metal layer 25, the barrier metal layer 24, and the high melting point metal layer 23, which are the underlying metal layers, using, for example, ion beam milling using the insulating film 26 as a mask, and then forming the gate. Form an electrode.

Next, as shown in FIG. 3C, a second insulating film 28, for example, a plasma silicon oxide film, is deposited to a thickness of about 0.3 μm on the main surface of the semiconductor substrate 21 including the remaining insulating film 26 and the underlying metal layer. A resist film 29 with a predetermined pattern is formed on the second insulating film 28, and high-concentration Si ions are implanted into the low-concentration region 2 using this resist film 29 and the second insulating film 28 as masks to form sources and drains. The high concentration region 30 is formed by self-alignment. Here, as the conditions for implanting the Si ions, an acceleration voltage is selected so that the Si ions penetrate the second insulating film 28 having a thickness of approximately 0.3 μm. In addition, by controlling the thickness of the second insulating film 28 on the side surface of the gate electrode, the gate-source and gate-drain distances can be controlled, allowing the FET to have a high gate breakdown voltage.
Try to get the following. Next, the resist film 29 is removed, and in order to activate the high concentration region 30 made of N-type impurities, for example, a halogen lamp is used to activate the high concentration region 30 made of N-type impurities.
Heat treatment is performed at 850°C for 5 seconds.

After that, as shown in Figure D, a third insulating film 31 with poor step coverage is deposited to a thickness of about 0.4 μm on the CVD silicon oxide film 28, and an overhang structure is formed at the shoulder of the gate. do. This makes it easy to cause breakage when applying ohmic metal, which will be described later. Next, as shown in Figure E,
A resist film 3 having a predetermined pattern on the third insulating film 31
After forming the second and third layers, for example, using the RIE method,
A window 33 is formed in the insulating films 28, 31 to expose the high concentration region 30, and portions of the second and third insulating films 28, 31 are left on the top and side surfaces of the gate electrode.

Next, as shown in FIG.
For example, AuGe (5%)/Ni is used as a metal.
It is deposited on the high concentration region 30 and the resist film 32 to a thickness of 0.2 μm/0.03 μm. Next, resist film 3
2 and the unnecessary ohmic electrode forming member attached thereto are removed by lift-off. After this, as an alloying treatment for the ohmic electrode 34, approximately
Heat treatment is performed at a temperature of 430° C. for 5 minutes in an N ₂ atmosphere. Further, the second and third insulating films 28 and 31 and the ohmic electrode forming member deposited thereon are removed using, for example, ammonium fluoride (NH ₄ F) or the like.

In this way, as shown in FIG. G, a semiconductor device 40 constituting a GaAs MESFET in which the spacing between the gate and source electrodes and the spacing between the gate and drain electrodes are set to be equal is obtained.

In the semiconductor device 40 obtained in this way,
The thicknesses of the second and third insulating films 28 and 31 on the gate side walls are precisely set so that the distance between the gate and the ohmic electrode 34 is equal.

In addition, in terms of process, a second insulating film 2 with poor step coverage is added on the first insulating film 26.
By depositing 8 to form an overhang portion, it is possible to easily break the ohmic electrode forming member deposited on the upper part of the gate, facilitate lift-off, and improve yield. Also,
Since a high melting point metal is used as the gate electrode, activation heat treatment of the high concentration region 30 can be performed after forming the gate electrode. As a result, the process of forming the high concentration region 30 after forming the gate electrode and the process of forming the ohmic electrode 34 are all performed in self-alignment, eliminating the need for strict mask alignment accuracy, simplifying the manufacturing process, and improving the characteristics of the device itself. It is possible to suppress the variation in

〔Effect of the invention〕

As explained above, according to the method of manufacturing a semiconductor device according to the present invention, high-concentration impurity regions that will become sources and drains and ohmic electrodes that will become these electrodes can be easily formed by self-alignment technology in a simple process, An element with high shape accuracy and reliability can be easily obtained.

[Brief explanation of drawings]

Figures 1A to 1G are explanatory views showing the method of the present invention in the order of steps, Figures 2A to 3D, and Figure 3A
FIGS. 1A to 1F are explanatory diagrams showing a conventional method for manufacturing a semiconductor device in the order of steps. 21...Semiconductor substrate, 22...Low concentration region, 2
3... High melting point metal layer, 24... Barrier metal layer,
25...Low resistance metal layer, 26...Insulating film, 27...
...Resist film, 28...Second insulating film, 29...Resist film, 30...High concentration region, 31...Third insulating film, 32...Resist film, 33...Window, 34...
... Ohmic electrode, 40 ... Semiconductor device.

Claims (1)

[Claims] 1. Forming a low concentration region of a predetermined conductivity type in a predetermined region of a semiconductor substrate, and forming a high melting point metal layer, a barrier metal layer, on the surface of the semiconductor substrate including the low concentration region.
a step of sequentially laminating a low-resistance metal layer and a first insulator layer, and using a photoresist film of a predetermined pattern as a mask, the first insulator layer, the low-resistance metal layer,
sequentially patterning a barrier metal layer and a high melting point metal layer to form a gate electrode and leaving the first insulating layer in a predetermined pattern on the gate electrode; a step of depositing a second insulating layer with good step coverage on the main surface of the semiconductor substrate including
After forming a resist film with a predetermined pattern on the insulating layer, a high concentration impurity is implanted into the low concentration region using the resist film as a mask to form a high concentration impurity region, and a third step with poor step coverage.
depositing an insulating layer on the second insulating layer to form an overhang at the top of the gate;
a step of removing a portion of the second and third insulating layers using a resist film of a predetermined pattern as a mask and using anisotropic dry etching to provide an opening that exposes the high concentration region; depositing an ohmic metal layer over the high concentration region and the third insulator layer; and removing the first, second and third insulator layers together with the overlying ohmic metal layer. A method for manufacturing a semiconductor device, comprising: