JPH0150995B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a readout circuit for a digital information storage device, and more particularly to a readout circuit suitable for an optical disk device that optically records and reproduces information.

Optical disk devices use a semiconductor laser or the like as a light source. Information is recorded by modulating the laser beam with digital information and forming pits on the recording medium. Also, when reproducing information, the laser beam is used to record information. detects that the reflected light changes depending on the presence or absence of pits when it is irradiated onto a
A method is used to obtain a readout signal by comparing the detection output with a threshold value. In this case, since the information is at the point of change between the presence and absence of pits, it is important how accurately the pits are recorded or reproduced. However, during recording, even if the data interval is 50% duty, which corresponds to a 1:1 spacing between the presence and absence of pits, the formation of pits depends on the recording energy, so the relative speed between the optical head and the medium or the recording power Therefore, the duty on the actual medium changes. In addition, during playback, low frequency fluctuations in the medium reflectance occur in the low frequency range of the playback signal.
Alternatively, servo error signals are included, and these components become unnecessary noise for information reproduction and must be cut.As a result, low frequency components that contain information are not reproduced, resulting in baseline fluctuations in the reproduced signal. occurs. The above-mentioned duty changes or baseline fluctuations result in bit shifts and are a factor in reducing the read error margin.
The FM method, which is widely used as a recording modulation method, has a wide data discrimination window and has few low frequency components in the reproduced signal, so these effects are small.
A fixed value or an average value of the read signal has been used as the detection threshold of the read circuit. but,
The FM method has a bit density of 2 compared to the information recording density.
Modified due to poor recording efficiency
There is a tendency for the FM (MFM) method to be used.
Although the MFM method has good recording efficiency, the data discrimination window is narrow and the reproduced signal contains many low frequency components. Alternatively, there is a problem in that the bit shift caused by baseline fluctuation cannot be corrected, resulting in a reduction in the read error margin.

SUMMARY OF THE INVENTION An object of the present invention is to provide a readout circuit for a storage device that corrects bit shifts caused by low frequency changes or baseline fluctuations, which could not be solved with the prior art.

A readout circuit for a storage device according to the present invention includes: a comparison circuit that compares a reproduced analog signal with a threshold value and outputs a binary readout signal; a clock circuit that generates a clock signal phase-synchronized with the readout signal; In a readout circuit for a storage device having means for reproducing stored information by data-discriminating a readout signal using the clock signal, the time difference between the readout signal and the clock signal is determined according to the rising and falling polarities of the reproduced analog signal. The device includes a detection circuit and a circuit that detects a difference between the detected polarity time differences and outputs a difference signal, and controls the threshold of the comparison circuit so that the difference signal is minimized to perform reading. It is characterized by the fact that

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the MFM recording modulation system, in which 1 is an optical reproducing head, 2 is an amplifier circuit, 3 is a comparison circuit, 4 is a clock generation circuit, 5 is a data demodulation circuit, and 6 and 7 are inverter,
8 to 15 are D-type flip-flops, 16 and 17 are OR circuits, 18 is a differential amplifier circuit, and 19 is a low-pass filter. Further, FIG. 2 is an operational waveform diagram of each part in FIG. 1, and a to j correspond to those in FIG. 1.

The optical reproduction head irradiates the recording medium with laser light,
It has the function of converting the strength of reflected light into electrical signals,
The output is amplified by an amplifier circuit 2 and becomes a reproduced analog signal a. The reproduced analog signal a is compared with a threshold voltage in a comparator circuit 3 and becomes a read signal b.
The signal is input to a clock generation circuit 4 and a data demodulation circuit 5. The clock generation circuit 4 generates a clock signal c that is phase-synchronized with the input read signal b, and the data demodulation circuit 5 generates a clock signal c that is phase-synchronized with the input read signal b.
and the clock signal c to obtain read data. On the other hand, the polarities of the read signal b and the clock signal c are inverted by inverters 6 and 7, and the read signal and clock signal of both polarities are passed through the D-type flip-flops 8 to 7.
15. As a result, the flip-flop 8 receives the read signal b when the clock signal c is "1".
The flip-flop 9 is set at the rising edge of the read signal b when the clock signal c is "0", and the flip-flop 10 is set at the falling edge of the read signal b when the clock signal c is "1". , the flip-flop 11 is set at the fall of the read signal b when the clock signal c is "0". Flip-flops 12-15 are for resetting flip-flops 8-11, and flip-flops 8-12, 9-13,
The flip-flops 10-14 and 1-15 are paired, and after each flip-flop 8-11 is set, it operates to be reset by the next clock signal.
Therefore, from the output d of the flip-flop 8 and the output e of the flip-flop 9, a time pulse proportional to the time difference _TER between the readout signal b at the rising polarity of the reproduced analog signal a and the center of the clock signal c is obtained, and the OR circuit 16 The sum of both is calculated to create a time difference signal h with rising polarity. Similarly,
From the output f of the flip-flop 10 and the output g of the flip-flop 11, a time difference signal i proportional to the time difference _TEF at the falling polarity of the reproduced analog signal a is created. Next, the differential amplifier circuit 18 detects the difference between the bipolar time difference signals h and i to obtain a difference signal j, and after the high frequency component is removed by the low pass filter 19, it is input to the comparator circuit as a threshold voltage. Ru.

The waveform diagram shown in Figure 2 assumes a case where a shift in duty occurs, and when the threshold voltage is apparently higher than the optimal value shown by the dashed-dotted line, as shown by the broken line in Figure a. In the difference signal j, the pulse width on the negative side is 3T ₀ +T _EF , and the pulse width on the positive side is 3T ₀ −
A negative voltage corresponding to the time difference T _EF + _{T ER is} supplied to the comparator circuit 3 as a threshold voltage. Therefore, in the state shown in FIG. 2, the circuit performs a feedback operation to lower the threshold voltage, and the threshold voltage is controlled so that the correct duty is always obtained. Further, by setting the shedding frequency of the low-pass filter 19 to a value higher than the shearing frequency at the low frequency of the amplifier circuit 2, it is possible to perform reading that follows the baseline fluctuation of the reproduced analog signal a.

In the above embodiment, an example of the circuit is shown in which the MFM method is used as the recording modulation method, but the present invention is not limited to the MFM method, and any modulation method that allows self-clocking can be applied.

As explained above, the present invention detects the threshold value for comparison with the reproduced analog signal by detecting the time difference between the readout signal and the clock signal for data discrimination according to the polarity of the reproduced analog signal, and the difference signal of the time difference between the two polarities is minimized. Such control has the effect of reducing bit shifts caused by baseline fluctuations when the duty changes and improving the read error margin.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram showing the operation of each part in FIG. 1... Optical reproduction head, 2... Amplification circuit, 3...
Comparison circuit, 4...Clock generation circuit, 5...Data demodulation circuit, 6, 7...Inverter, 8-15...
...D-type flip-flop, 16, 17...OR circuit, 18...differential amplifier circuit, 19...low-pass filter.

Claims (1)

[Claims] 1. A comparison circuit that compares a reproduced analog signal with a threshold value and outputs a binary readout signal, a clock circuit that generates a clock signal phase-synchronized with the readout signal, and a data valve that converts the readout signal into a data valve using the clock signal. A readout circuit for a storage device comprising means for separately reproducing digital information; and a circuit that detects a difference in the time difference between the two and outputs a difference signal,
A readout circuit for a memory device, characterized in that reading is performed by controlling a threshold value of the comparison circuit so that the difference signal is minimized.