JPH01500468A - A collection of two or more integrated semiconductor circuits - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] integrated semiconductor memories and integrated signal processors having such integrated semiconductor memories; sa The present invention provides a method for reading data from at least an addressed memory cell. Arranged in a matrix of peripheral circuits to address the memory cells. The present invention relates to integrated semiconductor memories comprising memory cells. The present invention also provides this The present invention relates to an integrated signal processor having such an integrated semiconductor memory.

Within the homologous concept of integrated products, variants of the product preferably with different storage capacities is made available. The increased storage capacity of integrated memory is due to the increase in the number of memory cells and This means an increase in the addressing capacity of the address decoding circuits around the memory. Ru. In this case, the surface area of the substrate increases substantially linearly. This is again Because of the need to design, there are usually far-reaching consequences.

Expansion of storage capacity is achieved when memory is integrated on the board along with a signal processor. has fairly wide-ranging consequences. Not only the memory, but also the area around the memory. The parts of the processor that are used are also "moved". Therefore, a completely new arrangement is must be done for the processor and associated memory. Redesigning integrated products Expensive and required to expand storage capacity of memory integrated on the same board Redesigning the signal processor has been found to be a significant disadvantage.

It is an object of the present invention to improve the memory arrangement when the storage capacity is increased. Integrated semiconductor memory or integrated semiconductor memory with its memory integrated within already existing limits. and an integrated signal processor.

The integrated semiconductor memory according to the invention is characterized in that the number of addressable memory cells is from the number of memory cells potentially addressable by said peripheral circuitry. It is characterized by deviating.

Next, the present invention will be described in detail with reference to the drawings.

In addition, in the drawing, Figure 1 shows the arrangement of the signal processor, Figures 2A and 2B show two different indicates a type of static memory cell, FIG. 3 schematically shows the assembly of an (integrated semiconductor) memory according to the invention, Figure 4 shows part of the memory circuit, FIG. 5 shows an example of an address decoding circuit for an (integrated semiconductor) memory according to the present invention. part, FIGS. 6A and 6B show memory sections with low and high cell densities, respectively. In addition to showing FIG. 7 illustrates the addressing of the memory portions shown in FIGS. 6A and 6B. The truth table for

In FIG. 1, the arrangement of a signal processor 1 is shown. This signal processor 1 has an input register 3 and an arithmetic and logic unit 5 with an accumulator and a multiplier , output register 7, read-only memory 9, read/write memo IJ11 , and a timer unit 13. Also, it is suitable for a given application of the signal processor 1. Read/Write Memo January 1 is a larger table when The entire arrangement of the signal processor 1 may be reconsidered or redesigned in order to occupy the surface area. is necessary.

By using memory cell types of different sizes, the maximum storage capacity ( In other words, the memory filled with the minimum memory (in terms of surface area) in this case By creating a decoding circuit suitable for the matrix), the signal processor 1 can , with various storage capacities without requiring changes in the arrangement of integrated processors. It can be configured as follows. This will be described later with reference to the drawings.

In FIG. 2A, a known 6-transistor memory cell 2A is shown. child The 6-transistor memory cell 2A is the power supply terminal ■. . and power supply terminal VssO connected between two PMO3) transistors Pi, P2 and two NMOS) Ransistor N1. CMOS with N2) has a transistor flip-flop are doing. This 6-transistor memory cell 2A also has two NMOS accesses. Transistor N3. It also has N4. CMOS-transistor flip flow The outputs Q, Q of NMOS access transistors N3. N4 is wordra The bit line BL and the integrated (Inverted) connected to each bit line BL. This kind of 6-transistor memory The size of the cell 2A is, for example, 40.5×40.75μ1112.

In the i2B diagram, a known 4-transistor memory cell 2B is shown. 6 - Portions corresponding to the transistor memory cell 2A are given the same numbers. 2 Instead of a large PMOS transistor (PI, P2. Fig. 2A), 4-The flip-flop of transistor memory cell 2B is a polycrystalline silicon resistor R1 , R2 are used. These polycrystalline silicon resistors R1 and R2 require more difficult technology. but with a surface area of size 25.5 x 25.5 μm2 It becomes a transistor memory cell 2B.

Polycrystalline silicon resistors R1, R2 can be alternatively removed and the 4-transistor memory The technology used to manufacture the recell 2B is simplified and becomes a quasi-static memory cell. CM OS 6-transistor memory cell 2A and 4-transistor memory cell 2B There is an approximately 2:1 relationship between the surface areas of . However, 6-transistor memory The two types of cell 2A and 4-transistor memory cell 2B are approximately rectangular. The ratio of length and width of these two types is 3:2. 2× 2CMO3) Polycrystalline silicon resistors R1, R instead of the transistor memory cell group A 3×3 memory cell group with 2 can be provided on the surface area of the same substrate. death Therefore, the storage capacity is more than doubled. Doubling the storage capacity means addressing The specification requires an address whose bit length is increased by a single bit. means to do so.

In FIG. 3, the arrangement of a memory 30 according to the invention is shown diagrammatically. this Memory 30 consists of two matrices of memory cells arranged in rows and columns. 31A and 31B. The memory cell receives the address signal Yo, Addressed by Xa, L+x, , x, , x, , x,. CM OS) When transistor memory cells are used, address The signal OP can actually be made unnecessary. Address signal X2. Xs, X -, Xs are supplied to the X-pre selection circuit 33A. This X-pre selection circuit 33A are supplied to the X-selection circuit 37 via a link 35 having a width of 8 bits. A selection signal is derived. The address signals OP, XO, Xi are the three X/Y-pre selection circuit 33 that generates a selection signal and three Y-pre selection signals B is supplied. These X-pre selection signals and Y-pre selection signals are The signal is supplied to the Y-decode circuit 39 and the Y-selection circuit 41, respectively. This Y-selection time Path 41 also receives address signal Y0. The output of the X-selection circuit 37 is It is connected to the other input of the decode circuit 39. Therefore, both word lines Drive circuit 43A.

The word line drive circuit in 43B receives the output of the X-post decode circuit 39. can be controlled by a combination of three pre-select signals via the pre-select signal. both word line drive Each word line drive circuit in the drive circuits 43A and 43B is a memory cell matrix. control the word lines of each of the boxes 31A and 31B. There are two Y-selection circuits 41. control the multi-pressure circuits 45A and 45B. These multi-press circuits 45A and 45B, eight columns of memory cells are always connected to each memory cell at the same time. Selected in matrices 31A and 31B. These memory cell matrices The eight selected columns of memory cells in boxes 31A and 31B are In the input circuit 47A and output circuit 47B via the digital circuits 45A and 45B. are connected to corresponding numbers of read and write circuits. These input times The circuit 47A and the output circuit 47B are connected to a signal RWN and a signal φprec, which will be described later. Controlled by h. This signal φprech is also used as a precharge/hold circuit. It is supplied to paths 49A and 49B. These precharge/hold circuits 49A, By 49B, the bit line BL and the inverted bit line is charged for write operations.

In Figure 4, the details of Figure 3, in other words, for example, the precharge/hold circuit. Precharge/hold circuit 49, such as line 49A, memory cell matrix 3 1A memory cell 51, part 45 of multi-pressure circuit 45A, and input circuit 47A read/write circuit 47 is shown. Memory 30 is precharged/ Operates in synchronization with sample clock pulses.

When the signal φprech is “old gh”, the bit line pull and the inverted bit line The two terminals are charged to the same potential. Also, the NMOS transistor 5';-, 53 , 54 are turned on. Furthermore, the inverted signal p prech is connected to the transistor 56, the read amplifier 55 is switched off.

The write circuit 57 also receives a signal HI derived from the signals φprech and RWN. Z is operating to turn off transistors 58, 59, 61, 62. do not have. Pass lines Bus and BIIS are controlled by signal φprech NMOS) Charged to Von-VTH via Ranjistaro 3.64.

These pass lines BtlS and BIIS are connected to multi-press circuits 45A and 45B. The outputs of are connected to the input circuit 47A1 and the output circuit 47B, respectively.

During the “High” state of the signal φprech, the input signals YO, XO to x5 are supplied. The addressed address is also decoded by the X-post decode circuit 39. signal φ After prech ends (signal φprech goes Low.), the memo 30 enters sample mode. Through the X-post decode circuit 39, the word The word line connects the cells connected to that word line to the bit lines BL and BL. It is operated to continue. NMOS) Connect to power supply VDD via transistor 5. The transistors 6 and 67 are connected to the memory cell 51. The data from the bit rate is PMOS) transistor 81.84 and PMOS ) reaches each gate of transistors 82 and 83, and also NMOS) It reaches transistors 88 and 87, respectively. The readout amplifier 55 also has two cross-connects. PMOS) has transistors 85 and 86. These two cross connections PMOS) The gate and main electrode junctions of transistors 85 and 86 are each connected to P One of the connections between MOS) transistor 83 and NMOS l-transistor 87 2 more questions O3) Connection between transistor 84 and NMOS) transistor 88 are connected to one of the two, respectively, to form an output OUT and an inverted output OUT for data. do.

When new data is to be written to the memory cell 51, the signal old Z becomes “old”. Therefore, the data at input DATAIN is divided into two bushes. The pass line BU is connected to the S, supplied to BtlS.

FIG. 5 shows the X-pre selection circuit 33A, SX/Y-pre selection circuit 338, SX- Details of the selection circuit 37, the X-bost decode circuit 39 and the Y-selection circuit 41 are shown. has been done. This X-pre selection circuit 33A consists of eight two-person NOR gates 33A. N and eight inverters 33AI. Address signal X2. X2. The four viable combinations of x3゜x3 are four NOR games) Supplied. (Other four NOR games) 33AN is the address signal X4. X4. X5. Receives 4 possible combinations of X5 and outputs 8 NOR output signals is passed through the inverter 33Al to the X-selection circuit 3702 and the human-powered NOR gate 37N. Supplied. The output of this inverter 33A1 is supplied to 16 NOR gates 37N. and the address signal X2. X2. X3. The combination of each logic of X3 is a Dress signal X4. r4. X5. It is combined with each logic combination of X5.

Each output of NOR gate 37N (only one shown) is an X-post decode It is connected to the inputs of three NAND gates 39B of circuit 39. These NAN Each of the O gates 39B receives the inverted signal φprech in the second input. each The output of the NAND gate 1-39B is connected to the input of the word line drive circuit 43D. ing. 3 NAND games) The third human power of 39B is the X-pre selection signal xpo Xx-Pre selection signal XP! or receive either the X-pre selection signal XP2 . Only one NAND gate 39E receiving the X-pre selection signal χP1 is shown in the drawing. It is shown. The Y-selection circuit 41 has six two-person NAND games) 49B. are doing.

Three of these two human-powered NAND gates 49E are connected to address signals YO and Y. - Receive one of the pre-selection signals YPO, YPl, YF3. the other three NAND game 1-49E has address signal quality and Y-pre selection signals YPO, YP. I, receive one of YF3.

NAND game) 49B output is sent to multiplex circuit via inverter 491 45A, 45B multiplex transistor (see Figure 4, transistor 6 8.69).

The selection method described above aims to achieve the following: address signal x When using 2 to x5, blocks of 8 or 18 memory cells are selected. (See Figures 6A and 6B), address signals DP, XO, XI, YO determines which cell of the associated block is addressed. Memo l730 (Fig. 3) has CMOS) transistor memory cells, the signals x2 to The block selected by x5 has 8 cells and an address signal Leaf selects a cell from the block using the remaining address signals XO, Xi, and YO. Therefore, it should always be "zero" (see Figure 6A). By selection signal xSEL The cells in the selected block are numbered from 0 to 7. Cell 0 selection For selection, the signals XPO, YPO.

YO should be “High” (if signal YO is “High”, Cell 1 is selected. ). For selection of cell 5, signals XP2. YF3. Y O should be "High". This procedure will be explained using the table in FIG.

In this table, address signals DP, XO, Xi, YO, pre-selection signal XP O, XPl, YPO, YPI.

The relationships between YF3 and the cells selected by them are written in the top four rows. . Since there is no movement on the signals XPI, YPI, there are actually two word drivers. Only one driver circuit 4300.43D2 needs to be present. Word line drive times The path 43D1 is shown in broken lines. The reason for this is that this word line drive circuit 43 This is because D1 is integrated in a single arrangement. But why is it connected? stomach. Furthermore, the required multiplex circuit 45 receives only four control signals. (Multiple break from 4 to 1). Therefore, the combination (YPI, YO) and combinations (YPI, ’YO) The jitter can actually be removed in this embodiment.

In Figure 6B, the memory 30 is a polycrystalline silicon resistor (R1, R2, i2, see Figure 6B). A case is shown in which the matrix consists of a small memory cell with ing. When using the signal “X5EL”, a block consisting of 18 memory cells selected. 16 of these memory cells are connected to the word line drive circuit Through three NAND gates 39E controlling 4300.4301.4302 It can be selected by address signals DP, XO, Xi, and YO. pre Selection signals YPO, YPI, YF3 are Y-selection in relation to address signal YO. Via circuit 41, multiplex circuits 45 from 6 to 1 are controlled. By X It should be noted that cells shown as cannot be addressed. Ru. Addressable cells are numbered from 0 to 15. last 2 column and address signals DP, XO to X5 and YO (7) in the table of FIG. In this case, from the values of “)Ihigh (= 1)” and “Low (=O)” Pre-selection signals xPO to XP2. YPO~YP2 moves in response to the selection of a predetermined cell. It can be estimated that this is possible. Also, from the table, to form the desired pre-selection signal , how address signals DP, XO.

It can be estimated whether xl must be logically combined.

Address signals XO, XI, and signal DP are used when the memory capacity is doubled. Note that it is used for line selection (row selection) and bitline selection (column selection). Should be.

The dummy cells indicated by X in each block naturally contain other address bits. can be addressed if is used in addition to the address signal DP . However, in this case the addressing capacity of this additional address bit is Only 178 are used.

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Claims (9)

[Claims] 1. At least that memory cell is used to read data from the addressed memory cell. Memory arranged in a matrix of peripheral circuits for addressing Mori cells In an integrated semiconductor memory comprising cells, The number of addressable memory cells is potentially addressable by the peripheral circuitry. The number of memory cells that can be specified as a response is substantially different from the number of memory cells that can be specified. An integrated semiconductor memory characterized by: 2. The memory cells are arranged in rows and columns, and The peripheral circuit has a row address decoding circuit and a column address decoding circuit, The number of addressable memory cells is the same as the number of column address decoding circuits and the number of addressable memory cells. Less than the product of the number of written address decoding circuits An integrated semiconductor memory according to claim 1, characterized in that: 3. The number of outputs of the column address decoding circuit is equal to the number of outputs of the matrix-shaped peripheral circuit. The collection according to claim 2, characterized in that the number of column drive circuits is larger than the number of column drive circuits. product semiconductor memory. 4. The number of outputs of the row address decode circuit is determined by the number of outputs of the row address decoding circuit. The integrated semiconductor memory according to claim 2, characterized in that the number of lines is greater than the number of lines of Li. 5. The memory cell includes a PMOS transistor and an NMOS transistor. Along with 3 column decode outputs and 3 row decode outputs exist every 2 columns and 2 rows respectively An integrated semiconductor memory according to claim 3 or 4, characterized in that: 6. The memory cells include nine cells arranged in three adjacent rows and three adjacent columns. subdivided into groups, and only 8 of these 9 cells are addressable. It is possible to specify a response. An integrated semiconductor memory according to claim 1 or 2, characterized in that: 7. The X memory cells in the second row and second column of each block are dummy cells. 7. An integrated semiconductor memory according to claim 6. 8. At least a matrix is used to read data from the addressed memory cell. address decoding circuit and its memory cells for addressing. It includes memory cells arranged in peripheral circuits, and also has multi-bit addresses. A first part is supplied to a column decoding circuit for addressing the memory cells. , and the second part of the multi-bit address specifies the addressing of the memory cell. one bit of the multi-bit address is supplied to the row decoding circuit for an integrated semiconductor device, characterized in that it is supplied to a column decoding circuit and to said row decoding circuit; conductor memory. 9. An integrated semiconductor memory according to any one of claims 1 to 8. equip An integrated semiconductor circuit characterized by: