JPH0148552B2 - - Google Patents

Description

[Detailed description of the invention]

TECHNICAL FIELD OF THE INVENTION This invention relates to graphics generators, and more particularly to multicolor raster graphics devices. [Background of the Invention] In recent years, the development of the electronic industry in the field of microelectronics has been remarkable, and many desktop computers on the market today have various computing capabilities. This development is true for consumer microprocessors, computers that are very small in nature, and also for a variety of consumer products, from microwave oven controls to electronic games. This new industry is currently being established. Commercially available microprocessors, e.g.
Manufactured by MOS Technology Inc., part number MCS6500
Efficient small data processing devices for home or (small) business use based on microcomputers are now commonplace. These microprocessor data processing devices are based on the software (programming) that accompanies the unit, that is, the software that provides programmed instructions, checklist balance sheets, classification and rewriting of communication lists, and even games. It can be applied to a variety of uses. The information output by the data processor system is provided to the viewer via some type of printer or video display device. Printers have the advantage of providing information in semi-permanent form. Although display devices display information only while the device is on, an important advantage of video display devices is that most of the world has a device in the form of a television receiver. Since television receivers are already in stock, there are many potential buyers for microprocessor-based data processing equipment, and communication between the equipment and people is therefore easy. Accordingly, most if not all microcomputer data processing devices are configured to mate with raster scan video equipment (ie, television receivers). Modern microcomputer devices have become extremely simple in detail, but have become extremely complex in overall operation. These microcomputers can perform relatively complex tasks by performing many simple operations. Thus, when processing data such as games or number calculations, microcomputers actually perform a significant number of these simple operations. In addition to this data processing function, the microcomputer must effectively control the transmission of information to the video display device, including what information to display and how to display the information. Also included. Therefore, the microcomputer must share its operating time between these two functions: data processing and information display control. When one function makes time-consuming demands on the microcomputer equipment, the other function becomes victim to this. As a result, many microprocessor-based data processing devices are somewhat slow in providing complex task results to users. Several attempts have been made to alleviate this problem. However, the results were not fully satisfactory. For example, one solution is to limit the tasks performed by the microcomputer to less complex tasks. The number of operations required to perform simpler tasks is smaller and therefore shorter. but,
Unfortunately, this solution significantly limits the processing power of the microprocessor and device. Another solution to the time problem is to increase the size of the microprocessor. This increases the size (eg, number of bits) of data words that the microprocessor can operate on. For example, if a microprocessor is configured to process 8-bit data words (as most currently available microprocessors are), it can also process 12- or 16-bit data words. It is made so that it can be done. However, as the size of the words processed by a microprocessor increases, the microprocessor
They are usually proportionately more complex, expensive, and large. The current advantages of the large-scale, single-chip, programmable microprocessors currently in use, which are powerful, cheap, and easy to use, will be lost. [Summary of the Invention] An object of the present invention is to provide a multicolor raster graphics device that avoids increasing the size of data words as much as possible and enables multicolor raster display with as little data processing as possible. shall be. In the multicolor raster graphics device of the present invention, graphics data representing an image projected on a raster display screen is stored in a memory means, while a plurality of color registers are stored with colors (and colors) corresponding to different colors. Preferably, the value of data (luminance) is stored. A graphics shift register is connected to said memory means for receiving graphics data therefrom. From the graphics shift register graphics data is shifted out in parallel bits in response to a periodic clock signal from the timing means. It is also characterized in that the number of bits shifted out at one time can be changed. Playfield encoding logic connected to the graphics shift register receives the shifted out graphics data and selects one of the plurality of color registers accordingly. The contents of the selected color register are sent by video signal generating means to a raster display screen to display a color image. Furthermore, in order to achieve the above characteristics, a graphical
Mode selection means are provided for controlling the number of bits shifted out of the shift register at one time and the number of color registers that may be selected by the playfield encoding logic. The advantage of the present invention is that it avoids unnecessarily large data words as much as possible, dynamically changes processing according to the type of color required depending on the part of the image, and multi-purpose data processing with less wasteful data processing. It is possible to create a color raster display. [Example] The present invention will be described below based on the drawings. A. General Description (1) System Components FIG. 1 shows the constituent devices of the data processing system of the present invention. The system 10 includes a console 12, a printer 1
4. It includes a small diskette unit 15, a cassette peripheral device 16, a game control device (joystick) 18, and a display device (preferably an ordinary television receiver) 22. console 12
connects a suitable radio frequency signal corresponding to one of the television channels on line 20 to a television antenna terminal (not shown) of display device 22. System 10 has two basic modes of operation. In the first mode, system 10 operates as a programmable general-purpose computer, and in the second mode, system 10 operates as a video game device. In the first mode, the personal home data processing system is intended to be used for many information management tasks. For example, with appropriate programming, the system can perform tasks such as balancing a checkbook, planning meals, managing pawn and inventory securities, and maintaining mailing lists of family and friends. These tasks are just some of the information management capabilities of the system. Furthermore, by displaying text and charts on a display device along with audio, a variety of interactive educational materials can be provided. A keyboard 24 and display device 22 allow user interaction with the system. While operating system 10 in this mode, a user may use one or more peripheral devices 14-16 to store or retrieve information. Display device 22 provides the user with systematically presented graphical information (typically an alphanumeric display). This information is transmitted via transmission line 20 to display device 22 by electronics included in console 12 . In the second basic mode, system 10 operates as a video gaming device, providing games to be played by one or more players. Console 12 has the necessary circuitry to generate display objects that can be viewed by a user on display device 22. Some of the display objects are
These objects can be moved or adjusted in response to the user's operation of the player console 18, and are hereinafter referred to as "movable objects." Other objects are relatively fixed, such as alphanumeric graphics, borders, and the like. These objects described below will be referred to as "playfield objects" hereinafter. Display device 22 is a raster scan display of the type that uses an image forming beam across the screen along a plurality of successively scanned horizontal lines. Beam movement is synchronized to the video data provided by console 12 by conventional horizontal and vertical synchronization signals, including signals forming horizontal and vertical blanking intervals. The selection between the two basic modes of operation described above is made by providing the system 10 with an appropriate program. This is done in two ways. First, a certain program is created in advance and stored in, for example, the disk device 15 or the cassette device 16. The electronic circuitry of the console 12 includes a memory containing sufficient resident instructions to allow a user to recall stored information, thereby allowing the console 12 to
Loads the requested operating program into a random access memory (RAM) section located at . Selection of an operating mode, on the other hand, is accomplished by providing system 10 with a read only memory (ROM) cartridge containing the requested operating program. FIG. 2 shows a housing portion 32 for housing a ROM cartridge 33 when the removable top portion 30 of the console 12 is removed. Additionally, the console 12 includes a system 10
A memory receiving portion 34 is provided which accommodates an additional memory package 36 for expanding the memory of the memory. One or both receiving parts 3 of the console 12
According to the program contained in the ROM cartridge 33 inserted into the system 10, the system 10 can be used as a programmable general-purpose computer system or a video game device. A block diagram of system 10 is shown in FIG. The parts included in the system console 12 (dotted line in FIG. 3) include a microprocessor unit (MPU) 40, a memory device 42, an object and graphics generator 44, an audio generator 46, and a peripheral interface device 50. Contains. Furthermore, the console 12
includes a video summer 52 that receives and combines color, luminance and composite synchronization information from an object graphics generator;
Produces a composite signal that is sent to RF modulator 54. The RF modulator also receives the audio signal generated by the audio generator 46 and produces a suitable radio frequency signal containing graphic and audio information, which is transmitted via signal line 20 to the display device 22. . MPU40, memory device 42, generator 4
4, 46 and peripheral interface device 50,
They are interconnected by a bidirectional data bus 60 and an address bus 62, so that data and instructions can be directly transmitted between them. Each device coupled to buses 60, 62 includes a control section that includes data buffer registers, selective address decoding circuitry, and other circuitry necessary for device control and information utilization. Contains elements.
Details of these control sections will be described later. Timing signals, including various clock signals described below, are generated by timing device 58 and sent to various devices within console 12 for use as needed. The memory device 42 is of the ROM type and includes a ROM cartridge 33 and an additional memory package 36.
Includes both RAM type memories. Memory device is up to
Can store 64K characters in memory. Each character is 1 byte (8 bits). Therefore, address bus 62 is 16 bits wide to provide sufficient addressing capability for maximum memory capacity. Of course, data bus 60 is 8 bits wide. Both MPU 40 and object graphics generator 44 can access memory device 42. However, to avoid accessing memory simultaneously by these devices, memory access priorities are
given to the generator. This is done as follows. Prior to a memory read cycle by generator 44, a HALT command is communicated to MPU 40 on line 64. The signal appearing on this line indicates the memory cycle that immediately follows.
This prevents the MPU 40 from accessing the memory device 42 during this time. data and address bus 60, 62 or
In addition to HALT line 64, an interrupt bus 66 connects object graphics generator 44 and peripheral interface devices 50 to MPU 40. The interrupt bus 66 transmits interrupt requests to the MPU 4.
0 to indicate the occurrence of an interrupt or MPU4
0 requests that a certain action be performed. For example, an interrupt signal may be transmitted by peripheral interface device 50 via interrupt bus 66.
It is transmitted to the MPU 40, and one of the peripheral devices 14 to 16
Indicates that information from someone has been received. This interrupt signal can be used with appropriate buffer registers. On the other hand, the signals generated by the peripheral device 50 are transmitted to the MPU 40, and from the peripheral interface device 50 to one of the peripheral devices 14-16.
Indicates that data transmission to one end has been completed. On top of that,
Peripheral interface device 50 communicates an interrupt signal to MPU 40 to indicate that one of keyboard switches 24 has been pressed and that the information of the pressed switch can be used for sampling by MPU 40. . Object Graphics Generator 4
The interrupt signal conveyed by interrupt bus 66 from MPU 4 provides information regarding the status of video blank time or other display timing information to MPU 40. Information transfer between console 12 and peripheral devices 14-16 is accomplished by serial I/O bus 70 under the normal management of peripheral interface device 50. As is clear from the explanation below,
Information is conveyed by bus 70 at a number of select mode data rates. (2) Object Graphics Generator Figures 4A and 4B show an object graphics generator 44, which includes a playfield object generator 44A (shown in Figure 4A) and a movable object generator 44B (shown in Figure 4A). 4B shown).
Playfield object generator 44A is connected to address bus 62 via address decoding device 80. Address decoding device 80 is configured such that certain counters and data registers are connected to data bus 60 or address 62.
to receive information from or bus 60 or 6
It contains the necessary logic circuitry to recognize, decode, and generate appropriate signals to selectively enable information to be provided to the computer. The playfield object in Figure 4A
One function of generator 44A is to offload many character generation burdens from MPU 40, including the transfer of video graphics information from memory device 42 to object graphics generator 44. Accordingly, playfield object generator 44A is programmable and performs direct memory access (DMA) operations, i.e.
Object graphics generator 44 from memory device 42 without intervention by MPU 40
Contains the ability to transfer graphic information to. Such DMA operations are directed by a set of instructions stored in memory device 42 and accessed continuously by playfield object generator 44A during graphics generation. these
The addresses required for a DMA operation are obtained from one of three mutually exclusive sources: display list counter 82, memory scan counter 84, or moveable object DMA counter 86. In the embodiment, each counter 82,
84 and 86 contain multi-bit buffer latches, which hold the most significant bits (MSBs) of the address.
and the remainder of the address (which is contained in a presettable digital counter section). Each counter section has sequential addressability. Display list counter 82 provides address signals for accessing storage locations in memory device 42, which contains a list of sequential instructions. This instruction provides information to the playfield object generator 44A representing where the graphics information is stored (in memory device 42) and how and when it is to be displayed. Each instruction is an 8-bit instruction (buffer) that is held temporarily while it is decoded.
The data is transferred to register 88 via data bus 60 . The contents of instruction register 88 are provided to DMA controller 90 by register output line 92. DMA controller 90 decodes instructions and generates the timing and control signals necessary to initiate and control various playfield generator functions. Each instruction produces one or more horizontal lines of graphical information as seen on display device 22, as described below. New instructions are not fetched from memory device 42 until the horizontal line of graphics information whose generation is commanded by the instruction currently held in instruction register 88 is completed. do not have. Therefore, the number of horizontal lines generated by each instruction must be counted. This is done by line counter 96. Information representing the exact number of horizontal lines of the playfield display to be generated is contained in the 4-bit portion of the instruction. This information is sent to the ROM94, and the ROM94
Convert the bit part to the actual number of lines to be generated. The line count produced by line counter 96 is equal to the contents of the line counter.
Digital comparator circuit 9 to compare with the total number (number of lines to be generated) supplied by ROM 94
8. If the count of line counter 96 is equal to the number of lines to be generated, a last line signal is produced by comparator circuit 98 and sent to DMA controller 90 on signal line 100. The DMA controller 90 thereby confirms that the instruction currently held in the instruction register 88 has served its purpose and that a new instruction has been fetched from the memory device 42 and the instruction - Register 88 is informed that it should be transferred. In FIG. 4A, a pair of buffer registers 1
02 and 104 are connected to the data bus 60. H-scroll register 102 and V-scroll register 104 hold information used during horizontal and vertical scrolling. register 1
The horizontal scroll information contained in 02 is transmitted to the DMA controller 90 by signal line 105. The information contained in V-scroll register 104 is sent to multiplexer circuit 108 which sends the V-scroll information to line counter 96 to preset it. Graphics information used to generate playfield objects is stored in memory device 42 in one of two configurations. 1st
In this configuration, the graphics information is contained in a number of sequentially arranged 8-bit bytes. These 8-bit bytes are stored in the playfield object during active scanning of each horizontal line.
It is linearly accessed one byte at a time by generator 44A. In the second configuration, the graphical information is contained in character blocks of 8-bit bytes arranged sequentially. Each of these blocks is typically an alphanumeric block.
Contains graphic information for characters or similar display objects. One byte of each block is transferred to the playfield object generator 44A during continuous horizontal scanning. This latter arrangement is more flexible because the same character can be generated multiple times in any display field by recalling the graphical information for the character when needed. To take full advantage of this latter feature, a block of character graphic information consists of a character base portion that indicates the portion of the memory device 42 that contains the character block, and a character name that indicates the specific character block in the memory portion. part and
It is accessed from memory device 42 using an address formed from line counter 96 which selects a particular byte of the character block. In this way, the playfield object
The generator has a character name register 110 and a character base register 112 for holding the name and base portions of character block addresses. As will be described below, during active scanning, memory scan counter 84 performs the following operations to access memory device 42:
Address signals are sequentially supplied to obtain the character name portion of the character address. The character name portion is transferred to character name register 110. The contents of the character name register are combined with the contents of character base register 112 and line counter 96 to access memory device 42 for graphics information. The information that is continuously transferred to character name register 110 during active scanning of the first horizontal line (used to obtain graphics information as described above) is used on a predetermined number of consecutive lines. In this way, rather than memory being accessed line by line, the information obtained during the first line is stored in display RAM 114 and
and is continuously accessed from there, furthermore,
It is transferred to the character name register 110 to generate a continuous horizontal line of horizontal blocks of characters or objects. Graphics information is stored in memory device 4 using address signals output from one of two signal sources.
2 and sent to the playfield object generator 44A. Address signals are generated from memory scan counter 84 or from character base register 112, character name register 110, and line counter 96. In either case, graphical information is displayed during the active horizontal line scan.
Only one byte is transferred at a time. As discussed in more detail below, there are times when graphical information displayed on one horizontal line should be displayed on one or more immediately following lines. In such a case, the graphical information for the first horizontal line is temporarily stored in display RAM 114 for access at consecutive locations specified by RAM address counter 116. Graphics information for the immediately next line is obtained from the display RAM 114,
This leaves the memory device 42 free so that the MPU 40 can use it. When graphics information from blocks located in various memory locations of memory device 42 is accessed, it is subsequently transferred to character name register 110, and
Information that is used as part of the address of stored graphical information for many subsequent lines. In this case, as each byte of address information is transferred to character name register 110, this byte is stored in display RAM 1.
14 and is temporarily stored. During the horizontal line immediately following the first horizontal line, address information is transferred from display RAM 114 to character name register 110. Using either of the above methods of sending address signals for accessing graphics information, the graphics information is sent to multiplex 120 and therethrough to playfield graphics shift register 122. Graphics information is stored in memory device 42 in response to address signals output by memory scan counter 84.
Under the management and control of the DMA controller 90, the graphical information is
It is transferred to the playfield graphics shift register 122. Each byte of graphics information is initially sent via data bus 60 to display RAM 114 where it is temporarily stored. Graphic information is immediately displayed on the display.
From RAM 114, it is transmitted via multiplexer 120 to playfield graphics shift register 122. When address information is temporarily stored in display RAM 114, the transfer of graphics information from memory device 42 is as follows. During the first horizontal line of a column of graphics to be displayed, memory scan counter 84 provides sequential address signals of the memory locations of address information to be transferred to character name register 110. Each byte of such address information is
Via data bus 60, this information is communicated to display RAM 114, where it is temporarily stored.
The currently memorized part-time job is displayed on the display.
It is read from RAM 114 and transferred to character name register 110. Character
Base register 112 and character name
The address signal formed by the contents of register 110 and line counter 96 is transferred to address bus 62.
and is used to access graphics information from memory device 42. The graphical information accessed in this way is transferred to the data bus 6.
0 to the multiplexer 120, where it is further transmitted to the playfield graphic
It is transmitted to shift register 122. Graphic information is transferred in the same way in the horizontal line immediately following this first line, except for the character name,
Address information communicated to register 110 is obtained from display RAM 114. In this way, the playfield graphics
Graphics information transferred to shift register 122 is communicated to playfield encode logic 124 in response to a clock signal provided by register controller 121. The register control device 121 receives the 2CLK signal (approximately 7.2MHz) from the timing device 58, and the DMA control device 9
0, this 2CLK signal or this
One of the three halves of the 2CLK signal (i.e., the 2CLK/2 or CLK signal at approximately 3.6MHz, or the CLK/2 signal at approximately 1.8MHz, or the CLK/2 signal at approximately 0.9MHz)
CLK/4 signal) to the playfield graphic shift register 122. When one of the four signals 2CLK, CLK, CLK/2, CLK/4 is communicated to the playfield graphics shift register 122, the graphics information it contains is transferred from there to the playfield encode logic 124. Register control device 1
21 shifts one or two bits for each clock pulse provided to the playfield graphics shift register 122. This will be explained in detail below. If the contents of the playfield graphic shift register are sent one bit at a time, the information is sent to the playfield graphic shift register via signal line 123a.
It is sent to encoding logic 124. At this time,
Signal line 123b is held at a logic zero. Both signal lines 123a and 123b are used when the contents of the playfield graphics shift register are sent two bits at a time. As discussed below, the selection of one or the other of these shift operations is accomplished by management signals generated by DMA control signals 90 in response to instructions received by instruction register 88. In response to the information signals on signal lines 123a and 123b, the playfield encoding logic operates on four signal lines.
Select one of PF0, PF1, PF2, PF3 and transfer the video information to the movable object generator 4 of the object graphics generator 44.
4B (Figure 4B). The selected signal lines PF0 to PF3 and the information appearing therein are displayed on the display device 22 (FIG. 3) as described below.
is used to select one of eight brightness values and one of sixteen color values corresponding to the playfield object to be displayed. FIG. 4B shows a movable object generator 44B which together with the playfield object generator 44A constitutes the object graphics generator 44 shown in FIG. In this embodiment, eight movable objects can be generated. The relative horizontal position and horizontal position of these movable objects when displayed on display device 22 is determined by the player.
Console 18 or keyboard and console tool
It can be varied in response to a user-generated input signal from switch 24. Four of the eight movable objects are player objects when system 10 is in game mode, and the remaining four movable objects are missile objects.
Objects, one missile object corresponds to each player object. Graphics information for each player object is stored in memory device 42 (FIG. 3) and contained in a number of contiguous arrays of bytes. Here, each byte corresponds to at least a respective one of the horizontal line scans of the display device 22. Similarly, the graphical information for each missile object is
stored in a number of contiguous arrays of bytes stored in memory device 42, each byte being one for each missile.
Contains two bits of graphical information for the object. Movable object generator 44B maps a continuous array of bytes of graphical information corresponding to each player object onto a display screen (not shown) of display device 22. This mapping of graphical information appears as vertical columns. Similarly, missile object graphic information is displayed.
The horizontal position at which each vertical column is to be displayed by display device 22 depends on information signals provided by player console 18 or keyboard and console switch 24.
Calculated by MPU 40. MPU 40 provides horizontal position information for each movable object to movable object generator 44B. This horizontal position information is used to effectively communicate moving object graphics information to display device 22 at the correct times during active horizontal lines. This is discussed in detail below. In FIG. 4B, movable object generator 44B is shown connected to data bus 60 by a plurality of connection elements. Data bus 60 is initially connected to each of eight movable object position (buffer) registers 140.
Each register 140 temporarily stores information transferred thereto from the MPU 40 and representing the horizontal position of the corresponding object to be displayed on the display device 22. The contents of each position register 140 are communicated to a corresponding comparator of eight digital comparators 142 via a corresponding line of eight signal lines 144. The horizontal count signal generated by sync generator device 146 is also connected to comparator 142 via signal line 148.
transmitted to. The sink generator device 146 has a timing device 58 (FIG. 3) at the input terminal 150.
Receive the 2CLK signal given by. The sink generator device 146 includes a plurality of conventional digital counters connected in series, the counters being generated by the timing device 58.
Count 2CLK signals and make horizontal and vertical sync signals. The horizontal and vertical sink signals are
Combined to create a composite sink. Horizontal and vertical sync counters are connected to conventional decode circuitry consisting of combinational logic and are used to time and control the various logic and circuitry of movable object generator 44B. Generates vertical (H-count and V-count) signals. In FIG. 4B, data bus 60 is connected to eight conventional parallel-serial graphics shift registers 152. In FIG. The four graphics shift registers 152 are four pieces of player object graphics information, each 8 bits in size. The remaining four graphics shift registers 152 are 2 bits in size and are for missile object graphics information. Graphics registers 152 receive graphics information in parallel from data bus 60 and convert the information to serial video signals. 4 player graphic shift registers 15
A video signal from each of the two appears on each of the four signal lines 154a. Signal line 154a
is player graphic shift register 15
Similarly, four signal lines 15 correspond to each of
4b corresponds to one of the missile graphic shift registers 152. Graphics register controller 156 includes eight
A shift pulse is generated on signal line 158 that is applied to a selected one of the two graphics registers 152. When a shift pulse is received, shift register 152 sequentially shifts its contents onto its corresponding video signal line 154a or 154b. If the horizontal count signal on signal line 148 (corresponding to the horizontal position of the electron beam scanning the display device 22) is equal to the horizontal position information in any of the position registers 140, then the shift register command signal is output to the appropriate comparator. 142 to register controller 156. Register controller 156 then provides a shift pulse to the corresponding graphics register 152, and the selected graphics register transfers its contents to signal line 154a (in the case of player graphics).
or 154b (for missile graphics)
sequentially supplied to one of the following. Graphics information contained in graphics register 152 is converted to video data and communicated to collision detector 164 and priority encoder 166 on signal lines 154a-154b.
Also, a collision detection device 164 and a priority encoder 166
In addition, playfield graphics are supplied via signal lines PF0-PF3. The eight video signal lines 154a and 154b and the four playfield graphics video signal lines PF0-PF3 are compared with each other by a collision detection device 164 that detects the simultaneous occurrence of video data on any two lines. be done. In this way, collisions between any of the movable objects or between any of the movable objects and the playfield object are detected. If such a collision is detected, a signal representative of the collision is communicated to one of sixteen 4-bit buffer registers 165. In this register, the signal is
It is temporarily stored until accessed by MPU 40. When one of the movable objects overlaps another movable object or a playfield object, the priority encoder 166 determines which of the simultaneously occurring objects appears on top of the other object (i.e., the display device 22 before the other object). (appears in). In this way, movable objects (e.g. airplanes) are moved behind playfield objects (e.g. clouds) and are erased by them, but appear in front of others. This decision is based on MPU40
via the data bus 60 to the priority register 168.
This is done in response to information sent to Priority register 168, which is connected to data bus 60 like the other registers, receives information in response to register selection signals generated by register selection device 200, as described below. No such determination is necessary between a player object and its corresponding missile object. That is, the player object and its corresponding missile object are typically spaced apart from each other. Conversely, as detailed below, a player object and its corresponding missile object are the same color and have the same brightness characteristics since there is no need to distinguish them even if they overlap. .
Thus, each of the four player graphics signal lines 154a is connected to its corresponding missile graphics line 1 by OR gate 170.
It is OR-linked with 54b. The logical OR combination performed by gate 170 is transmitted over four lines 172 to priority encoder 166. Priority encoder 166 has 8
1 input line (i.e. 4 playfield graphics lines PF0-PF3 and 4 moving object graphics lines 17)
2) Monitor and place graphics on which line.
Depending on whether the video appears, the encoder 16
6 selects only one of line 172 or PF0-PF3 to output mutually exclusive encoder output lines 1-8.
It is transmitted to the color-brightness selection device 178 via. The priority encoder thus determines which of the two or more concurrent object videos should be displayed. If no graphics information is provided to priority encoder 166, or if only the PF0 signal line is active, encoder output line 1 is active and selects color-luminance information. Color - Brightness register selection device 178 has 8 colors -
It serves to select one of the brightness (buffer) registers 176. Each color-luminance register 176 is
The information sent by MPU 40 via data bus 60, namely the brightness (3 bits giving 8 selectable levels) and color (16
(4 bits) giving the selectable colors of the image. The color-intensity register 176 selected by the color-intensity register selector 178 has a 3-bit portion representing the intensity to be converted to an analog voltage level by the register selector 178 (in a well-known manner). . This voltage level (brightness)
is connected to video summation device 52 via brightness line 180.
and finally to the RF modulator 54.
(FIG. 3) and is sent to the display device 22. The four bit contents of selected register 176 representing the color are communicated by device 178 over four signal lines 184 to delay line tap select device 182. The tap selection device 182 is 4-16
It is a decoder. Information appearing on signal line 184 selects one of sixteen mutually exclusive output lines 186 of tap selector 182. Analog delay line circuit 190 receives at input terminal 191 a color clock signal generated by timing device 58 (FIG. 3). Delay line circuit 190 includes a number of well-known analog delay devices to effect relative phase shifting of the signals received at input terminal 191. The phase-shifted signals are output to the 16 output lines 19 of the delay line circuit 190.
Appears in 2. Each output line has a signal that is phase shifted by a predetermined amount with respect to the color clock and other output lines. These output lines 19
2 is provided to AND gate 194. Each output line 192 is ANDed with a corresponding one of the tap select output lines 186, thus selecting one of the phase shifted signals. these
AND gate 194 is connected to OR gate 196 which in turn sends the selected signal to video summation device 5.
Send to 2. The chrominance signal is combined with a luminance signal appearing on line 180 and a composite sync signal generated by sync generator 146 to form a composite display signal, which is transmitted to the display device via RF modulator 54 and terminal line 20. Sent to 22nd. Information sent from MPU 40 to the movable object generator is managed by register selection device 200. Typically, an address indicating the register to be selected is connected from address bus 62 to register selection device 200, where the address is decoded. The selection device 200 combines the decoded address and the read/write (R/W) signal from the MPU 40 to write data to or read data from the selected register. For example, for a "write" command specified by the first binary level of the R/W signal, the register specified by the address on data bus 62 (e.g., one of the horizontal position registers 140) is
By the register selection device 200, the data bus 6
The information present at 0 is received and stored while the R/W signal remains intact. Also, for a "read" command specified by the R/W signal at the second binary level, the contents of the selected register (eg, one of the 16 collision detection registers 165) are read by the data bus 60. MPU4
Sent to 0. Graphic information is MPU40 as mentioned above.
and independently of MPU 40, are transferred to each graphics register 152 by the playfield object generator. Generally, in cases unrelated to the MPU 40, the following procedure is performed. Within each horizontal blanking interval, five scheduled periods are established for the playfield generator to transfer graphics information from memory device 42 to graphics register 152. 4 of this period
One period is for transferring graphics data to four player registers, and one period is for transferring 1-byte (8 bits) in parallel to four 2-bit missile graphics registers. will be carried out. DMA control device 90
(FIG. 4A) is a sink/generator device 46.
A HALT signal is provided to MPU 40 and DMA register selection logic 202 in response to the decoded horizontal count information from DMA register selection logic 202 . The HALT signal is
The MPU 4 instructs the playfield object generator to perform a fetch in the immediately next memory cycle time of the memory device 42.
Inform 0. Therefore, the mobile object generator's DMA register selection logic 202
uses the HALA command in combination with the horizontal counter (H-counter) decode signal so that the register corresponding to the scheduled period is
be able to accept the information that appears. DMA controller 90 then initiates a memory "fetch" routine by providing the contents of movable object DMA counter 86 to address bus 62 and issuing a read command to memory device 42. Thereby the memory device 42
sends the contents of the memory location indicated by the address appearing on address bus 62 to data bus 60. At the same time, the DAM register selection logic device 20
2 generates a signal on one of the five selection lines;
It is routed through OR logic 204 to the selected graphics register 152, which accepts and temporarily stores the information appearing on data bus 60. (3) Audio Generator FIG. 5 shows an audio generator 46 of the present invention. Audio generators are used to generate many audible sounds, such as signal tones, for example. Such sounds may produce effects such as gunshots, explosions, motors, gongs, and the like. The audio generator 46 includes a polynomial counter section 210 and a divide-by-N section.
by-N) counter section 212, audio controllers 214a-214d, and an 8-bit data register 216 supplied with information by MPU 40 via data bus 60. The contents of data register 216 are used to select the particular audio to be generated by audio generator 46. Polynomial counter section 210 includes three polynomial counters 220, 222, and 224, which are 4, 17, and 5 step polynomial counters, respectively;
Each is used as a noise generator. Each counter receives a CLK/2 signal (approximately
1.8MHz). Each counter 220,
222 and 224 are gates 220a and 222, respectively.
a, 224a. Each counter essentially consists of a gate 220
A-224A is a shift register with two stages connected to A-224A. Preferably gate 220a-2
The stages to be connected to 24a are selected such that the counter obtains a maximum number of counting stages 2 ^N -1. where N is the number of counter stages. For example, the 4-stage counter 220 uses the final two stages, whereas the 5-stage counter 224 uses the final and third (ie, intermediate) stages.
In the 17-stage counter 222, the final stage and the fifth (ie, 12th) stage from the final stage are connected to the gate 222a. Further, the 17-stage polynomial counter 222 is configured to register 216 with bit D.
Gate 2 to one input of the inner stage of the counter (shift register) 222 when 7 is a binary 1
The feedback loop has a switch 222b which shortens the feedback loop by connecting 22a. The output of each polynomial counter is connected to each audio controller 214a-214.
d. The N-divide counter section 212 consists of four essentially identical N-divide counter circuits 226a--
226d. Each circuit has an N-divided counter 228, and the division of this counter 228 is
It is controlled by an 8-bit data register 230 connected to data bus 60 for receiving information from MPU 40. Each data register 2
30 is connected to and supplies its contents to its corresponding counter 228 to determine the final frequency output of the counter. The clock frequency used to drive each N-divided counter 228 is determined by the selection switch 231a-
231d. These switches outputs D3, D4, D5, D of register 216.
Controlled by 6 binary states. For example, divide-by-N counter 228 of circuit 226a may be driven by a clock-A (CLK-A) signal provided on clock input line 232 (when the D0 and D3 outputs of data register 216 are logic zeros). Moreover, the CLK/2 signal of the input terminal 226 is
When the D3 output of register 216 is a logic one, it is selected to drive counter circuit 228. In this embodiment, the CLK-A signal is approximately 64 KHz, while the CLK-B signal is approximately 15 KHz. CLK
-A and CLK-B signals are timing device 58
(Figure 3). The final frequency output of each divide-N circuit 226a-226d is connected via lines 236a-236d, respectively, to one or more audio controllers 214a-214d as shown. The signals provided to each audio control device 214a-214d are selectively mixed and
18 and is sent to the RF modulator 54 (FIG. 3). The structure and function of each audio control device are as follows:
Details are given below. Audio generator 46 includes an address decoder 238 that receives as input signals on address bus 62 and the R/W signal line. Address decode unit 238 decodes addresses and manages the transfer of information from data bus 60 to designated registers in the same manner as register select unit 200 does. The address and R/W signals are used by address decoder 238 to select one of the audio generator's data registers (eg, one of 8-bit data registers 230) and to select the selected register. receives and stores information on data bus 60. FIG. 6 shows a more detailed audio control device 21.
4a is shown. Each audio control device 214
Since the structures of audio controllers a-214d are essentially the same, the description of audio controller 214a can also be applied to other audio controllers. However, the circuit structure of the audio control devices 214c and 214d is as follows.
Although identical to each other, the structure is slightly different from that of the audio control devices 214a and 214b, as will be pointed out below. Audio controller 214a of FIG. 6 includes an 8-bit data register 240 having output lines 240a-240h by which the contents of the register are sent to various control circuits. Polynomial counters 220-224 (Figure 5)
are connected to audio controller 214a by signal lines 242, 244, and 246, respectively. Input lines 242, 244 are connected to a two-way selection switch 248, while signal line 246
is connected to the data D input of D-type flip-flop 250. N division circuit 226a
The low-pass clock frequency from (Figure 5) is
Through signal line 236a, flip-flop 2
50 clock C input. The Q output of flip-flop 250 is connected to two-way select switch 25.
4 and is sent to AND gate 252. Gate 252, which has as another input a low pass clock signal appearing on signal line 236a, is connected to the clock C input of D-type flip-flop 256. The data D input of flip-flop 256 is connected to a two-way select switch 258. The high pass clock is provided by signal line 236c from divide-by-N circuit 226c to audio control signal 214a and to the clock C input of flip-flop 260. flipflop 26
The zero data D input is connected to the Q output of flip-flop 256. flipflop 26
The 0 Q output is connected to the volume control circuit via gates 262 and 264. This is the difference between the audio control devices 214a, 214b and the audio control devices 214c, 214d. In particular, the audio controllers 214c and 214d include a high-pass clock input, a flip-flop 26
0, has no gate 262, or switch 266. That is, the output Q of flip-flop 256 is sent directly to gate 264. The gate 264 is a MOS transistor 268
AND gate 266a- driving a-268d
266d. The volume control circuit consists of a gate and a resistor R,2 that are selectively used to control the amplitude.
An effective digital-to-analog converter using a combination of R, 4R, and 8R, which converts the analog output according to the digital input to the AND gate 266a.
-266d. Select signal line 2
40a-240d and AND gate 266a-
266d depending on the contents of that portion of data register 240. The outputs of polynomial counters, such as counters 220, 222, and 224, have very wide frequency spectra and generally provide "white" noise. First the audio control device 214a-21
4d acts as a low pass filter to selectively limit the frequency content of the signal provided to audio line 218. flipflop 25
A low-pass clock associated with 0,256 and appearing on signal line 236a is connected to input line 242,2.
The polynomial counter signal appearing at 44,246 is
Works like a “sample”. The output Q of each flip-flop 250, 256 cannot be changed faster than the sampling rate (ie, the low pass clock). The frequency sent to gate 264 by the flip-flop is therefore limited by the rate at which the flip-flop is clocked. This speed is determined by the divide-by-N circuit 226a. Additionally, all audio controllers have this low pass filter function, and the sampling rate of audio controllers 214b-214d is provided by N-divide counter circuits 226b-226d, respectively. Furthermore, audio control circuits 214a, 214b
has a high pass filter consisting of a flip-flop 260 and a gate 262. The Q output of flip-flop 256 is connected to signal line 236.
is sampled by flip-flop 260 at a rate determined by the high-pass clock signal appearing at b. In addition, flip-flop 25
The 6,260 Q outputs are provided to an exclusive OR gate 262. Data D of flip-flop 260
If the signal applied to the clock input changes significantly faster than the signal applied to the clock C input, gate 26
2 is the data input (i.e. flip-flop 2
56 Q output) to selection switch 266. However, if the signal provided to the clock C input of flip-flop 260 is at a higher frequency than the signal provided to its data D input (i.e., the Q output of flip-flop 256), the Q output of flip-flop 260 will be at a higher frequency than the signal provided to its data D input. The trend continues, and since both inputs of exclusive OR gate 262 are nearly equal, it produces a very small output.
The circuitry of flip-flop 260 and exclusive OR gate 262 act as a single high-pass filter, passing noise. The minimum frequency of the noise is
Set by a high pass clock signal appearing on signal line 236b. Only audio controllers 214a, 214b have such high pass filters. The signals selected by each audio controller 214a-214d (FIG. 5) are divided into four channels.
is sent to audio line 218. Four channel audio line 218 sends the selected signal to RF modulator 54 (FIG. 3).
RF modulator 54 receives the composite video and audio signals to form radio frequency signals and sends the video and audio information to display device 22 . The signal is transmitted to the display device 2
2, the audio signal is extracted from the radio frequency in well known manner and sent to conventional audio conversion equipment (eg, speakers, not shown). The audio signal is converted to sound by an audio conversion device (not shown). (4) Peripheral interface device The peripheral interface device 50 in FIG.
It serves to sample and temporarily hold the information sent to it by the player's controller and keyboard and console switches 24 until the MPU 40 is ready to receive the information signals. For example, information provided by pressing a key requires a peripheral interface device to inform MPU 40 that the information is currently available. Therefore, the peripheral interface device 50:
Generates an interrupt signal sent to MPU 40 via interrupt bus 66. Thereafter, the MPU 40 executes an interrupt routine to issue an interrupt, and the peripheral interface device 5 which holds information.
Read the appropriate buffer register (not shown) for 0. Peripheral interface device 50 connects peripheral devices 14, 15, 16 via a serial (I/O) bus.
It further includes logic circuitry for transferring information between the peripheral interface device 50 and the peripheral interface device 50 . (5) Memory Device FIG. 7 shows a typical configuration of the memory device 42. Addresses are coupled to the memory device by address bus 62. Instructions or data are transferred to and from the memory device via data bus 60. Memory device 42 includes a memory storage section 2 that includes both read-only memory (ROM) and random access memory (RAM).
It has 80. In general, the above ROM and
RAM A portion of both types of memory resides in the system. The resident portion of ROM type memory contains operating system instructions stored in ROM location 282. These operating system instructions include peripheral interface devices,
Peripheral devices 14-16 provided therein, or
Contains the instructions necessary to process data to and from keyboard or console switch 24. This resident ROM supplements a program ROM cartridge 33 (FIG. 2), which contains operating system instructions for the specific use of the entire system. Similarly,
RAM section 284 is RAM module 3
The module 36 is added to expand the memory capacity of the memory device 42. Furthermore, the various circuits described so far include
For example, character name and base registers 110, 112 (FIG. 4A), graphics register 152, and collision detection register 165.
(Figure 4B) and audio generator 46
8-bit data registers 216, 230, 2
There are many data registers, such as 40 (Figures 5 and 6). To MPU 40, these registers appear as if they are part of memory device 42, each addressable by a specific 16-bit address. Some of those registers are MPU
information can be received from 40 by data bus 60;
Others can be read by MPU 40, some receive information from MPU 40 via the data bus, and
Information can be transferred to the MPU 40. Accordingly, these registers are shown in FIG. 7 as sections 281 in each successive memory location of memory device 42. Each memory location in section 281 can be identified by a particular address. in this way
The MPU 40 is located in a section 28 of the memory device 42.
Similarly to writing data to and reading data from section 0, writing to (transferring data to) or reading from (transferring data to) a memory location (i.e., a register) in section 281 (transferring data from a memory location) transfer).
That is, addresses sent by MPU 40 to address bus 62 address memory locations, and read or write commands are sent via R/W signal lines (FIG. 3). Section 280 of memory device 42 consists of ROM and RAM type memory, as described above, and
Arbitrarily divided into blocks or groups of contiguous memory locations to sequentially store related instructional graphics or other information. For example, the memory location consisting of memory block 282 is
Contains instructions. These locations are typically addressed by MPU 40. Similarly, the memory location comprising memory block 284 stores DMA display instructions. That is, these instructions are used by the playfield object generator section of the graphics generator 44 to select and format a field of display objects (i.e., characters, etc.), and to output them to the display device 22. send to Similarly, the actual graphics information, namely playfield object graphics, movable object graphics, and character graphics, are stored in consecutive memory locations forming memory blocks 286, 288, and 290, respectively. To obtain a graphic representing the character name, select Character Graphics block 290.
The list of character names used by the playfield generator to address memory locations in memory block 292
are stored in contiguous memory locations represented as . These memory locations are typically
Play field as well as with MPU40
addressed by the object generator (Figure 4A). The various RAM memory locations or data registers of memory location 42 are manipulated in a conventional manner to transfer information to and from particular locations in the memory device. For example, a 16-bit address is gated onto address bus 62,
When an 8-bit data word is sent to data bus 60 and the R/W signal line is placed in the write state, information is transferred to memory device 42.
Similarly, read (or "fetch") operations are performed in much the same way. Reading is performed by the object graphic generator 44.
(i.e. playfield object
generator), this readout is preceded by a signal on the HALT signal line,
The MPU 40 prevents read operations from occurring at the same time. (6) Serial (I/O) Data Bus The peripheral devices 14-16 and peripheral interface device 50 shown in FIG. 3 are interconnected by a serial (I/O) bus 70. This bus is
It is a reversible conducting bus such that information is transferred to and from each device over the bus. As shown in more detail in FIG. 8, bus 70 consists of several signal wires for specific purposes. wire 3
00 and 302 transfer interrupt signals from peripheral devices to the MPU 40 via the peripheral interface device 50. Signal wire 304 sends motor control signals to cassette peripheral 16 to operate a tape drive motor (not shown). Audio signal wire 306 connects electronic audio signals from cassette peripheral device 16 to peripheral interface device 5.
Send to 0. The remaining signal wires connect peripheral interface device 50 and peripheral device 14-1 connected to bus 70.
6, transmits digital data and status information serially at a data rate (baud) selected by either MPU 40 or a peripheral device. In particular, signal wire 308 sends command signals in a first binary state to peripheral devices 14, 15 and serial (I/
O) Inform peripheral devices 14, 15 of the presence of command/data information on bus 70; signal wire 310
The peripheral interface device 50 and the peripheral device 1
A reversible data clock signal is sent between 4 and 16. The reversible data clock signal carried by signal line 310 originates from peripheral devices 14-16 and is sent by peripheral interface device 50. Signal wire 312 connects peripheral devices 14-16
Serial data from peripheral interface device 5
Send to 0. The serial data of signal 316 is sent to peripheral device 1.
Signal line 314 connects the data clock signal to peripheral device 14 for use in transmitting the data clock signal to peripheral device 4-16.
- Send to 16. Finally, the READY signal is sent to the peripheral devices 14-16, and the peripheral interface device 5
0 indicates that it is in a state of receiving information from peripheral devices 14-15. B. Object Graphics Generator In order to fully understand the present invention, it is necessary to
First, the instruction set for the operation of the graphics generator 44 will be explained. Each instruction has an operation code,
some flag bits, and 2-byte
consists of an address (omitted from some instructions) that is used to directly connect the object graphics generator to another section of memory (which also contains display instructions or graphics information). It will be done. With these instructions, the Object Graphics Generator 44
generates graphics information without substantially any dependence on MPU 40. The operation, address mode and graphics generation code of the display instruction are related to each other and constitute the main signals of the playfield object generator's DMA controller 90 when the instruction is decoded. 1 Display Instructions Display instructions are operated and executed solely by the graphics generator 44. These are microprocessor
It's not an instruction. When properly programmed with these instructions, object graphics generator 44 produces the desired display format for display on display device 22. line, border,
Playfield objects such as characters can be displayed on the display device 22 with little, if any, intervention by the MPU 40 during the graphics generation process. the result,
MPU 40 is relieved of its normal object graphics generation duties and can perform other processing operations. The instruction is 1 or 3 bytes. The 1-byte instructions are used to determine the manner in which playfield object graphic information is displayed by the display device 22, and are typically display mode control instructions. be. The 3-byte instruction is typically a 1-byte instruction that the generator 44 "jumps" to the location of another list display instruction or graphical information in the memory device 42. Location, object generator 44
This is a continuation of two bytes of address information specified by . Once a particular instruction is sent to instruction register 88 and decoded by DMA controller 90 (FIG. 4A),
Output signals are generated to control the selection and transfer of graphics information from predetermined memory locations in memory device 42 to video summer 52. This information is then sent by RF modulator 54 to display device 22 (Figure 3). The instructions are formed as shown in the table. Table - Playfield Object Generator Instructions Display Mode Instructions: These instructions are used to store graphics information from memory device 42 (i.e. character
(by addressing indirectly using a name or by addressing directly) and sent to the playfield object generator (FIG. 4A) and further to the display device 22.
It is up to you to determine how the information will be sent.
Display mode instructions are
Register controller 121 selects the clock signal provided to graphics shift register 122 so that a horizontal line of graphics information is displayed as multiple horizontal lines on display device 22, or graphics information is transferred to graphics register 122. to the playfield encode logic circuit 124 one at a time.
Bits or two bits at a time may be transferred. Instruction number 1 generates one or more blanking horizontal lines. Instructions 2-9 generate playfield objects by sending graphics information directly from memory device 42 to display device 22. Instructions 10-15 generate a horizontal block of characters using a list of character names using the indirect addressing method. Inclusive data bits D0-D3 form the instruction's operation code. An "X" in any bit position of an instruction indicates whether that bit is not in question or has some other use.

[Table] Explanation: This instruction is for blank
Generate 1 to 8 horizontal lines of video.
The number of horizontal lines is data bits D4-D6
(eg, 000 is one horizontal blanking line and 111 is eight horizontal blanking lines). The color and intensity of each line is determined by the information contained in the color-intensity register. color-
The brightness register is connected from the playfield object generator 44A (FIG. 4A) to the movable object generator 44B (FIG. 4B).
The selection is made by the signal on line PF0 sent to (Figure). Playfield encode logic circuit 124 (Figure 4A) to priority encoder 1
66 (FIG. 4B), no graphics information is sent. In this state, if there is no movable object graphic, the priority encoder 166
causes its output 9 to successively select a background color-intensity register (one of registers 176) corresponding to the number of lines to be generated.

[Table] Explanation: Graphic information is stored in the memory device 42.
(Fig. 3) to the playfield graphic shift register 122 of the playfield object generator (Fig. 4A).
to, one at a time during active scanning of horizontal lines.
Bytes are transferred. The information is then shifted out of the shift register one bit at a time and appears as video data on signal line 123a to playfield encode logic 1.
24 to the priority encoder via the PF0 or PF1 signal line, depending on the logic state of the data bits. The clock signal sent to the shift register is 2-CLK (approximately 7.2MHz).

Explanation: This instruction requires that graphics shift register 122 has CLK supplied thereto by register controller 121 and that graphics information is transferred to register 12.
Essentially the same as instruction No. 1 above, except that 2 bits are transferred at a time from 2.
is the same as In this way, the play field
Four output lines of encode logic circuit 124
One of PF0-PF3 becomes active.

[Table] Description: Instructions except that the graphics information for one entire horizontal line is stored in display RAM 114 to be sent to graphics shift register 122 during the generation of the first horizontal line. Shion No.4
is almost the same as instruction No. 2 (i.e., shift clock = CLK; data is shifted out of shift register 122 two bits at a time), and the immediately following horizontal line is stored in display RAM. Generated using graphics.

[Table] Explanation: Essentially the same as instruction No. 2 except that the data is sent one bit at a time.

[Table] Explanation: Shift clock = CLK; data is
It is shifted one bit at a time and displayed in two consecutive horizontal lines. Instruction No.7

Table Description: Shift Clock = CLK/2: Data is shifted two bits at a time and displayed on four consecutive lines.

Table Description: Shift Clock = CLK/2; Data is shifted one bit at a time and displayed on four consecutive horizontal lines.

Table Description: Shift Clock = CLK/4; Data is shifted two bits at a time and displayed on eight consecutive horizontal lines.

[Table] Explanation: This and the following instruction No.
11 to 15, Instruction No. 2-9
Similarly, the graphics data is stored from the memory device 42.
Graphics information transferred to generator 44 is transformed. Instruction No.10-15
differs from the previous instructions in the procedure used to obtain graphics information from memory device 42. Essentially, this and instructions 10-15 are used to generate a swath of video to be displayed on display device 22. Each horizontal row contains 20 or 40 characters, and each character swath is 8, 10, or 16 vertical lines high. Additionally, these instructions (similar to instructions No. 2-9 above)
Specify the clock speed for (Figure 4A),
and specifies whether information is sent from register 122 to encode logic 124 one or two bits at a time. Instructions Nos. 10-15 access graphics information from memory device 42 through a reversible address structure described below. According to instruction No. 10, (1) Graphic shift register 122
CLK signal, (2) send information one bit at a time from register 122 through signal line 123a, (3) generate 20 characters per horizontal swath, and (4) generate 16 consecutive characters for each column. (5) make two consecutive horizontal lines of the graphic display the same (e.g., the second line of a pair is equal to the first
(Includes the same graphic video as Line).

[Table] Explanation: This instruction is the same as instruction No. 10, except that none of the horizontal lines of the graphic information are paired. This instruction uses only eight consecutive horizontal lines per swath.

[Table] Description: Shift Clock = CLK; Graphics information is sent from graphics register 122 two bits at a time. Each two consecutive horizontal lines are the same. 16 continuous horizontal lines are displayed.

[Table] Explanation: This instruction is the same as instruction No. 12, except that none of the horizontal lines in the graphic information are overlapping. Only eight consecutive horizontal lines are displayed.

[Table] Description: Shift clock = 2CLK; Graphic information is shifted one bit at a time. 10 consecutive horizontal lines will be displayed.

[Table] Description: Shift clock = 2CLK; Graphic information is shifted one bit at a time, and eight consecutive horizontal lines are displayed. B jump instruction

[Table] Explanation: This is a 3-byte instruction. The byte containing the operation code is followed by two additional bytes, which constitute the address of the memory location (in memory device 42) containing the next consecutive instruction to be executed by graphics generator 44. do. When decoded by DMA controller 90 (FIG. 4A), control and timing signals emerge from which the two bytes following the instruction are sent from memory device 42 to display list counter 82. C Flag Bits Data bits D7-D4 of any instruction are used in addition to the operation specified by the operation code (data bits D3-D0).
Instructs to take another action depending on the logical state of The flag bit is a blank instruction (instruction No. 1),
It is ignored in Jump Instructions (Instruction No. 16). Data Bit D4 = 1 Description: Begins horizontal scrolling of the display. Data Bit D5 = 1 Description: Begins vertical scrolling of the display. Data Bit D6 = 1 Description: If one of Display Mode Instructions No. 2-15 is used, this flag bit represents the instruction as a 3-byte instruction and Luxion Bite
This indicates that the two consecutive bytes (including bits) are sent to memory scan counter 84.
Logic 1 if jump instruction (instruction No. 16 only) is used
(D6=1) transfers the next instruction from memory device 42 to instruction register 88 (fourth A
This indicates that the object generator 44 waits until the end of the next vertical blanking period before sending to the blank line in FIG. Data Bit D7 = 1 Description: Enables interrupts generated by the graphics generator. 2 Display Graphics Generation In addition to this overview of the instruction data bits, a more detailed description of the graphics generated by object graphics generator 44 in response to various instructions will be provided. a. Playfield Object Generation Generally, only playfield objects are generated in response to and under the control of an instruction set. The instructions direct where the graphical information to be sent to display device 22 is located in memory device 42, how the transfer is to occur, and how the information is to be displayed. Typically, playfield objects (eg, alphabets, horizontal and vertical lines, etc.) are generated using one of two different methods. These two methods of object graphics generation will be described below as "memory map" and "character" display modes. Essentially, both display modes use graphical information stored in memory device 42. Both display modes send graphics information from the memory device to playfield generator 44A where it is converted to serial video information by playfield graphics shift register 122 (FIG. 4A). However, the techniques differ in how the graphics information is accessed from memory device 42 and will be discussed separately. (i) Memory Map Display Mode Graphics information is displayed, for example, in the playfield graphics block 286 (Figure 7).
are stored in memory device 42 in blocks of contiguous addressable memory locations such as . In Figure 4A, the playfield object generator operation is performed by MPU40 (Figure 3).
begins when writes a 2-byte (16-bit) address to display list counter 82. The MPU 40 also controls the DMA control register 101.
The playfield object generator 44A is enabled and begins operation. The data sent by MPU 40 to display list counter 82 is the address of the memory location (in memory device 42) containing the first instruction. Once the playfield object generator is enabled,
Control and timing signals are issued by the DMA controller to generate a HALT signal, which subsequently causes a read operation to read the contents of the memory location specified by the address issued by display list counter 82. via bus 60 to instruction register 88.
Typically, this first instruction will generate a number of blanking horizontal lines (ie, instruction No. 1). As each horizontal line is generated, the line counter 96
It is incremented by the controller 90. At the end of the last horizontal line specified to occur by the instruction, the instruction's data bits D6-D4 and line counter 96
Comparison circuit 98 performs a comparison between them. (Data bits D6-D4 are DMA controller 90
(under the control and management of signals from the MPX) via a multiplexer (MPX) 95 to a comparator circuit 98).
Comparator circuit 98 outputs a last line signal, which is sent to DMA controller 90 via signal line 100. During the horizontal blanking interval immediately following the last generated horizontal line, the DMA controller 9
0 generates a signal, which is displayed on the display.
The contents of list counter 82 are incremented by one and memory device 42 is addressed to obtain the next sequential instruction following the blank instruction just completed. Typically, when a playfield object instruction is displayed, the next instruction will be one of instructions No. 2-6 with flag bit D6 set to a logic one. It is one. That instruction specifies two things.
DMA controller 90 determines when an instruction is sent to instruction register 88 and
And the controller 90 begins to recognize when it is decoded. (1) The instruction is the instruction that has just been sent in the memory device 42.
It is located in the memory location immediately following the byte memory location and is a 3-byte instruction with two additional bytes. (2) These two bytes contain the graphical information to be displayed and indicate a memory location that is followed in sequence by many other memory locations. Once the instruction is determined to be a 3-byte, memory map mode instruction, display list counter 82 is incremented appropriately;
The two bytes of data following the first instruction are then transferred from memory device 42 to data bus 6.
0 and is continuously transferred to the memory scan counter 84. The two-byte transfer, including the incrementing of the display list counter, is performed under the control and management of signals generated by DMA controller 90, and is preceded by a HALT command. Memory scan counter 84 contains the first address of a sequential list of bytes containing graphics data. DMA controller 90 uses the contents of memory scan counter 84 as an address (sent to memory device 42 via address bus 62) to initiate a memory read operation. The bytes of information so accessed are sent from memory device 42 via data bus 60 to display RAM 114 where
The byte is stored in RAM 114. At the same time, under the control of DMA controller 90, information is sent via multiplexer 120 to playfield graphics shift register 122.
According to the control signal from the DMA control device 90, the register control device 121 controls the shift register 122.
Select one of four clock signals (2CLK, CLK, CLK/2, or CLK/4) to send to the clock. The bytes of graphics information are then transferred to the playfield graphics shift register 12.
clocked out from signal line 1
23a or both signal lines 123a, 123b (1
(depending on whether it is to be shifted one or two bits at a time) to playfield encode logic 124. play field・
In the encode logic circuit 124, one of the four output lines PF0, PF1, PF2 or PF3 is activated according to the state of the bit or byte applied thereto. The operation continues as follows. A series of arranged bytes of graphics information are transferred from memory device 42 to playfield generator 44A. As the playfield generator receives each byte,
It is placed through the display RAM 114 (where each byte is stored) into the shift register 122 where it is converted into video information that appears on one of the output lines PF0-PF3. This video information is sent to priority encoder 144 (Figure 4B) and color-intensity register 176 as described in detail below.
It is used to select one of the following. If the instruction being executed is one that generates only one line of the memory map graphic (for example, instruction No. 2, 3, or 5), the new instruction will generate only one line of the completed horizontal line. instruction register 8 during the horizontal blanking period following
Must be sent to 8. On the other hand, the instruction being executed is 2,
If 4 or 8 lines are required (eg, instructions Nos. 4, 6, or 7-9), the graphics information currently contained in display RAM 114 is used. This procedure is illustrated in FIG. In FIGS. 4A and 9, it is assumed that instruction No. 8 in the table is being executed. Further assume that flag bit D6 of the instruction is set to a logic one. This logic 1
indicates that the instruction is a 3-byte instruction, and the two additional bytes contain the address of the graphics information to be used. Located in section 42' of memory device 42 are a number of contiguous arrays of 1-byte
memory location, this memory location is memory location 35
0a-350e, each memory location containing graphics information. After the instruction is sent to instruction register 88 and the two-byte address is sent to memory scan counter 84, the playfield object generator uses the address signal sent by memory scan counter 84 to Then, continuous access to the memory device 42 is started. The contents of the memory locations in memory section 42' are sequentially sent, one byte at a time, to display RAM 114 and temporarily stored therein. Each byte is a display
Once sent to RAM 114, the byte is immediately read out and passed through multiplexer 120 to shift register 122. Shift register 122 transfers information via signal line 123a to playfield logic circuit 124 as described above, where it uses the code shown in FIG.
1 is selected. Graphic information is displayed on the selected PF0 or PF
It appears on the display device 22 as a color-luminance value specified by one line. Once the first or first horizontal line 354 of the instruction
Once completed, the graphic information used to generate the lines is stored in memory device 42.
Display RAM in the same arrangement as when
114. The next three lines 356, 358, 360 are the display
Generated by successively accessing graphics information from RAM 114. in this way,
During active scanning of lines 356, 358, and 360, display RAM 114 is addressed by RAM access counter 116 in response to appropriate timing and control signals from DMA controller 90. Upon completion of the last horizontal line 360 generated by an instruction, a last line signal is generated by comparator circuit 98 to begin fetching a new instruction. As mentioned above, according to the instruction (instruction No. 8), the shift register 122
Each byte of the graphics is sent one bit at a time from the playfield encoding logic circuit 124 via signal line 123a. Next, the encoding logic circuit 124 connects the signal line
After passing through PF0 or PF1, the graphic is given priority to the encoder 166 and collision detection device 164 (FIG. 4B).
send to The one selected from PF0 or PF1 is
It depends on the binary state of the signal appearing on signal line 123a. Assuming a point in time when there is no graphical information representing a moving object on the four output signal lines 172, the playfield graphical information sent to signal line PF0 or PF1 is used to select one of the color-intensity register selectors 178. to obtain the color and brightness values used. FIG. 10 shows a portion of the circuitry of color-intensity selector 178 with color-intensity registers 176a-176d corresponding to playfield graphics signal lines PR0-PF3. Although FIG. 10 only shows the selection logic used for signal lines PF0-PF3, it is clear that similar logic could be used for the moving object graphics and their corresponding color-intensity registers 176. It is. The selection device 178 in FIG.
AND gate 372a used to select 4 bits of color information included in one of a-176d
- Contains 372d. Similarly, each AND gate 374a-374d has three bits of luminance information sent from each color-luminance register 176a-176d. For simplicity, the AND and OR gates shown in FIG. 10 are represented as individual gates. However, as will be clear to those skilled in the art, said individual gates may also be multiple gates in parallel configuration. For example, although AND gate 372a is depicted as a single 2-input AND gate, AND gate 372a is also a four-parallel 2-input AND gate. This also applies to AND gates 372b-372d.
Similarly, each AND gate 374a-374d has 3
It is a parallel 2-input AND gate. Each OR gate 37
5a-375b are similarly simplified. However, the OR gates 375a and 375b are
AND gates 372a-372d and 374a-3
Information from player missile color-intensity registers 176e-176h (FIG. 14) is received via similar enabling circuitry, such as represented by 74d. Therefore, OR gate 375a is a 4-parallel 8-input OR gate, while OR gate 3
76b is a 3-parallel 8-input OR gate. AND gates 372a-372d OR gate 3
75a and then four signal lines 18
4 is sent to the delay line tap selection circuit 182. Similarly, AND gates 374a-374d
selectively sends the 3-bit contents of registers 176a-176d representing one brightness value to an OR gate 375b and thence to a 3-bit digital-to-analog converter (DAC) 376. DAC37
6 converts the 3-bit information to a voltage level and sends it to video summer 52 via signal line 180. Only one of the priority encoder output lines 1-8 is active at any time. Which of the priority encoder output lines 1-8 is active depends on the information received. For example, playfield
Information on any of the graphic signal lines PF0-PF1 causes one of the priority encoder outputs 1-4 to become active. The active priority encoder outputs are then connected to AND gates 372a-372.
d, which color-brightness register 176a-17
The 4-bit portion (including color information) of 6d is connected to the delay line tap selection circuit 182 on the 4 signal line 184.
Choose whether to be sent to. Similarly, one 3-bit portion of color-luminance register 176 (containing luminance information) is sent to DAC 376 on signal line 1.
80 is converted to a voltage level representative of the brightness provided to 80. The playfield graphic line is
Each corresponds to priority encoder output lines 1-4. In this way, Fig. 4A, Fig. 4B, Fig. 9,
In FIG. 10, when graphics information is sent one bit at a time from graphics shift register 122, one of the playfield graphics lines PF0 or PF1 becomes active. Next (again, assuming no moving graphics information), output lines 1-2 of priority encoder 166, corresponding to signal lines PF0 or PF1, respectively, enable AND gates 372a, 374a or 372b, 374b to register the corresponding registers. Select the contents of 176a or 176b. In this way, the 4 display line part 2 in Figure 9
For 2', if the graphics information is a logic zero, the color and brightness, designated as PF0, is dictated by the contents of the PF0 register 176a. Similarly, logic 1 displays an object as shown in PF1' in Figure 9, and this object is
It has the color-luminance specified by the contents of the PF1 register 176b. Instruction (No. 8) (and instructions No. 2, 5, and 6) sends or maps a section of memory device 42 to display device 22, one bit at a time. Each bit here indicates one of two corresponding registers containing the color and brightness characteristics to be displayed.
However, other instructions in the table (e.g. instruction no. 3, 4, 7, 9)
also generates playfield graphics in this memory map mode. However, as shown in this table, each byte of information is processed two bits at a time by the playfield encoding logic circuit 1.
Sent to 24th. This content is shown in FIG. Three bytes 377a-377c are shown as they are sent sequentially from the memory device (Figure 3) to shift register 122 (Figure 4A). That is, byte 377a is sent first, followed by byte 377b, then byte 3.
77c is sent. If playfield object generator 44A is currently under the control of one of table instructions Nos. 3, 4, 7, or 9, each byte is transferred from graphics shift register 122, two bits at a time, by data 3.
78a-378c as compressed 2x4 blocks to the playfield encoding logic. Depending on the logic state of the individual bits sent, the logic signal appearing on output lines 123a, 123b can be in one of four possible states at any time. As shown in FIG.
0-Used to select one of PF3. Each 2-bit segment of graphics information is then sent to playfield encoding logic 124 (FIG. 4) from there to priority encoder 166 and color-intensity register selector 178 (FIGS. 4B and 10). sent to. In the latter, the information is used to send the contents of one of the color-intensity registers 176 (one of registers 176a-176d) to signal line 184 and DAC 376. Note that in both the examples shown in FIGS. 9 and 11, a logic zero, whether one or two bits, selects the PF0 register 176a. instructions
If no movable or playfield object graphics information is sent to the priority encoder during active scanning of a horizontal line, such as when No. 1 is being executed, the color specified by the contents of register 176a. - Brightness characteristics are displayed. In this embodiment, the number of consecutive elementary beam positions used by display device 22 to construct a particular horizontal line of video is selected to be 160, corresponding to one period of the CLK signal. However, some pixels consist of multiples or submultiples of this number (eg, 320, 80, or 40), and multiple multiple clock speeds can be used for this purpose, as described below. Information is transferred one or two bits at a time from the playfield graphic shift register 122.
bits, at one of four possible rates, according to instructions executed by object generator 44. The available rates are 2CLK, CLK, CLK/2 and CLK/4, of which CLK is generated by timing device 58 and is the timing signal for each beam position designation. In this way, any active horizontal line has color-luminance playfield information of 320, 160, 80 or
Display 40 increments. For example, Instruction No. 2, which specifies data transfer from shift register 122 at a 2 CLK frequency (approximately 7.2 MHz), will result in 320 color-brightness increments during each active horizontal line shown on display device 22. . On the other hand, according to instruction No. 3-6, the shift register 122 is
It transfers data at the CLK (approximately 3.6MHz) frequency and displays up to 160 increments of information.
Instructions No. 7 and No. 8 display (maximum) 80 increments of color-luminance information per horizontal (active) line using a data rate of CLK/2. On the other hand, instruction No. 9 that specifies CLK/4 uses color-luminance information.
Up to 40 increments are sent to the display device 22 and displayed. Another way to consider the interrelationship between the rate at which graphics information is transferred from graphics shift register 122 and the maximum number of color-luminance increments that can be used in a horizontal line is in terms of display resolution. Then, instruction No. 2
specifies a horizontal resolution of 320 increments per scanned line. Instruction No.3
-6 specifies a resolution of 160 increments per line. Instructions No.7 and No.8 are
Specifies a resolution of 80 increments per line. Instruction No. 9 specifies a resolution of 40 increments per line. The number of lines generated for each instruction is
Determined by decoding the code. Therefore, each instruction's operation
The code is provided to ROM 94 and addresses a memory location in the ROM that contains four bits of digital information specifying the number of horizontal display lines for the instruction. The contents of the addressed memory location of ROM 94 is sent to comparator circuit 98 . A line counter 96, updated after each line is generated, counts the number of lines generated and sends the count to the comparison circuit. When a match is obtained, a last line signal is generated by comparator circuit 98, which indicates that execution of the current instruction is complete and that a new instruction is available to continue display operation. indicates that it must be done. The last line signal is via signal line 100.
to DMA controller 90, thereby incrementing the contents of display list counter 82 by one. The DMA controller then manages the transfer of subsequent instructions from memory device 42 to instruction register 88 (FIG. 4A). The instruction is decoded and the timing and control signals are as specified by the instruction.
generated by DMA controller 90 and continues to generate playfield graphics. Memory map mode using one of the instructions No. 2-9 in the table directs the generation of playfield objects that appear on display device 22 by using one or more of the following methods: Can be done. a The graphics are one horizontal line per instruction (instruction No. 2, 3, 5),
2 lines per instruction (No. 4, 6), 4 lines per instruction (instruction No. 7, 8),
Alternatively, eight lines per instruction (instruction No. 9) are mapped from the memory device 42 to the display device 22. In multiple line generation, subsequent lines are copies of the first horizontal line. Graphic information is
It is stored in display RAM 114 during the first line and continues to be output from RAM for subsequent lines. b Graphic information from the memory device 42 is
The video information is converted one bit at a time or two bits at a time. In the former case, it is used to select one of two possible color-luminance characteristics (instruction No. 2, 5, 6, 8) for display. In the latter case, it is used to select one of four possible color-luminance characteristics (instruction No. 3, 4, 7, 9). c The horizontal resolution of each line generated according to the instructions is 320 elements per line (instruction No. 1), 160 elements per line (instruction Nos. 2-6),
per line (instruction No. 7 and 8)
80 elements, or 40 elements per line (instruction No. 9). All playfields are mapped to memory maps.
This can be generated using mode instructions. However, for playfield objects such as alphanumeric graphics, it is preferred to store the graphical information in addressable blocks of memory locations in memory device 42. Here, each block contains graphical information indicating the character to be displayed. This mode is designated as the "Character Name" mode and is described below. (ii) Character Name Mode Playfield graphic information is stored in the playfield object generator 44 in the manner described above regardless of the operation mode.
A is sent to the display device 22. However, in character name mode,
The method of accessing graphics information from memory device 42 is somewhat different from that used in the memory map mode described above. Additionally, each instruction used in character name mode (e.g., one of instructions Nos. 10-15) causes one complete horizontal row of alphanumeric characters to appear on display device 22. Character information can be displayed. Each displayed horizontal row consists of at least eight horizontal scan lines. FIG. 12 is a diagram of the operation of object generator 44 in this mode. For purposes of explanation, character instruction 380 (one of instructions Nos. 10-15) is the memory device 42.
Assume that an active horizontal scan has just been completed on display device 22 at the next instruction in the list of instructions stored in memory location 284 (FIG. 7). The last line signal is generated as described above,
sent to the DMA controller 90 (FIG. 4A).
Under the management and control of DMA controller 90, horizontal line counter 96 is cleared and instruction 380 is fetched, stored in instruction register 88, and decoded into a 3-byte instruction. (eg, flag bit D6 is set to logic 1, see table). A 3-byte instruction is obtained when this instruction is of the first type in the instruction list (e.g., character mode), for the following reason. Addressing memory device 42 under the control of DMA controller 90 and using the contents of display list counter 82, immediately following the instruction byte 380a,
380b is a 16-bit memory scan counter 8
Sent to 4. Two bites 380a and 380b
contains the address of the block at memory location 292 (FIG. 7). Block 292, for example CN
-The memory location shown as A contains a data word called a character name, which data word is used to fetch a contiguously arranged block of bytes 382 from memory device 42. Used by field object generator 44A. Part-time job 38
2 contains graphic information sent to display device 22. When the active scan for the next horizontal line begins, using the contents of memory scan counter 84 to address memory block 292, byte CN-A of memory is stored under the control of DMA controller 90. Display RAM11
4 and is sent to character name register 110. Before starting this instruction,
MPU 40 sends information to character base register 112. Now, using the combined contents of line counter 96, character name register 110, and character base register 112, first byte 382a is stored in memory device 4.
2 to a graphics shift register 122 and thence to playfield encode logic 124 on signal line 123a. Character base register 112 contains a base address, which is:
A section of memory device 42 containing approximately 128 (3 8-byte blocks) of graphics information.
82) is used to locate sections containing 8-, 10-, or 16-byte blocks 290 (FIG. 7). Typically in ASCII format, character name register 110 contains the address of one of 128 blocks 290 representing a particular character. Finally, line counter 96 completes the address of the designated block and also completes the address of block 38, for example.
Used to specify one of the eight bytes of each block, such as bytes 382a-382h of 2. During active scanning of the first horizontal line of instructions, the memory scan counter 84 is continuously incremented and the character name is transferred from the memory device 42 to the display for storage.
RAM 114, character name register 110, and registers 110, 11.
One byte of graphics information at the memory location specified by 2 and the contents of line counter 96 is sent to graphics register 122. Upon completion of the first scan line, line counter 96 is incremented. The character name used to generate the remaining display lines required by the instruction is DisplayRAM.
114 are now stored continuously. During the rest of the horizontal line scan (in the instruction), like this:
Character graphics information is obtained simply by accessing the contents of display RAM 114 and character name register 110.
Update. Graphic information is transferred in the same manner as the first line. At the end of each horizontal line,
Line counter 96 is incremented. Assuming that instruction No. 10 of the above table is executed, a horizontal column 386 of 20 characters, consisting of eight consecutive horizontal display lines, will be displayed on display device 22. Upon completion of this instruction, the next following instruction 381 is sent to the instruction register, which may be one of the instructions in the table, such as another character mode instruction. No.10 is also fine. If the instruction's flag bit is set to logic zero (indicating a 1-byte instruction), the list of character names 292 will contain the final instruction 38.
Continue from the point where there are no 0s. On the other hand, if instruction 381 indicates an ordered list of character names stored elsewhere in memory device 42, flag bit D6 of the instruction is set to a logic one.
This immediately follows instruction 381,
Indicates the presence of two bytes sent to memory scan counter 84. Note another feature of the invention. In other words, the same address and graphic information
A point that can be operated by more than one instruction, in which case the same graphical information is displayed, but the display device 22
The dimensions on the top are different. For example, if horizontal swath 386 of characters is generated by execution of instruction no. It is expressed as Each byte of graphical information is displayed only once. This is simply done by simply incrementing line counter 96 every other horizontal line. Object Graphics Generator 4
4 (FIG. 3) continuously accesses from memory device 42 a list of display instructions stored in the memory location indicated by the address signal output from display list counter 82 (FIG. 4A). do. When the end of the object graphic's display field typically reaches or near the bottom horizontal line scan, the display list counter 82 registers the object graphic's next display field.
To start generating fields, select the first one in the list.
Must return to display instructions. Therefore, for this purpose, Jump Instructions (Instruction No.
16) is used. The list of display instructions for direct operation of object graphics generator 44 all have a 3-byte jump instruction as their last instruction. The last two bytes contain the address of the first display instruction in this list. During the execution of the jump instruction, the 2-byte address is
from memory device 42 to a buffer register (not shown) of display list counter 82. The contents of the buffer register are then passed to display list counter 82 and become address signals output by address counter 82 to address memory locations in memory device 42. The memory device 42 contains the first display instructions of the list used to generate and display the object graphics display field on the display device 22. If, in some cases, the display field of the object graphics ends early, ie some horizontal lines end early, jump instruction No. 16) with flag bit D6 set to logic 1 is used. In this case, the jump is performed as described above.
However, further operation of the object graphics generator is halted until the end of the vertical retrace interval of display device 22. When the end of the vertical blanking period is detected by the monitor by the DMA control device 90,
The DMA controller 90 begins outputting timing and control signals, continuously sends and executes the display instruction list, and again starts displaying the object graphics.
field is generated. b. Movable Object Generation Graphics information is sent from either MPU 40 or memory device 42 to graphics register 152 of movable object generator 44B (Figure 4B). In the latter case, the playfield object generator 44A
(Figure 4A) manages and controls the transfer.
4A, 4B, and 14, the movable object DMA counter 86 (shown in more detail in FIG. 13) consists of three sections, the contents of which include the player and missile graphics. Memory device 42 for information
Constructs a 16-bit address used to address the As shown in FIG. 13, counter 86 has a 6-bit latch 86a, a modulus 5
It consists of a counter 86b and a 7-bit counter 86c. The contents of 6-bit data latch 86a constitute the most significant bits of a 16-bit address, while the contents of modulo-5 counter 86b and 7-
The contents of bit counter 86c constitute each remaining address. The counter operates by receiving clock pulses from signal line 87a that increments modulo 5 counter 86b through the five possible logic states, 000, 001, 010, 011, and 100.
When counter 86b reaches its maximum (100) and is incremented to the next (initial) state (000), an increment occurs on signal line 87b, incrementing the contents of the 7-bit counter. Graphic information for the player and missile objects is located in memory section 288 of memory device 42 and is arranged in five consecutively arranged 256-byte blocks 288a-288e.
include. The bytes of each block 288a-288e are arranged sequentially to correspond to a horizontal line scan of display device 22. The configuration of movable object counter 86 described above functions as follows. The contents of 6-bit data latch 86a address a particular section 288 (FIG. 7) of a memory location in memory device 42 that contains moveable object graphics. Module 5 counter 86b sequentially selects one of the five 256-byte blocks 288a-288e of memory section 288 while
A 7-bit counter 86c sequentially selects one of the 256 bytes available from a particular addressed block. Each byte of each block 288a-288e corresponds to a horizontal line scan of display device 22. Each byte of the 256-byte block contains 2-bits of missile graphics information M1-M4. 256-Bite Block 288b-288
Each of e is a player object 420-4
Contains graphic information for 26. For example, all blocks 288b are sent to display device 22'. Each byte of block 288b is displayed in ordered order forming a vertical swath 430. Graphic information representing player object 420 is displayed on display device 22' as object 420' and is stored in a 256-byte block 288.
has a vertical position on the display corresponding to that position of b. player object 422,
The same goes for swaths 424 and 426, which are displayed in vertical swaths 432, 434, and 436, respectively. As mentioned above, each missile object is
Only 2 bits are required per horizontal display line. In this way, memory block 288
Each 1-byte memory location consisting of a contains 2 bits of graphics information for missile objects M1-M4. In a manner similar to the display of player objects, the 256 2-bit portions representing missile graphics M1-M4 are displayed as vertical swaths. In FIG. 13, player object 44
2' and 426' (on display device 22') are assumed to have launched their corresponding missiles M2' and M4'. Therefore, missile M2'
The graphical information contained in the memory locations of block 288a for M4' and M4' are displayed as vertical swaths 438 and 440, respectively. 4A, 4B, and 13, during the vertical blanking period, movable object DMA counter 86 is supplied with an initial address by MPU 40 via data bus 60. Referring to FIGS. Besides, MPU4
0 transfers one byte of data to each of the eight horizontal position registers 140. Register 140-4
one corresponds to one of the player objects,
The remaining four registers 140 correspond to each missile object. register 1
40 contains information indicating the horizontal position of the player or missile object on display device 22'. During the horizontal blanking period preceding the first horizontal active line scan (and all horizontal blanking periods that follow), the playfield object generator 44A controls the movable object generator 44A.
Using the contents of DMA counter 86 as an address, reading of memory device 42 is initiated. Each read is performed during a scheduled time of the horizontal blanking interval and is preceded by a HALT command generated by DMA controller 90. Movable object generator 44B
The DMA register selection logic circuit 202 selects the sink/
With the decoded output from the H-counter provided by generator device 146,
Upon receiving the HALT command, one of the five signal lines
A select signal is sequentially generated in the graphics register 152 via the OR gate 204. The select signal is applied to one of the four 8-bit (player) graphics registers 152 (i.e., register 152b shown in FIG. 13).
152c) to receive graphics information from memory device 42 via data bus 60. Graphics information for missile objects is transferred one byte at a time. Simultaneously, four 2-bit missile graphic registers 152 (register 152 shown in FIG.
a) is loaded once every horizontal blanking period. At the end of each read operation (for player missile graphics), the movable object DMA counter 86 (i.e., modulo 5 counter 86a) is activated via signal line 87a.
It is incremented by an increment signal sent from the DMA control device 90. The contents of movable object DMA counter 86 are 1 from each block 288a-288e during each horizontal blanking period.
Addresses two memory locations. The contents of each addressed memory location are transferred via data bus 60 to the selected graphics register 152 (13th
The four 2-bit registers combined in the figure 1
52a or player graphics register 1
52b-152e). During active scanning of each horizontal line, the contents of each horizontal position register are sent to a corresponding one of comparators 142 and compared with the horizontal count issued by sync generator device 146 via signal line 148. When the contents of the horizontal position register match the horizontal count issued by the sink generator device 146, the corresponding comparator 142
initiates a shift command and sends it to graphics register controller 156. Register controller 156 then controls the corresponding graphic
Signal line 154a (player video graphics) or 154b (missile video graphics) to register 152 (i.e., one of four missile registers 152a or one of player registers 152b-e shown in FIG. 13).
The collision detection device 164 is commanded to continuously send its contents via one of the following. This video
The graphics are also sent to priority encoder 166 via OR gate 170. The function of the priority encoder 166 is to determine which of the graphical information of two or more objects to display when they overlap at the same time. That is, decisions are made as to which objects overlap which other objects. for example,
As specifically explained in FIG. 10, from playfield generator 44A to signal line PF0-
The graphic information sent to the priority encoder 166 via PF3 is sent to each encoder output line 1.
-Activate 4. Next, encoder 16
The active output of 6 is the color-intensity register 17.
Select one content from 6a-176d. Colors for moving object graphics
Brightness selection is done in a similar manner. As shown in FIG. 14, encoder output lines 5-8 are
color-intensity register selector 178;
Select the contents of one of the color-intensity registers 176e-176h that corresponds to the two player-missile combinations. Each missile object has the color and brightness characteristics of its corresponding player object. Figure 3, Figure 4A, Figure 4B, Figure 7, Figure 14
In the figure, during the vertical blanking period, the MPU 40:
Send horizontal position information to horizontal position register 140.
Furthermore, the movable object DMA counter 86 is
It has an address indicating the first byte of memory section 288. The first byte is 256-
It is also the first byte of byte block 288a. During each horizontal blanking interval immediately preceding each active horizontal line scan, five bytes of graphics information are fetched from memory device 42 using the address output by movable object DMA counter 86. Each of the five bytes is selected from a different one of the five blocks 288a-288e. During continuous active scanning of horizontal lines, windows are created and graphical information is sent to selection device 178. In this selection device, this information is converted to color-intensity information and then sent to display device 22. Each block 288a-28 of the aforementioned memory locations
This method of transferring the graphical information contained within 8e effectively maps each block onto display device 22'. Horizontal movement of objects displayed in this manner is accomplished simply by changing the contents of the corresponding horizontal position register 140. This not only moves the object graphics, but also moves all vertical columns associated with the object. For example, considering swath 430 corresponding to memory location block 288b, in response to operation of player input control 18 (FIG. 3),
MPU 40 calculates a new relative horizontal position for player object 420 on display device 22'. During the next vertical blanking period,
The MPU 40 transfers the new horizontal position information to the horizontal position register 140 corresponding to the object 420'.
Write in one of the. During each display field, the blocks of graphical information 288b are sequentially sent to the movable object generator 44b, which then finalizes the display device 288b.
2' where it is displayed again as swath 430, but shifted to the right or left. Vertical movement of a movable object graphic is accomplished by removing the object graphic from a location in its block and writing it back to a new location in the same block. For example, during a vertical blanking interval, object graphics information 420 (FIG. 13) contained in memory location block 288b is read and sent to a new location in the block designated as object graphics 421.
Object graphics 420 is then erased. New object graphics 4 during the next active display field
21 appears on the display device 22 as an object 421'. c Collision Detection Graphic information for each moving object is
Collisions are determined by comparisons between each other and with playfield objects for temporal consistency. Collision detection device 164 (FIG. 4B) includes a number of
includes an AND gate (not shown), which is
Used to determine time alignment between moveable and playfield objects. Such a determination is made using 16 4-bit collision detection registers 16
sent to one or more of 5. With reference to FIGS. 4B and 15, collision detection for a particular movable object (here player 2) will be described, but the description is equally applicable to the remaining players and missile objects. As shown, the graphics information from player 2 graphics register 152c is input to four ANDs included in collision detection device 164.
are sent to gates 164a-164d. The second input to each of AND gates 164a-164d is
Graphic signal lines PF0-PF3 for playfield objects. When a graphics information signal from graphics register 152c coincides in time with a graphics information signal appearing on one of the playfield graphics signal lines PF0-PF3, the signal indicating such a match or collision is a 4-bit signal. • Sent to data register 162' where the signal is temporarily stored. The time coincidence information now stored in data register 162' is transferred to MPU 40 (the (Fig. 3). The address of data register 162' is sent to register selector 200 (FIG. 4B), which decodes the address and selects register 162'.
2', the contents of the register are output to the data bus 60, and the contents of the register are output to the MPU 4.
Sent to 0. Normally, the MPU 40 performs the following during each vertical blanking period:
All 16 collision detection registers 165 are read out in a similar manner. After the information contained in the 16 collision detection registers 165 is sent to the MPU 40, a write command is started. The address placed on address bus 62 is decoded by register selector 200 to generate a clear (CLR) signal, which is sent to collision detection registers 165 to simultaneously clear their contents. Collision information obtained from collision detection register 165 by MPU 40 is used for various purposes depending on the mode of system operation. For example, information regarding a collision between a movable "target" object (eg, a ball) and a playfield "boundary" object causes MPU 40 to change the direction of movement of the target object. Information indicating the collision between the player object and the missile object is sent to the MPU 40,
The graphical information indicating the player is changed to display it as if it were an explosion. The collision information allows the MPU 40 to create an appropriate score table. C. Operating System 10 has two basic modes of operation, which are selected by providing system 10 with the appropriate operating program. When operating in the first mode, system 10 functions as a programmable general-purpose computer. The second mode of operation is
System 10 is made to function as a video game device. There are several ways to provide an operating program to system 10. The operation mode is thereby selected. ROM cartridge 33 containing operating program
is inserted into cartridge container 32 (FIG. 2). The operating system program is also stored in a peripheral device such as a disk drive 15 or a cassette (tape) drive 16, for example. The desired operating program thus stored is read from the selected peripheral device into the RAM section of memory device 42. However, regardless of the mode of operation in which system 10 functions, the operation of the internal circuitry of FIG. 3 remains essentially unchanged. For example, system 1
0 functions as a general-purpose computer information manager, such as listing the names of relatives, friends, and other suitable data, the operating program may display portions of that information on the display device 22. Can be done. In this way, object generator 4
4 from the memory device 42 to the display device 22
You will be asked to send graphic information to The operating program
A predetermined list of instructions is stored in RAM section 284 of memory device 42.
(FIG. 7), the MPU 40 is instructed to send the display instructions so that the MPU 40 can use them. In this way, information is shown to the user via the display device 22;
The MPU 40 can modify portions of the display instructions, primarily the 2-byte addresses of 3-byte instructions, thereby modifying the graphical information to be displayed (e.g. alphanumeric characters). Object generator 44 is directed to those sections of memory device 42 containing lines, heading marks, etc.). Conversely, an operating program may require information to be displayed in a graph-like format. Therefore, in the form of a Cartesian coordinate system, the playfield display is connected to the display device 2.
2 to the user. Additionally, the operating system may require the display of a movable cursor.
In such a case, the operating system includes a block of graphical information containing image data for the vertical columns that movable object generator 44B configures on display device 22. The image data also includes data for cursor objects. The MPU 40 then registers the movable object DMA counter 86 (FIG. 4A) with
Writes the address of the location in memory device 42 of the block of graphical information containing the cursor image data. MPU 40 also writes data words to DMA control register 10. The contents of the DMA control registers are sent to the DMA controller 90 for displaying movable object graphics. Therefore, the DMA controller 90 controls the movable object.
A signal is provided to a DMA counter 86 which causes the DMA counter 86 to identify a memory location in the memory device 42 containing graphics information for the cursor.
Address sequentially. The DMA controller controls the movable object generator 44B (Figure 4B).
Sent to DMA register selection logic circuit 202
Generates a HALT command. Immediately following the HALT command, the DMA controller 90 uses the address signal provided by the movable object DMA counter 86 to indicate the memory location to the memory device 4.
Start accessing 2. At the same time, using the H-counter decode generated by the sink generator 146, the DMA register selection logic circuit 2
02 generates a SELECT signal on one of the five lines, which is sent to the corresponding graphics register 152. The select signal is used to select the graphics card to receive and store information present on the data bus 60.
Select one of the registers 152. As previously mentioned, the selection of a particular one of the graphics registers 156 is determined by the particular time interval within the horizontal blanking period during which memory accesses are made for moving object graphics. Each movable object is given a scheduled interval during each horizontal blank time for receiving graphical information. Therefore, the DMA controller 80 initiates memory reads during these scheduled time intervals;
And, the DMA register selection logic circuit 202
In response to receiving the HALT command and the appropriate H-counter decode, a select signal is generated for the signal line corresponding to the scheduled time interval. The OR gate 204 shown in FIG. 4B is shown as five OR gates, each corresponding to one of the five graphics registers 152 (the four 2-bit missile graphics registers are loaded simultaneously). is treated as a single 1-byte register for transferring information thereto). Additionally, each OR gate, shown as OR gate 204, receives a select signal from DMA register selection logic 202 and a register selection (REG.
SELECT) signal. This latter signal is
It is used when graphics information is written to one or more of graphics registers 152 by MPU 40. Relative horizontal and vertical movement of a cursor object displayed on display device 22 is effected by MPU 40 in the manner described above. New horizontal position information is written to the movable object position register 140 during the vertical retrace interval. Rewriting of the image data for the cursor object to a new location within the block of graphics information is performed by the MPU 40 during the vertical retrace interval. The data used by MPU 40 is provided by actuation of control stick 18 or keys 24 by the user. Typically, control stick 18 provides user-generated position information, which is sent to MPU 40 via peripheral interface device 50 .
Control stick 18 may be constructed in a manner such as that shown in U.S. Pat. No. 4,091,234. The present invention provides a data processing system having a programmable object graphics generator that allows the transfer of graphics information from a memory device to a display device with little assistance from the system's processor unit. Therefore, the generated movable object is
Only positioning circuitry for horizontal movement is required, thereby eliminating the need for additional circuitry for vertical positioning. Although the best mode for carrying out the present invention has been described above, improvements and changes based on the present invention are possible.

[Brief explanation of drawings]

Fig. 1 is a schematic diagram showing the component parts of the present invention, and Fig. 2 is a schematic diagram showing the component parts of the present invention.
FIG. 3 is a general block diagram of the circuit of the present invention; FIG. 4A and FIG. 4B is a block diagram of the object graphics generator shown in FIG. 3, FIG. 5 is a block diagram of the audio signal generator control device shown in FIG. 3, and FIG. 6 is a block diagram of one of the audio control devices shown in FIG. Outline diagram, No. 7
The figure is a block diagram of the memory device shown in FIG. 3, FIG. 8 is a diagram showing signals transferred to the serial (I/O) bus shown in FIG. 3, and FIG. 9 is a diagram showing the signals transferred to the serial (I/O) bus shown in FIG. Example 1 of how playfield object graphics are generated by the illustrated object graphics generator.
Figure 0 is a schematic diagram of the color-brightness selection device of the object graphic generator shown in Figures 3 and 4, Figure 11 is a diagram showing backing of graphic information, and Figure 12 is a diagram showing playfield character generation. Figure 13 is a diagram showing the indirect addressing technique used in connection with
Figure 14 illustrates a method and apparatus used to store, transfer and communicate information stored and transferred in the illustrated display device; Figure 14 illustrates color-intensity storage registers for movable objects; , FIG. 15 is a diagram showing a portion of the collision detection logic circuit shown in FIG. 4A. 10... System, 12... Console, 14... Printer, 15... Floppy disk, 16... Cassette, 18... Control stick, 22... Display device,
33...ROM cartridge, 36...additional memory/
Package cage, 24...Keyboard, 40...MPU,
42...Memory device, 44...Object graphics generator, 46...Audio generator, 50...Peripheral interface device, 5
2...Video totalizer, 54...RF modulator, 5
8... Timing device, 82... Display list counter, 84... Memory scan counter, 86
...Movable object DMA counter, 88...Instruction register, 90...DMA controller, 94...ROM, 95, 108...MPX, 96
...Line counter, 98...Comparison circuit, 101...
DMA control register, 110...Character name register, 112...Character base register, 114...Display RAM, 116...
RAM address counter, 121...Register controller, 122...Playfield graphics shift register, 124...Playfield encode logic circuit, 140...Moveable object horizontal position register, 150...Sink generator, 156...Graphics register control device, 164...collision detection device, 166...priority encoder, 178...color-luminance register selection device, 18
2... Delay line tap selection device, 200... Register selection device, 216, 230, 240... 8-bit data register, 228... N division counter, 214... Audio control device, 250, 25
6,260...flipflop.

Claims (1)

[Scope of Claims] 1. A multicolor raster graphics device connected to a data bus 60 from which data for one of a plurality of different colors is transmitted.
a plurality of color registers 176 for respectively receiving and storing; timing means 58 for generating a periodic clock signal; and memory means 1 for storing graphics data.
14; and a graphics shift register 122 connected to the memory means to receive the graphics data and shift out the graphics data in parallel bits in response to the clock signal.
and; playfield encoding logic 124 connected to the graphics shift register 122 for selecting one of the color registers in response to the shifted out bits of graphics data it receives; video signal generating means 52, 54 for connecting the selected color register to the raster display device 22 for displaying a color according to the data stored in the selected color register; mode selection means 90 for controlling the number of bits shifted out by the graphic shift register 122 and the number of color registers selectable by the playfield encoding logic 124 for each cycle of the clock signal; Multicolor raster graphics device with 121. 2. In the device according to claim 1,
The clock signal has a constant rate relative to the scan rate of the raster display, and means includes means for dividing the constant rate by two to allow selection of the horizontal resolution of the raster display.