JPH0143465B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention has a semiconductor separation layer provided so as to surround a required portion of an epitaxially grown semiconductor layer (hereinafter referred to as "epitaxial layer") formed on the main surface of a semiconductor substrate. It relates to semiconductor integrated circuit devices (ICs).

Below, vertical PNP transistors are used as constituent elements.
This will be explained using an IC as an example.

FIGS. 1A and 1B are a sectional view showing a main part of an example of a conventional IC and an equivalent circuit diagram for explaining its operation, respectively.

In FIG. 1A, 1 is a p-type semiconductor substrate, 2 is an n ^- type epitaxial layer formed on the main surface of the p-type semiconductor substrate 1, and 3a is a vertical pnp transistor of the n ^- type epitaxial layer 2. Similar to the p-type isolation layer 3a, the p-type isolation layer 3b is formed by introducing p-type impurities so as to surround the required portion 2a and reach the p-type semiconductor substrate 1 from its surface ^. A p-type isolation layer 4 is formed surrounding a required portion 2b of the epitaxial layer 2 for forming another vertical pnp transistor, and 4 is a p-type impurity introduced into a part of the surface of the n ^- type epitaxial layer 2a. 5 is a diffusion region for bonding an n ^- type base electrode, which is formed by diffusing n-type impurities into a portion of the n - type epitaxial layer 2a other than the portion where the p-type emitter region 4 is formed. , 6 is a vertical pnp transistor having the p-type emitter region 4 as the emitter, the n ^- type epitaxial layer 2a as the base, and the p-type semiconductor substrate 1 as the collector. 7 is silicon oxide formed over each surface of the p-type separation layers 3a, 3b, the p-type emitter region 4, the n-type base electrode bonding diffusion region 5, and the n ^- type epitaxial layers 2, 2a, 2b. Insulating films such as SiO ₂ ), 8,
Reference numerals 9 and 10 denote an emitter electrode, a base electrode, and a collector electrode, which penetrate through the insulating film 7 and are connected to the p-type emitter region 4, the n-type base electrode adhesion diffusion region 5, and the p-type isolation layer 3a, respectively. 11
is connected to the p-type isolation layer 3b through the insulating film 7, and uses as an emitter a p ^- type emitter region (not shown) formed on the surface of the n ^- type epitaxial layer 2b. Based on p
This is the collector electrode of another vertical PNP transistor whose collector is the shaped semiconductor substrate 1. Although not shown, the collector electrodes 10 and 11 are each connected to a ground terminal via a ground wiring layer formed on the surface of the insulating film 7. R _1a is the portion corresponding to the p-type emitter region 4 of the p-type semiconductor substrate 1 and the p-type
substrate resistance between the part in contact with the shape separation layer 3a,
R _1b is both p-type isolation layers 3a, 3 of p-type semiconductor substrate 1
The substrate resistance between the parts in contact with b, R _3a is p
The separation layer resistance R _3b between the collector electrode 10 of the type separation layer 3a and the p-type semiconductor substrate 1 is the p-type separation layer 3b.
is the separation layer resistance between the collector electrode 11 and the p-type semiconductor substrate 1. In FIG. 1B, 12 is a power supply terminal connected to the power supply, 13 is a ground terminal that is grounded, 14 is an output terminal connected to the emitter electrode 8, and R _E is between the emitter electrode 8 and the power supply terminal 12. The connected emitter resistance, R ₁₀ is the grounding wiring resistance of the grounding wiring layer that connects the collector electrode 10 and the ground terminal 13 , and R ₁₁ is the grounding wiring of the grounding wiring layer that connects the collector electrode 11 and the grounding terminal 13 It is resistance.

Next, the operation of this conventional example will be explained with reference to FIG. 1B.

When a voltage is applied between the power supply terminal 12 and the ground terminal 13 and a signal current is input to the base electrode 9, this signal current is amplified by the vertical PNP transistor 6. This amplified current flows from the power supply terminal 12 to the load resistance R _L , the vertical PNP transistor 6, the substrate resistance R _1a , the separation layer resistance 3a and the ground wiring resistance R ₁₀
It flows through to the ground terminal 13, and an output is obtained from the output terminal 14.

By the way, in this conventional example, since the amplified current flowing into the collector of the vertical pnp transistor 6, that is, the p-type semiconductor substrate 1, flows to the ground terminal 13 through the substrate resistance R _1a , the separation resistance R _3a , and the ground wiring resistance R ₁₀ , the substrate Resistance R _1a , R _1b and separation layer resistance
Connection point where R _3a meets at one point [Illustrated in Figure 1B]
A voltage V ₁ is generated at . Due to this voltage V ₁ , a current flows from the connection point A to the ground terminal 13 through the substrate resistance R _1b , the separation layer resistance R _3b and the ground wiring resistance R ₁₁ , and the voltage V ₂ [V ₂ = V ₁ × R ₁₁ /
(R _1b + R _3b + R ₁₁ )] is generated. Here, R _1b = R _3b
= R ₁₁ , the voltage V ₂ will be 1/3 of the voltage V ₁ . When such a voltage V ₂ is generated at the collector electrode 11, a high gain amplifier circuit is constructed using another vertical pnp transistor formed in the n ^- type epitaxial layer 2b shown in FIG. 1A. In this case, the disadvantage was that the output of this amplifier circuit was influenced by the voltage _V2 .

The present invention was made in view of the above-mentioned drawbacks, and includes a semiconductor separation layer that surrounds and separates a required portion of an epitaxial layer formed on a main surface of a semiconductor substrate, and a semiconductor separation layer that surrounds and separates a required portion of an epitaxial layer formed on a main surface of a semiconductor substrate. forming a semiconductor separation layer separate from the semiconductor separation layer, and forming a semiconductor separation layer between the parts of the epitaxial layer separated by the semiconductor separation layer and this part by the substrate resistance between the parts of the semiconductor substrate that are in contact with both the semiconductor separation layers, respectively; and a portion of the semiconductor substrate corresponding to the required portion of the epitaxial layer outside the another semiconductor isolation layer, and a portion of the semiconductor substrate corresponding to this portion. The purpose of the present invention is to provide an IC that reduces the influence of

FIGS. 2A and 2B are a sectional view showing a main part of an IC according to an embodiment of the present invention and an equivalent circuit diagram for explaining its operation, respectively.

In the figure, the same reference numerals as those in the conventional example shown in FIG. 1 indicate equivalent parts. 3a1 surrounds a required portion 2a of the n ^- type epitaxial layer 2 for forming a vertical pnp transistor and extends p from its surface.
The first p-type isolation layer 3a2 is formed to reach the p-type semiconductor substrate 1, and surrounds the first p-type isolation layer 3a1 with a space therebetween, and extends the p-type from the surface of the n ^- type epitaxial layer 2. A second p-type isolation layer 10a formed to reach the semiconductor substrate 1 is a first
p-type separation layer 3a1 and second p-type separation layer 3a
2 and commonly connected vertically through the insulating film 7.
This is the collector electrode of the pnp transistor 6. Although not shown in FIG. 2A, the collector electrode 10a is connected to a ground terminal via a ground wiring layer formed on the surface of the insulating film 7. R _1a1 is the substrate resistance between the part of the p-type semiconductor substrate 1 corresponding to the p-type emitter region 4 and the part in contact with the first p-type separation layer 3a1, and R _1a2 is the resistance of both p-type semiconductor substrate 1
The substrate resistances R _{3a1 and R 3a2 between the portions in contact with the type separation layers 3a1} and _3a2 are respectively the first p
The separation layer resistance R10a between the collector electrode 10a of the type separation layer 3a1 and the second p-type separation layer 3a2 and the p-type semiconductor substrate 1 is the resistance of the ground wiring layer connecting the collector electrode _10a and the ground terminal 13. This is the ground wiring resistance. Note that R _1b in this embodiment is the substrate resistance between the portions of the p-type semiconductor substrate 1 that are in contact with both the p-type separation layers 3a2 and 3b, respectively.

In the configuration of this embodiment, as shown in FIG. 2B, when a voltage is applied between the power supply terminal 12 and the ground terminal 13 and a signal current is input to the base electrode 9,
This signal current is amplified by the vertical pnp transistor 6. This amplified current is transmitted to the power supply terminal 12.
from emitter resistance R _E , vertical pnp transistor 6,
The flow passes through the substrate resistance R _1a1 , the separation layer resistance R _3a1 and the ground wiring resistance R _10a to the ground terminal 13, and the output terminal 1
Output is obtained from 4. When this amplified current flows, the substrate resistances R _1a1 and R _1a2 and the separation layer resistance
Connection point where R _3a1 meets at one point [Illustrated in Figure 2 B]
At this time, a voltage V ₃ approximately equal to the voltage V ₁ at the node A shown in FIG. 1B is generated. With this voltage V ₃ ,
From connection point RO to substrate resistance R _1a2 , R _1b , separation layer resistance R _3b
A current flows to the ground terminal 13 through the ground wiring resistor R ₁₁ and a voltage V ₄ is generated at the collector terminal 11. Since the separation layer resistance R 3a2 is connected between the connection point of the substrate resistances R _1a2 and R _1b and the collector electrode 10a, this voltage V ₄ is caused by the separation layer resistance R _3a2 being the substrate resistance _.
If it is extremely large compared to R _1a2 , V ₃ × R ₁₁ /
(R _1a2 + R _1b + R _3b + R ₁₁ ) However, since the separation layer resistance R _3a2 is usually smaller than the substrate resistance R _1a2 , V ₃ ×
R ₁₁ /(R _1a2 + R _1b + R _3b + R ₁₁ ) or less. Here, if R _1a2 = R _1b = R _3b = R ₁₁ , then the voltage
V ₄ is less than 1/4 of the voltage V ₃ . Therefore, in this embodiment, the effect on another vertical pnp transistor formed in the n ^- type epitaxial layer 2b shown in FIG. 2A of the vertical pnp transistor 6 is compared with the conventional example shown in FIG. can be reduced from that in the case of

In addition, in this embodiment, the p-type separation layers 3a1, 3
Although the double separation layer a2 is used, it is not necessarily limited to two layers and may be two or more layers. Furthermore, although this embodiment has been described with reference to the case where the vertical pnp transistor 6 is used as a component, it is not necessarily limited to the vertical pnp transistor, and the n ^- The same effects as in this embodiment can be obtained even when other semiconductor elements such as a semiconductor capacitive element constituted by a p-type epitaxial layer 2a and a p-type semiconductor substrate 1 are used as constituent elements. Further, in this embodiment, the case where a p-type semiconductor substrate 1 is used has been described, but the present invention can also be applied to a case where an n-type semiconductor substrate is used.

As explained above, in the IC of this invention,
Since the second semiconductor isolation layer was formed to surround and separate a required portion of the epitaxial layer formed on the main surface of the semiconductor substrate at a distance from the first semiconductor isolation layer, the semiconductor substrate The portion of the epitaxial layer separated by the first semiconductor separation layer and the portion of the semiconductor substrate corresponding to this portion are separated by the substrate resistance between the portions in contact with the first and second semiconductor separation layers, respectively. an influence on another semiconductor element, which is made up of a required part of the epitaxial layer outside the second semiconductor isolation layer and a part of the semiconductor substrate corresponding to this part; can be reduced.

[Brief explanation of drawings]

1A and 1B are a cross-sectional view showing the main parts of an example of a conventional IC and an equivalent circuit diagram for explaining its operation, and FIGS. 2A and 2B are main parts of an IC according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing a portion and an equivalent circuit diagram for explaining its operation. In the figure, 1 is a p-type semiconductor substrate (semiconductor substrate of first conductivity type), 2 is an n ^- type epitaxial layer (epitaxially grown semiconductor layer of second conductivity type), and 3a
1 is the first p-type separation layer (the first semiconductor separation layer of the first conductivity type), 3a2 is the second p-type separation layer (the second semiconductor separation layer of the first conduction type), and 6 is the vertical pnp. In the transistor (semiconductor element), 10a is a collector electrode (electrode of the semiconductor element), and _R1a2 is a substrate resistance. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1 A semiconductor substrate of a first conductivity type, an epitaxially grown semiconductor layer of a second conductivity type formed on the main surface of this semiconductor substrate, and a semiconductor substrate that surrounds a required portion of this epitaxially grown semiconductor layer from its surface. a first semiconductor separation layer of a first conductivity type formed to reach the surface thereof and having an electrode bonded to its surface; a portion of the epitaxially grown semiconductor layer surrounded by the first semiconductor separation layer; and a portion of the epitaxially grown semiconductor layer that is surrounded by the first semiconductor separation layer; and a portion of the semiconductor substrate corresponding to the portion of the layer, the first semiconductor isolation layer and a portion surrounding the first semiconductor isolation layer at a distance from the surface of the epitaxially grown semiconductor layer. A second semiconductor isolation layer of a first conductivity type is formed to reach the semiconductor substrate, and an electrode connected to the electrode of the first semiconductor isolation layer is provided on the surface of the second semiconductor isolation layer. A semiconductor integrated circuit device comprising one of the electrode lead-out regions of the semiconductor element.