[go: up one dir, main page]

JPH0142186B2 - - Google Patents

Info

Publication number
JPH0142186B2
JPH0142186B2 JP58104134A JP10413483A JPH0142186B2 JP H0142186 B2 JPH0142186 B2 JP H0142186B2 JP 58104134 A JP58104134 A JP 58104134A JP 10413483 A JP10413483 A JP 10413483A JP H0142186 B2 JPH0142186 B2 JP H0142186B2
Authority
JP
Japan
Prior art keywords
circuit
light
signal
switch
charge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58104134A
Other languages
Japanese (ja)
Other versions
JPS59229966A (en
Inventor
Tooru Umaji
Juji Izawa
Eizo Ebii
Hideaki Yamamoto
Toshihisa Tsukada
Hisao Oota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Nippon Telegraph and Telephone Corp filed Critical Hitachi Ltd
Priority to JP58104134A priority Critical patent/JPS59229966A/en
Publication of JPS59229966A publication Critical patent/JPS59229966A/en
Publication of JPH0142186B2 publication Critical patent/JPH0142186B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/40Picture signal circuits
    • H04N1/40056Circuits for driving or energising particular reading heads or original illumination means

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Image Input (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Facsimile Heads (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Character Input (AREA)

Description

【発明の詳細な説明】 本発明は光学読取装置、更に詳し言えば、フア
クシミリや、文字読取装置において、書画等の原
稿を走査された電気信号に変換する装置に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an optical reading device, and more particularly, to a device for converting a document such as a calligraphy or drawing into a scanned electrical signal in a facsimile or character reading device.

この種の光学読取装置として、多数の受光素子
(光電変換素子)を直線状に配列して、各素子の
選択、走査駆動は外部からの駆動電圧によつて行
い、選択、走査された各素子の信号は単一又は小
数の信号読出処理回路(例えば積分器、サンプリ
ング回路)に時系列信号として加える方式のもの
が知られている。
As this type of optical reading device, a large number of light receiving elements (photoelectric conversion elements) are arranged in a straight line, and each element is selected and scanned by an external driving voltage. A method is known in which the signal is added as a time-series signal to a single or small number of signal readout processing circuits (for example, an integrator or a sampling circuit).

これらの方式を実現する装置において、各受光
素子から信号読出回路への線路は多層配線で、か
つ密度高く配線するため、寄生容量が存在し、そ
のためその寄容量に蓄積された電荷が受光素子か
ら読出される信号電荷に影響を与え、正確な走査
出力信号が得られないという問題がある。これに
対し、本発明者らは後で第2図によつて説明する
上記寄生容量の影響を除去する発明をした(特願
昭55―129258号「受光素子」馬路等)。上記発明
は有効であるが、各受光素子に対して発生する寄
生容量が異なる場合、寄生容量の不揃が原因とな
つて走査出力信号に雑音となつて表われることが
分つた。
In devices that implement these methods, the lines from each light-receiving element to the signal readout circuit are multilayered and densely wired, so there is parasitic capacitance, and as a result, the charge accumulated in the parasitic capacitance is transferred from the light-receiving element to the signal readout circuit. There is a problem in that it affects the signal charges read out, making it impossible to obtain accurate scanning output signals. In response to this problem, the present inventors have devised an invention to eliminate the influence of the parasitic capacitance, which will be explained later with reference to FIG. 2 (Japanese Patent Application No. 129258/1983, "Light-receiving element" Umaji et al.). Although the above invention is effective, it has been found that when the parasitic capacitances generated in each light-receiving element are different, the unevenness of the parasitic capacitances becomes a cause and appears as noise in the scanning output signal.

したがつて、本発明の目的は多素の受光素子に
対して存在する寄生容量に不揃いが存在しても、
上記受光素子から読出された電気信号に上記寄生
容量の影響が生じない光学読取装置を実現するこ
とである。
Therefore, an object of the present invention is to solve the problem even if there is unevenness in the parasitic capacitances that exist for multiple light-receiving elements.
It is an object of the present invention to realize an optical reading device in which the electric signal read out from the light receiving element is not affected by the parasitic capacitance.

本発明は上記目的を達成するため、光量に対応
する電荷を保持する複数個の受光素子と、上記受
光素子の選択及び動作状態を切換える駆動回路
と、上記駆動回路によつて選択された受光素子か
ら上記光量に対応する電気信号を読み出す信号読
出回路とからなる光学読取装置であつて、上記信
号読出回路は積分手段を有し、上記電気信号を積
分して電荷量として読出し、かつ上記駆動回路お
よび信号読出回路の少なくとも1部に上記信号読
出回路で光量に対応する電気信号を読出す直前
に、上記選択された受光素子に寄生する寄生容量
に蓄積された電荷を放電する手段を具備して構成
されたことを特徴とする。
In order to achieve the above object, the present invention includes a plurality of light receiving elements that hold charges corresponding to the amount of light, a drive circuit that selects and switches the operating state of the light receiving elements, and a light receiving element selected by the drive circuit. An optical reading device comprising a signal readout circuit for reading out an electric signal corresponding to the amount of light from the drive circuit, the signal readout circuit having an integrating means, integrating the electric signal and reading it out as an amount of charge, and reading out an electric signal corresponding to the amount of light from the drive circuit. and at least a portion of the signal readout circuit is provided with means for discharging the charge accumulated in the parasitic capacitance of the selected light receiving element immediately before the signal readout circuit reads out the electrical signal corresponding to the amount of light. It is characterized by being configured.

本発明によれば、各光学素子毎に、読出しモー
ドの直前に寄生容量に蓄積された電荷が放電され
るため寄生容量の値がばらついても問題とはなら
ない。
According to the present invention, since the charge accumulated in the parasitic capacitance of each optical element is discharged immediately before the read mode, even if the value of the parasitic capacitance varies, there is no problem.

本発明における受光素子とは以下に説明する分
離ダイオードとホトダイオードを組合せたものの
他、ホトダイオードと容量、あるいは分離ダイオ
ードと光電導膜を組合せたものでも良い。
The light receiving element in the present invention may be a combination of a separation diode and a photodiode as described below, or a combination of a photodiode and a capacitor, or a separation diode and a photoconductive film.

以下、本発明を図面を用いて詳細に説明する。 Hereinafter, the present invention will be explained in detail using the drawings.

まず、発明の理解を容易にするため、光学読取
装置の一般的構成ならびに、先に発明した光学読
取装置について説明する。
First, in order to facilitate understanding of the invention, the general configuration of an optical reading device and the previously invented optical reading device will be explained.

第1図は本発明が適用される光学読取装置の多
数の受光素子が配置されるラインセンサ部分の斜
視図を示すものである。同図において、1は密着
読取りライセンサ、2は受光素子、3はレンズア
レイ、4はLED等による光源、5は原稿、6は
原稿走行方向(副走査方向)、7は主走査方向で
ある。
FIG. 1 shows a perspective view of a line sensor portion of an optical reading device to which the present invention is applied, in which a large number of light receiving elements are arranged. In the figure, 1 is a contact reading license sensor, 2 is a light receiving element, 3 is a lens array, 4 is a light source such as an LED, 5 is a document, 6 is a document traveling direction (sub-scanning direction), and 7 is a main scanning direction.

第2図は上記本発明者等が先に発明した光学読
取装置の回路図で、第3図は第2図の回路の動作
説明のためのタイムチヤートである。同図中、2
は複数の受光素子部であり、各受光素子は分離ダ
イオード11とホトダイオード13が直列に接続
されている。a1およびa2は上記受光素子を選
択し、各素子を空読み、電荷蓄積、読出し等のモ
ードに切換るための受光素子駆動回路で、各受光
素子の選択、走査する回路を簡単にするため、a
1は上記複数の受光素子を複数の群に分け、各群
のダイオード11に共通に接続される線(行配線
と呼ぶ。)を、アースとバイアス電源10に切換
るためのスイツチ群9と、上記スイツチ群を駆動
する行走査パルスを発生する回路8(以下行走査
回路と呼ぶ)からなり、a2は上記各ブロツクの
同じ位置のホトダイオード13同志を接続した線
(列配線と呼ぶ)を電源17と信号読出回路の入
力とを切換えるスイツチ群15と、上記スイツチ
群15を駆動する信号を発生する回路(以下列走
査回路と呼ぶ)とからなる。
FIG. 2 is a circuit diagram of an optical reading device previously invented by the inventors of the present invention, and FIG. 3 is a time chart for explaining the operation of the circuit shown in FIG. In the same figure, 2
denotes a plurality of light-receiving element sections, and each light-receiving element has a separation diode 11 and a photodiode 13 connected in series. a1 and a2 are light-receiving element drive circuits for selecting the above-mentioned light-receiving elements and switching each element to modes such as idle reading, charge accumulation, readout, etc. In order to simplify the circuit for selecting and scanning each light-receiving element, a
1 is a switch group 9 for dividing the plurality of light-receiving elements into a plurality of groups and switching a line commonly connected to the diodes 11 of each group (referred to as a row wiring) to ground and bias power supply 10; It consists of a circuit 8 (hereinafter referred to as a row scanning circuit) that generates a row scanning pulse for driving the above-mentioned switch group, and a2 is a line connecting the photodiodes 13 at the same position of each block (referred to as a column wiring) to a power source 17. It consists of a switch group 15 for switching between the input signal and the input of the signal readout circuit, and a circuit (hereinafter referred to as a column scanning circuit) that generates a signal for driving the switch group 15.

信号読出回路bはバイアス電荷キヤンセル用リ
セツトスイツチ19、バイアス電荷キヤンセル用
容量20、バイアス電荷キヤンセル用電圧源2
1、信号電荷積分用演算増幅器22および容量2
3、リセツトスイツチ24、サンプルホールド回
路を構成するスイツチ25、容量26およびバツ
フアアンプ27よりなる。なお、32は配線抵抗
である。
The signal readout circuit b includes a bias charge cancel reset switch 19, a bias charge cancel capacitor 20, and a bias charge cancel voltage source 2.
1. Operational amplifier 22 for signal charge integration and capacitor 2
3, a reset switch 24, a switch 25 constituting a sample and hold circuit, a capacitor 26, and a buffer amplifier 27. Note that 32 is a wiring resistance.

この光学読取装置は上記各スイツチ9,15,
19,24の動作によつて空読み、信号電荷蓄積
および読出しのモードを切換えて行なう。
This optical reading device has the above-mentioned switches 9, 15,
By the operations 19 and 24, the idle reading, signal charge accumulation, and readout modes are switched.

次に読出し時の動作について第3図のタイムチ
ヤートを用いて説明する。
Next, the read operation will be explained using the time chart of FIG. 3.

まず時間t1〜t2の間、リセツト信号RSTによつ
てスイツチ19を閉じて信号線の電位V29を電圧
源21の電圧−VBにセツトしておく。同時にス
イツチ24を閉じて積分器容量をリセツト(放
電)してお。時間t2〜t4では列スイツチ15(こ
こではXo1)を信号線側に接続し、同時に先ほ
ど閉じていたりセツトスイツチ19,24を開
く。これにより分離用ダイオード11がターンオ
ンして容量13およびダイオード11に蓄積され
ていた信号電荷が積分器容量23に伝わるととも
に、列配線寄生容量14に蓄積されていた正電荷
が、容量20および容量18に蓄積されていた負
電荷とキヤンセルしあう。これにより積分器出力
端にはV30のようにほぼ信号電荷のみが積分され
て現われてくる。これをスイツチ25(信号S/
H)によりサンプリングし、増幅器27および容
量26によりホールドして出力V31を得る。サン
プリング期間は積分値が安定した時間t3〜t4で行
なう。
First, during time t1 to t2 , the switch 19 is closed by the reset signal RST, and the potential V29 of the signal line is set to the voltage of the voltage source 21 -VB . At the same time, close switch 24 to reset (discharge) the integrator capacity. From time t2 to t4 , the column switch 15 (X o -1 in this case) is connected to the signal line side, and at the same time the previously closed set switches 19 and 24 are opened. As a result, the separation diode 11 is turned on, and the signal charge accumulated in the capacitor 13 and the diode 11 is transmitted to the integrator capacitor 23, and the positive charge accumulated in the column line parasitic capacitance 14 is transferred to the capacitor 20 and the capacitor 18. cancels the negative charge accumulated in the As a result, almost only the signal charge, such as V 30 , is integrated and appears at the integrator output terminal. Switch this to switch 25 (signal S/
H) and held by the amplifier 27 and capacitor 26 to obtain the output V31 . The sampling period is performed from time t 3 to t 4 when the integral value is stable.

上記回路において、寄生容量による電荷の影響
は次のようにして除かれる。
In the above circuit, the influence of charge due to parasitic capacitance is removed as follows.

読出しを行なつていない列配線には逆バイアス
電圧VB(図中17)を印加する。この電圧は列配
線寄生容量CLi(図中容量14の合計)に充電さ
れ、このバイアス電荷QBi QBi=CLi・VB ……(1) は列スイツチXiを信号線側に切換えると信号線を
通つて積分器に積分される。これに対し、受光素
子13で得られる信号電荷QSは QS=Iph×τs ……(2) である。ここでIphは1画素の光電流源、τsは蓄積
時間である。Iphは3pA/xの値であり、素子
の飽和照度は約100x、τsは5mSである。これ
により電荷QSの値は約1.5pCとなる。これに対
し、容量CLは約100PF,VBは5Vであるのでバイ
アス電荷QBは500pFになる。このため、積分器2
2がQBiで飽和してしまい、信号QSを読めなくな
る。また、信号読取りを行なうためには分離ダイ
オードをターン・オンさせる必要があるが、列配
線の電位がこの寄生容量CLiによつてVBに上がつ
ていると、ターンオンさせるにはより高い電圧を
ダイオードのアノード(行配線)に印加する必要
がある。そこで上記第2図の読取装置では、容量
CL1およびCL2(図中18および20)をあらかじ
め逆バイアス電圧VBとは逆符号の電圧−VB′に充
電しておき、列スイツチが信号線に切換えられた
と同時にバイアス電荷QBiをキヤンセルするもの
である。これによる残留電荷QRは QR=QBi−(CL1+CL2)VB′ =CLi・VB−(CL1+CL2)VB′ ……(3) である。容量値CL2および電圧VB′を適切に選ぶ
ことにより、残留電荷QRを減らすことができ、
積分器が飽和することなく信号電荷QSを読取れ
る。また、行配線に高い電圧を印加することなく
分離ダイオードをターン・オン出来る。
A reverse bias voltage V B (17 in the figure) is applied to column wirings that are not being read. This voltage charges the column wiring parasitic capacitance C Li (total of capacitors 14 in the figure), and this bias charge Q Bi Q Bi = C Li・V B ...(1) switches the column switch X i to the signal line side. and is integrated by the integrator through the signal line. On the other hand, the signal charge Q S obtained by the light receiving element 13 is Q S =I ph ×τ s (2). Here, I ph is a photocurrent source for one pixel, and τ s is an accumulation time. I ph has a value of 3 pA/x, the saturation illuminance of the element is approximately 100x, and τ s is 5 mS. As a result, the value of the charge Q S becomes approximately 1.5 pC. On the other hand, since the capacitance C L is approximately 100PF and V B is 5V, the bias charge Q B is 500pF. Therefore, integrator 2
2 becomes saturated at Q Bi , making it impossible to read the signal Q S. Also, in order to read the signal, it is necessary to turn on the isolation diode, but if the potential of the column wiring is raised to V B by this parasitic capacitance C Li , a higher voltage is needed to turn it on. must be applied to the anode (row wiring) of the diode. Therefore, in the reading device shown in Figure 2 above, the capacity
C L1 and C L2 (18 and 20 in the figure) are charged in advance to a voltage -V B ' with the opposite sign to the reverse bias voltage V B , and the bias charge Q Bi is charged at the same time as the column switch is switched to the signal line. It is something to cancel. The residual charge Q R resulting from this is Q R = Q Bi − (C L1 + C L2 ) V B ′ = C Li ·V B − (C L1 + C L2 ) V B ′ (3). By appropriately selecting the capacitance value C L2 and voltage V B ′, the residual charge Q R can be reduced.
The signal charge Q S can be read without the integrator becoming saturated. Also, the isolation diode can be turned on without applying a high voltage to the row wiring.

ところで、上記バイアス電荷QBiは列配線寄生
容量CLi(i=1〜n)に比例する。この値は列ご
とにばらつくため、残留電荷QRも列ごとにばら
つき、出力信号にはこれが現われる。信号電荷
QSに比較して電荷QBiの値が大きいだけに、これ
による信号のばらつきは光学読取装置出力の信号
対雑音(S/N)比を大きく悪化させる。
By the way, the bias charge Q Bi is proportional to the column wiring parasitic capacitance C Li (i=1 to n). Since this value varies from column to column, the residual charge Q R also varies from column to column, and this appears in the output signal. signal charge
Since the value of the charge Q Bi is large compared to Q S , the signal variation caused by this greatly deteriorates the signal-to-noise (S/N) ratio of the output of the optical reading device.

第4図は本発明による光学読取装置の一実施例
の回路図である。第2図の回路との相違点は、画
素読出周期に同期して分離ダイオードのアノード
を接地するためのスイツチ34が加わり、前記バ
イアス電荷キマンセル用回路、19,20,21
の変わりに積分器入力端をリセツト期間中接地す
るためのスイツチ33を設けた点にある。
FIG. 4 is a circuit diagram of an embodiment of an optical reading device according to the present invention. The difference from the circuit of FIG. 2 is that a switch 34 is added to ground the anode of the separation diode in synchronization with the pixel readout cycle, and the bias charge chiman cell circuit 19, 20, 21
Instead, a switch 33 is provided for grounding the integrator input end during the reset period.

以下、第5図のタイミングチヤートと合わせて
第4図の実施例の動作を説明する。なお、この種
の光学読取装置はライン状に配列された多数の受
光素子のホトダイオードに順次一定の電荷を加え
る空読みと、上記空読み後一定時間τs上記空読で
加えられた電荷を入力光信号に応じて放電する電
荷蓄積と、上記電荷蓄積後、上記放電した電荷を
読み出す信号読出しの制御が行なわれるが、本発
明は信号読出し時における寄生容量の影響を除く
部分に係るものであるため、第5図のタイムチヤ
ートは信号読出し時の動作に係る部分のみを示し
ている。すなわち、多数の受光素子のうちYj1
のブロツクの第Xo1,Xo番目の素子およびYj
ブロツクの第X1,X2,X3,X4が順次信号読出し
される部分の動作を示している。
The operation of the embodiment shown in FIG. 4 will be described below in conjunction with the timing chart shown in FIG. Note that this type of optical reading device performs a blank reading in which a constant charge is sequentially applied to the photodiodes of a large number of light receiving elements arranged in a line, and also inputs the charge added in the blank reading for a certain period of time τ s after the blank reading. Charge accumulation that discharges in response to an optical signal and signal readout that reads out the discharged charge after the charge accumulation is performed, and the present invention relates to the part that eliminates the influence of parasitic capacitance during signal readout. Therefore, the time chart in FIG. 5 shows only the part related to the operation at the time of signal reading. In other words, among a large number of light receiving elements, Y j - 1
The operation of the portion in which signals are sequentially read from the X o - 1 and X o -th elements of the block Y and the X 1 , X 2 , X 3 , and X 4 of the Y j block is shown.

まず、YjブロツクのXo1の受光素子の信号読
出の動さについて述べる。行走査回路a1の行走
査パルスYj1が高レベルの状態で、列走査回路
a2の例走査パルスXo1が高レベルとなること
によつて信号読出モード(時間t1〜t3)となる。
このモードのうち、時間t1〜t2では、受光素子
Xo1は信号読出回路側に接続されるが、スイツ
チ34は接地側に閉じられ、スイツチ33および
24は閉じられる。(第5図で信号YCLRは上記ス
イツチ34の駆動信号を示し、高レベルで接地
側、低レベルで電源10側に切換られる。又
RSTはスイツチ24,33の駆動信号を示し高
レベルでスイツチを閉じ、低レベルで開く。)し
たがつて受光素子の分離ダイオードのカソードに
加えられる電圧Y′j1は0となり分離ダイオード
は遮断された状態になる。したがつてXo1に寄
生する寄生容量に蓄積されたバイアス電荷QBi
全てアースに流れる。上記電荷QBiを全て放電し
た(第5図中QBで示す)後、時間t2〜t3で、スイ
ツチ34を電源10側に切換え、スイツチ24お
よび33を開くと、分離ダイオードに電圧VT(電
源10の電圧)が加わり、分離ダイオードが順方
向がバイアスされ、QS +が積分器のキヤパシタ2
3に蓄積される。この電荷は QS +=Iph・τs+Ca・Cd・VT(Ca+Cd)……(4) となる。
First, we will discuss the signal readout operation of the X o -1 light receiving element of the Y j block. When the row scanning pulse Y j - 1 of the row scanning circuit a1 is at a high level, the example scanning pulse X o - 1 of the column scanning circuit a2 becomes a high level, so that the signal readout mode (time t 1 to t 3 ).
In this mode, at time t1 to t2 , the light receiving element
X o -1 is connected to the signal readout circuit, but switch 34 is closed to the ground side, and switches 33 and 24 are closed. (In FIG. 5, the signal Y CLR indicates the drive signal for the switch 34, and is switched to the ground side at high level and to the power supply 10 side at low level.
RST indicates a drive signal for the switches 24 and 33, and a high level closes the switch, and a low level opens the switch. ) Therefore, the voltage Y' j - 1 applied to the cathode of the separation diode of the light-receiving element becomes 0, and the separation diode is cut off. Therefore, the bias charge Q Bi accumulated in the parasitic capacitance of X o1 all flows to the ground. After all of the charge Q Bi has been discharged (indicated by Q B in FIG. 5), switch 34 is switched to the power supply 10 side at time t 2 to t 3 and switches 24 and 33 are opened. T (voltage of power supply 10) is applied, the isolation diode is forward biased, and Q S + is applied to the capacitor 2 of the integrator.
It is accumulated in 3. This charge is Q S + =I ph・τ s +C a・C d・V T (C a +C d )...(4).

ここでCa,Cdはそれぞれホトダイオード13
および分離用ダイオード11の容量である。(4)式
第1項が前記(2)式に対応する信号成分、第2項は
行配線印加電圧に対応するオフセツト成分であ
る。時点t3にて行配線の電圧を再び接地すると、
積分器には逆符号の電荷 QS -=−Ca・Cd・V- T/(Ca+Cd) ……(5) が積分され、先ほどの積分値との合計QS QS=QS ++QS -=Iph・τs ……(6) が出力に現われる。積分器コンデンサ23の値を
CFとした場合、出力V30には V30=Iph・τs/CF ……(7) の電圧が現われる。これを時点t3でサンプルホー
ルドして出力V31を得る。
Here, C a and C d are each photodiode 13
and the capacitance of the isolation diode 11. The first term in equation (4) is a signal component corresponding to equation (2), and the second term is an offset component corresponding to the voltage applied to the row wiring. If we ground the voltage on the row wire again at time t 3 , we get
The integrator integrates the charge with the opposite sign Q S - = -C a・C d・V - T / (C a + C d ) ...(5), and the sum with the previous integrated value is Q S Q S = Q S + +Q S - = I ph・τ s ...(6) appears in the output. The value of integrator capacitor 23 is
In the case of C F , the following voltage appears at the output V 30 : V 30 = I ph ·τ s /C F (7). This is sampled and held at time t3 to obtain an output V31 .

以上はYj1ブロツクのXo1の受光素子の動
作について述べたが、時点t4で、列走査パルスXo
が高レベルとなり、Yj1ブロツクのXoの受光素
子について前述の時間t1〜t4の動作が行なわれ
る。更にYj1ブロツクのXoの受光素子の信号読
出動作が終了すると、行走査パルスYjのみが高
レベルとなり、YjブロツクのX1について、前述
の信号読出動作が行なわれる。以下同様にして、
順次走査が行なわれる。
The above has described the operation of the X o - 1 light receiving element of the Y j - 1 block. At time t 4 , the column scanning pulse X o
becomes a high level, and the above-described operation from time t 1 to t 4 is performed on the X o light receiving element of the Y j -1 block. Further, when the signal reading operation of the X o light receiving element of the Y j -1 block is completed, only the row scanning pulse Y j becomes a high level, and the aforementioned signal reading operation is performed for the X 1 of the Y j block. Similarly below,
Sequential scanning is performed.

以上のように本発明による光学読取装置では、
信号電荷QSをこわすことなく読出の直前の時間t1
〜t2であらかじめバイアス電荷QBiを完全に放出
し、時間t2〜t4で信号成分のみを読出す。これに
より列配線寄生容量CLiのばらつきに起因する出
力信号のばらつきは見られない。さらには、第5
図のようにt3の時点でサンプルホールドを行なえ
ばCa,Cdのばらつきによる信号オフセツト分の
ばらつきも無くなり、(7)のように信号分のみが読
取れる。
As described above, in the optical reading device according to the present invention,
Time t 1 immediately before readout without destroying the signal charge Q S
The bias charge Q Bi is completely discharged in advance from ~ t2 , and only the signal component is read out from time t2 to t4 . As a result, variations in the output signal due to variations in the column wiring parasitic capacitance C Li are not observed. Furthermore, the fifth
If sample and hold is performed at time t3 as shown in the figure, the variation in signal offset due to variation in C a and C d will be eliminated, and only the signal component can be read as shown in (7).

なお積分器には図のように演算増幅器を用いた
が、特に高速、低雑音を要求される装置において
は、この部分を第6図のように構成する方が望ま
しい。ここで35はカツプリング容量、36は低
雑音接合形電界効果トランジスタ、37はそのド
レインに接続された負荷抵抗、38は高増幅率G
の増幅器、39は帰還抵抗RF、40はカツプリ
ング容量、41はトランジスタのバイアス点をき
めるための抵抗で図のようにそれぞれのトランジ
スタに対し対称に配置されている。42はACバ
イパス用容量、43はpnpトランジスタ45のエ
ミツターに接続された抵抗44と同じ値を持つ。
46は45とコンプリメンタリーなnpnトランジ
スタ、47は積分用の容器、48はそのリセツト
(放電)用スイツチ、49,50はMOS型電界効
果トランジスタで高入力インピーダンスのバツフ
ア(ソース・フオロワー)を形成する。51,5
2はそれぞれ正負の電源である。
Although an operational amplifier is used as the integrator as shown in the figure, it is preferable to configure this part as shown in FIG. 6, especially in an apparatus that requires high speed and low noise. Here, 35 is a coupling capacitor, 36 is a low-noise junction field effect transistor, 37 is a load resistor connected to its drain, and 38 is a high amplification factor G.
39 is a feedback resistor R F , 40 is a coupling capacitor, and 41 is a resistor for determining the bias point of the transistors, which are arranged symmetrically with respect to each transistor as shown in the figure. 42 is an AC bypass capacitor, and 43 has the same value as the resistor 44 connected to the emitter of the PNP transistor 45.
46 is an npn transistor complementary to 45, 47 is an integration container, 48 is its reset (discharge) switch, and 49 and 50 are MOS type field effect transistors forming a buffer (source follower) with high input impedance. . 51,5
2 are positive and negative power supplies, respectively.

以下第6図の回路動作の簡単な説明を行なう。
今、一画素の読取時間をτVとすると、信号電荷
QSは等価的な(平均的な)電流 IS=QS/τV ……(8) として読み取られる。これが増幅器38のゲイン
Gが十分高いとするとその出力端で V53=−RF・IS=RF・QS/τV ……(9) として読み取られる。次にこの電圧にしたがつて
トランジスタ45,46のバランスがくずれ、ト
ランジスタ46により以下の電流が容量CFに充
電される。
The operation of the circuit shown in FIG. 6 will be briefly explained below.
Now, if the reading time of one pixel is τ V , then the signal charge is
Q S is read as an equivalent (average) current I S =Q SV (8). If the gain G of the amplifier 38 is sufficiently high, this can be read at its output terminal as V 53 = -RF ·I S = RF ·Q SV (9). Next, in accordance with this voltage, the balance between the transistors 45 and 46 is lost, and the following current is charged to the capacitor C F by the transistor 46.

I=V53/R=RF・QS/τV/R ……(10) これによりV54は以下の値だけ増加する。 I=V 53 /R= RF ·Q SV /R (10) As a result, V 54 increases by the following value.

V54=I・τV/CF =RF・QS/R・CF ……(11) この電圧を1:1のバツフア(49,50で構
成されたもの)を通してS/H回路に伝える。低
雑音接合形電界効果トランジスタ36を入力初段
に用いるため低雑音であり、また積分器に高速の
バイボーラ・トランジスタ45,46を用いるた
め高速である。さらにトランジスタ45,46に
対し回路を対称形にし、コンプリメンタリは素子
を用いることにより温度変化に対する安定性も高
い。
V 54 =I・τ V /C F =R F・Q S /R・C F ...(11) This voltage is passed through a 1:1 buffer (consisting of 49 and 50) to the S/H circuit. tell. Since the low-noise junction field effect transistor 36 is used at the first input stage, the noise is low, and the high-speed bipolar transistors 45 and 46 are used as the integrators, resulting in high speed. Furthermore, by making the circuit symmetrical with respect to the transistors 45 and 46 and using complementary elements, stability against temperature changes is also high.

以上述べたように本願発明によれば、多数の受
光素子に寄生する寄生容量に不揃いが存在して
も、受光素子から読出された電気信号に寄生容量
の影響が生じないという効果を奏することができ
る。
As described above, according to the present invention, even if the parasitic capacitances parasitic to a large number of light receiving elements are uneven, it is possible to achieve the effect that the electrical signals read from the light receiving elements are not affected by the parasitic capacitance. can.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は密着読取りライセンサの斜視図、第2
図、第3図はそれぞれ本発明者が先に発明した光
学読取装置の回路図およびタイミング・チヤー
ト、第4図、第5図はそれぞれ本発明よる光学読
取装置の一実施例の回路図およびタイミング・チ
ヤート、第6図は本発明に使用される積分器回路
の一実施例の回路図である。 11……分離用ダイオード、12……光導電膜
の光電流、13……光導電膜の容量、14……列
配線の寄生容量、17……分離用ダイオード逆バ
イアス用電源、21……バイアス電荷キヤンセル
用電源、33……バイアス電荷はき出し用スイツ
チ、34……行配線接地用スイツチ。
Figure 1 is a perspective view of the close reading licensor;
Figure 3 is a circuit diagram and timing chart of an optical reading device previously invented by the present inventor, and Figures 4 and 5 are a circuit diagram and timing chart of an embodiment of an optical reading device according to the present invention, respectively.・Chart, FIG. 6 is a circuit diagram of one embodiment of an integrator circuit used in the present invention. 11... Separation diode, 12... Photocurrent of photoconductive film, 13... Capacity of photoconductive film, 14... Parasitic capacitance of column wiring, 17... Separation diode reverse bias power supply, 21... Bias Power supply for charge canceling, 33... switch for discharging bias charge, 34... switch for grounding row wiring.

Claims (1)

【特許請求の範囲】 1 光量に対応する電荷を保持する複数個の受光
素子と、上記受光素子の選択及び動作状態を切換
える駆動回路と、上記駆動回路によつて選択され
た受光素子から上記光量に対応する電気信号を読
み出す信号読出回路とからなる光学読取装置であ
つて、上記信号読出回路は積分手段を有し、上記
電気信号を積分して電荷量として読出し、かつ上
記駆動回路および信号読出回路の少なくとも1部
に上記信号読出回路で光量に対応する電気信号を
読出す直前に、上記選択された受光素子に寄生す
る寄生容量に蓄積された電荷を放電する手段を具
備して構成されたことを特徴とする光学読取装
置。 2 第1項記載の装置において、受光素子は直列
に接続されたホトダイオードと容量素子、光導電
膜と分離用ダイオード、又はホトダイオードと、
これと整流方向が逆の分離ダイオードの1つで構
成された光学読取装置。 3 第1項記載の装置において、上記複数個の受
光素子は複数個の群に分割され、上記駆動回路は
上記各々の群の全素子に対応する行配線とアース
又は第1のバイアス電源を切換える第1のスイツ
チ群と、上記第1のスイツチ群を駆動する第1の
スイツチ駆動回路とからなる行走査回路と、上記
各群中で相対的に同位置にある素子を結合した列
配線と、第2バイアス電源、又は上記信号読出回
路の入力とを切換える第2のスイツチ群と、上記
第2のスイツチ群を駆動する第2のスイツチ駆動
回路とからなる列走査回路とからなり、上記放電
する手段は選択された受光素子に対応する行配線
および列配線とアースに接続する手段とからなる
ことを特徴とする光学読取装置。 4 第3項記載の装置において、信号読出回路
は、上記第2のスイツチ群を介して、列配線が反
転入力端子に接続され、非反転入力端子がアース
に接続され、反入力端子と出力端子間にリセツト
スイツチ付容量が接続された演算増幅器と、上記
演算増幅器の出力をサンプルホールドするサンプ
ルホルード回路とで構成されたことを特徴とする
光学読取装置。
[Scope of Claims] 1. A plurality of light-receiving elements that hold charges corresponding to the amount of light, a drive circuit that selects and switches the operating state of the light-receiving elements, and receives the light amount from the light-receiving element selected by the drive circuit. An optical reading device comprising a signal readout circuit for reading out an electric signal corresponding to the drive circuit and the signal readout circuit, the signal readout circuit having an integrating means to integrate the electric signal and read it out as an amount of charge, and for reading out an electric signal corresponding to the drive circuit and the signal readout circuit. At least a portion of the circuit is configured to include means for discharging the charge accumulated in the parasitic capacitance of the selected light receiving element immediately before the signal readout circuit reads out the electrical signal corresponding to the amount of light. An optical reading device characterized by: 2 In the device described in item 1, the light receiving element includes a photodiode and a capacitive element, a photoconductive film and a separation diode, or a photodiode connected in series;
An optical reader consisting of one of the isolation diodes with the opposite rectifying direction. 3. In the device according to item 1, the plurality of light receiving elements are divided into a plurality of groups, and the drive circuit switches between the row wiring and the ground or the first bias power supply corresponding to all the elements in each group. a row scanning circuit consisting of a first switch group and a first switch drive circuit that drives the first switch group; and a column wiring that connects elements at relatively the same position in each group; A column scanning circuit includes a second switch group for switching between a second bias power source or the input of the signal readout circuit, and a second switch drive circuit for driving the second switch group, and An optical reading device characterized in that the means comprises means for connecting row wiring and column wiring corresponding to a selected light receiving element to ground. 4 In the device described in item 3, the signal readout circuit has the column wiring connected to the inverting input terminal, the non-inverting input terminal connected to ground, and the inverting input terminal and the output terminal connected to each other via the second switch group. 1. An optical reading device comprising an operational amplifier having a capacitor with a reset switch connected therebetween, and a sample-and-hold circuit that samples and holds the output of the operational amplifier.
JP58104134A 1983-06-13 1983-06-13 Optical reader Granted JPS59229966A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58104134A JPS59229966A (en) 1983-06-13 1983-06-13 Optical reader

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58104134A JPS59229966A (en) 1983-06-13 1983-06-13 Optical reader

Publications (2)

Publication Number Publication Date
JPS59229966A JPS59229966A (en) 1984-12-24
JPH0142186B2 true JPH0142186B2 (en) 1989-09-11

Family

ID=14372629

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58104134A Granted JPS59229966A (en) 1983-06-13 1983-06-13 Optical reader

Country Status (1)

Country Link
JP (1) JPS59229966A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6251868A (en) * 1985-08-31 1987-03-06 Kyocera Corp Reading system
JP2571644B2 (en) * 1990-12-26 1997-01-16 ローム株式会社 Image sensor
JP4497619B2 (en) * 2000-02-01 2010-07-07 株式会社日立メディコ X-ray diagnostic imaging equipment
JP2006323261A (en) * 2005-05-20 2006-11-30 Mitsubishi Electric Corp Method for driving display device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59168771A (en) * 1983-03-15 1984-09-22 Mitsubishi Electric Corp Photoelectric converter

Also Published As

Publication number Publication date
JPS59229966A (en) 1984-12-24

Similar Documents

Publication Publication Date Title
EP0275217B1 (en) Photoelectric converting apparatus
KR100660193B1 (en) Self compensating correlated double sampling circuit
US6903771B2 (en) Image pickup apparatus
JP3581031B2 (en) Photodetector
CN103281056B (en) Sense slowdown monitoring circuit and operation method and photoelectric conversion array
JPH05207220A (en) Solid-state image pickup device and its driving system
US5796431A (en) Solid-state image pickup device and driving method thereof
US5146074A (en) Solid state imaging device
US5168153A (en) Integrator and image read device
US4556910A (en) Image sensing device having on-chip fixed-pattern noise reducing circuit
US6657664B2 (en) Solid-state image pickup device
JPH0142186B2 (en)
US7372489B2 (en) Signal processing circuit and solid-state image pickup device
JP3836911B2 (en) Solid-state imaging device
JPH06105068A (en) Image sensor
JP3548244B2 (en) Photoelectric conversion device
JPH0556213A (en) Solid-state image pickup device
JPH1169231A (en) Sensor output read circuit
JP3017036B2 (en) Solid-state imaging device
JP2907268B2 (en) Signal processing device, solid-state imaging device, and imaging method of the device
JPS60139060A (en) Image sensor
JPS623630B2 (en)
JPH04360382A (en) Photoelectric conversion device
JPS61121581A (en) Driving method of solid-state image pick-up device
JPS63177649A (en) Image sensor