JPH0136638B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital musical tone modulation device that temporally modulates a musical tone signal. This is what I did.

Traditionally, musical tones have been modulated using amplitude modulation, phase modulation,
There are many methods, such as delay modulation. One of the most widely used devices is a bucket bridge gate device (BBD) in which the transfer clock frequency of a charge transfer element is increased or decreased by a modulation signal to modulate the delay time. However, since BBD is an analog device, it has the disadvantage of having a lot of residual noise. On the other hand, if a digital shift register is used, the noise is reduced, but since the frequency of the shift clock varies, there is a drawback that compatibility with surrounding systems whose original clock frequency is constant is poor.

The present invention solves these conventional problems by keeping the sampling clock frequency constant.
The present invention provides a digital musical tone modulation device capable of digitally applying delay modulation.

First, the basic principle of the present invention will be explained. FIG. 1 is a block diagram showing the basic configuration of the present invention. In FIG. 1, reference numeral 1 denotes a modulation signal generator, which generates a modulation signal of a frequency lower than the normal audible band in the form of a digital code. Reference numeral 3 denotes a read/write memory having a plurality of addresses, which can sequentially store musical tone signals input from the input terminal 5 at predetermined addresses and read out musical tone signals written at predetermined addresses. Reference numeral 2 denotes an address arithmetic circuit which generates a write address and a read address, as well as interpolation data for interpolation calculations, based on the address generated by itself and the modulation signal. Reference numeral 4 denotes an interpolation calculation circuit which performs an interpolation calculation on the tone signal outputted from the read/write memory 3 based on interpolation data, and outputs the output signal from the output terminal 6.

The basic operation of FIG. 1 will be explained with reference to FIG. 2. A musical tone signal sample as shown in Figure 2 a is output from input terminal 5.
When S _i , S _i+1 , S _i+2 , . . . , S _i+8 , . The written sample is read out after a certain time delay, as shown in FIG. 2b. Let the read samples be S _j , S _j+1 , . . . , S _j+8 , . If the data is output as is, there will only be a certain time delay. In the present invention, when reading musical tone signal samples, the phase of the waveform is varied by changing the address to be read depending on the modulation signal. Simply increasing or decreasing the readout addresses of musical tone signal samples does not result in a smooth waveform arrangement, resulting in the generation of unnecessary frequency components, or in the case of uneven modulation. Therefore, in the present invention, two or more samples of S _j and S _j+1 are read out, and interpolation calculation is performed between them according to the lower part of the modulated signal size, such as the size below the decimal point. S _j shown in Figure 2c
Output ^* .

In this way, when the modulation signal fluctuates, the time at which the sample is output fluctuates, resulting in a fluctuation in delay time, that is, delay modulation. When reading, instead of increasing j by 1 for the set (S _j , S _j+1 ), if j keeps the same value and only the interpolation position changes, the time delay will increase significantly. Conversely, j is 2
Alternatively, if the number increases further, the delay time becomes significantly smaller. As for how to increase j, the magnitude of the modulation signal may be added to the increase in i during writing, and the manner in which i increases may be changed.

Basically, the input waveform is expanded or contracted on the time axis based on the above-mentioned concept.

Since such an operation can be performed in synchronization with a fixed clock cycle, if this is performed in a time division multiplexed manner, it becomes possible to apply different modulations to a plurality of input signals.

FIG. 3 explains the operating principle of time division multiplexing, and a indicates that four types of modulation signals M _a , M _b , M _c , and M _d are sequentially supplied. b is the input signal
It shows that S _a , S _b , S _c , and S _d are supplied in order.
c indicates that S _a *, S _b *, _{S c *} , S _d ^{* are} obtained sequentially by M a , _{M b} , M _c , M d and S _a , S _b ^, S _c ^, S _d There is.

FIG. 4 is a block diagram of a first embodiment of the invention. 1 is a modulation signal generator. 23 is a 7-bit counter that generates the write address i, and is counted up by the timing pulse φ ₀ . The 7-bit write address i is applied to gate 25, and its MSB is applied to inverter 2.
8 and becomes (i-N), which is added to one input of the adder/subtracter 21. A modulation signal is applied to the other input of the adder/subtractor 21. The upper 7 bits of the output of the adder/subtractor 21 are added to the gate 27 as a read address (i-N+α). Furthermore, this upper bit is also added to the "1" adder 24, where "1" is added, and the second read address (j-N+α+1) is sent to the gate 2.
Added to 6. At gates 25, 26, 27,
Timing pulses φ ₁ , φ ₂ and φ ₃ are applied, respectively. In addition, the timing pulses φ ₀ , φ ₁ , φ ₂ , φ ₃
are four-phase timing pulses as shown in FIG. Then, the write address is selected by the timing pulse φ ₁ , the first read address is selected by the timing pulse φ ₂ , and the second read address is selected by the timing pulse φ ₃ , and the address input to the read/write memory 31 is performed.
Applied to AD. The read/write memory 31 stores 128 1-word 16 bits corresponding to 7-bit addresses.
It consists of so-called random access memory made of bit memory. For data input DI,
An input signal is applied from the input terminal 5. When "1" is input to the write terminal WR, DI is written into the 16-bit memory cell specified by the address AD at the falling edge. When WR is "0", one word of the address specified by address AD appears on output DO. 32 is a latch with 1 word and 16 bits, and since the clock is _φ2 , the first
A sample of the read address (i-N+α) is stored. 32 is also a latch of 1 word and 16 bits, but since the clock is _φ3 , the sample of the second read address (i-N+α+1) is stored. These samples are represented by S _i , S _j+1 (j=i-N+α). Samples S _j and S _j+1 are added to a subtracter 41 and the difference (S _j-1 - S _j ) is calculated and added to a multiplier 42 . The lower bits of the adder/subtracter 21 are input to the other input of the multiplier 42. The output of the multiplier 42 and the sample S _j are added to an adder/subtractor 43, and the sum thereof is outputted from the output terminal 6 as S _j ^* .

Therefore, at timing pulse φ ₀ , the counter becomes i, and at timing pulse φ ₁ , the address becomes i.
Write sample S _i to , read S _j from address (i-N+α) with timing pulse φ ₂ , read address (i-N+α+1) with timing pulse φ ₃
Read S _j+1 from and for these S _j and S _j+1
S _j ^* will then be output.

Next, the relationship between addresses and interpolation will be explained. Let T be the period of the timing pulse φ ₀ .
The counter 23 outputs a sample timing iT corresponding to the address i. Modulate the signal as follows (1)
Expressed by the formula.

M(iT)=M _M Tsinω _n iT (1) One input of the adder/subtractor 21 is (i-N)T. Therefore, the sum output T _R (iT) of the adder/subtractor 21
becomes T _R (iT)=(iN)T+M _M Tsinω _n iT (2). ω _n is the angular frequency of modulation in rad/s. M _M represents the depth of modulation. Let N≧M _M.
From the readout center position (i-N)T, maximum M _M
This means reading a position shifted by T. M
does not necessarily have to be an integer. It may also change over time. The entire second term of equation (2) is not necessarily an integer.

Here, divide T _R (iT) by T and take the integer part,
When expressed as A _j , A _j =[(iN)+M _M sinω _n iT]=i-N+α (3). [ ] indicates rounding down to the decimal point.
α is an integer.

On the other hand, the fraction below the decimal point is expressed as {T _R (iT) moduloT}/T (4).

Equation (3) means that if there is no modulation, the address A _j that should originally be read out is (i-N), but is shifted by the second term α due to the modulation signal.

Equation (4) represents the difference between equations (2) and (3). That is,
This corresponds to the deviation from A _j in the A _j+1 direction. In this embodiment, according to this deviation, that is, the amount of interpolated data, the distance between the sample value S _j at A _j and the sample value S j _{+1 at A j +1} is calculated by linear interpolation.

The output of the multiplier 42 is obtained by multiplying the difference by a weight equal to the amount of interpolation data, and is (S _j+1 -S _j )T _R (iT) moduloT/T (5). The output signal from the interpolation calculation is S _j ^* =S _j +(S _j+1 −S _j )T _R (iT) moduloT/T (6).

Equation (3) corresponds to the upper 7 bits of the output of the adder/subtractor 21, and equation (4) corresponds to the lower bits. In FIG. 4, the modulation signal has a maximum of 17 bits, and the lower bits of the sum output of the adder/subtractor 21 are 10 bits. The upper seven bits of the modulated signal correspond to the integer part, the most significant bit of which is the sign bit. The amplitude is represented by 6 bits of an integer. The decimal part is the lower 10 bits. Therefore, the deviation from the original center address corresponds to 6 bits, so it is ±64. The read/write memory 31 has 128 addresses corresponding to 7-bit addresses, and the difference between the write address and the read center address is N=64, so the read address will never overtake the write address. If M _M is kept small, this risk can be completely prevented.

Write address i or read address A _j
increases as i increases, but since it is actually represented by 7 bits, it is modulo 2 ⁷ =128, and the address moves cyclically on the read/write memory 31.

FIG. 5 shows an embodiment in which the embodiment of FIG. 4 is used in time division multiplexing. The difference from FIG. 4 is in the count 28 and multiplexer 14.
The counter 28 is a 3-bit binary counter that counts up the clock φ ₀ , and the carry signal becomes the clock input of the counter 23 . The 3-bit output of the counter 28 is added to the lower 3-bit address AD2 of the read/write memory 31. Eight different input signals are sequentially input to the input terminal 5. Therefore, in the read/write memory 31,
Eight types of input signals are stored in sequence. The 3-bit output of the counter 28 is applied to the multiplexer 14, so that the 8-bit output from the modulation signal generator 1 is
The seed modulated signals are time-division multiplexed and sent to the adder/subtracter 2.
1. In this way, each of the eight time slots TS ₀ , TS ₁ , TS ₂ , ..., TS ₇ performs independent modulation on different input signals, and the results are sent to the output terminal 6 as an output signal. can get. The read/write memory 31 requires eight times the capacity, and each part operates according to eight times the frequency φ ₀ to _{φ 3} .

Note that AD2 may be the upper 3 bits of the read/write memory. In this case, nothing essentially changes except the write and read arrays.

Next, the modulation signal will be explained.

FIG. 6 is a block diagram showing a specific configuration of the modulation signal generator 1 and its peripheral circuits. The outputs of the vibrato oscillator 11, ensemble oscillator 12, and celeste oscillator 13 are sent to an analog multiplexer 1 corresponding to the multiplexer 14 shown in FIG.
4', and applied to the analog-to-digital converter 15, where they are sequentially converted into digital signals and applied to the adder/subtracter 21 in FIG. Counter 16 corresponds to counter 28 in FIG. The vibrato oscillator 11 outputs an analog sine wave of about 6 Hz. Ensemble oscillator 11
is a mixture of sine waves of about 6Hz and about 1Hz,
Three types with phase differences of 120° are generated. The Celeste oscillator 13 generates a four-phase sine wave or triangular wave of approximately 0.5 Hz. In this way, all modulation signals conventionally used for modulation effects in analog systems can be utilized.

FIG. 7 shows a specific configuration of the modulation signal generator 1 and its peripheral circuitry, which digitally generates a plurality of modulation signals. A read-only memory 110 digitally generates a vibrato waveform, and is sequentially read out by CK. 120
130 is a similar read-only memory that creates a three-phase ensemble modulation signal, and 130 is a similar read-only memory that creates other modulation signals. These outputs are multiplexed by a digital multiplexer 14''. Numerals 111, 112, and 113 are modulation envelope circuits that digitally create a ramp-shaped waveform for varying the degree of modulation.
CK1, U/D1, CK2, U/D2, CK3,
Controlled by U/D3. In other words, when U/D becomes "1", the output changes from 0 to 1 digit at a time.
It increases according to CK and maintains that value when it reaches full scale. When U/D becomes "0", it decreases by one digit and reaches zero.

FIG. 8a shows modulation envelope circuits 111 and 12.
1,131, a timing chart of each part is shown in FIG. 8b. 20 in Figure 8a
0 is D flip-flop, 201, 203, 20
7 is an AND gate, 202 is an inverter, 20
4 and 205 are RS flip-flops, 206 is an OR gate, 208 is an up-down counter with a clear terminal CL, and 209 is a gate circuit that detects whether the output of the counter 208 is all 0 or all 1. With this configuration, as is clear from the timing chart in FIG. 8b, an output signal having a ramp-like code can be obtained. Of course, by changing the CK cycle, the rising and falling speeds can be varied.

Returning to Figure 7, each modulation envelope circuit 1
The outputs of 11, 121, and 131 are also multiplexer 1.
7 multiplexed. The outputs of multiplexers 14 and 17 are multiplied by multiplier 18, and the product is supplied to adder/subtracter 21 in FIG.

There are various other methods for the modulation signal generator 1. For example, on October 15, 1981, the inventors
It may also be one that generates a sine wave as proposed in the dated patent application (45).

Note that the calculation speed can be increased by configuring the portion including the interpolation calculation circuit 4, the address calculation circuit 2, etc. in a so-called pipeline configuration in which data is processed while latching it.

Further, in the above description, linear interpolation using two samples has been described, but quadratic function interpolation can also be performed using three samples.

Furthermore, when the sampling period is sufficiently small, that is, when the number of samples is large, sufficiently accurate modulation can be performed by omitting interpolation data, omitting interpolation calculations, and only changing the readout position.

As described above, the present invention includes a modulation signal generator, a read/write memory, and an address control device, and the present invention includes a modulation signal generator, a read/write memory, and an address control device, and the digitized input signal to be modulated is adjusted according to the write signal output from the address control device. The address control device generates a read signal based on the output of the modulation signal generator, reads the input signal from the read/write memory, and outputs an output signal obtained by modulating the input signal on the time axis. Because the clock frequency is fixed, it does not generate residual noise unlike when using analog elements such as BBD, and can be operated in synchronization with a constant clock cycle. system and consistency will also improve. Also, since it can be operated with a constant cycle clock like this,
Time division multiplexing can be easily performed, and one device can easily apply vibrato, ensemble, celeste, and other effects to the same signal or to different signals.

Furthermore, when an interpolation calculation device is added and the input signal is modulated on the time axis by performing interpolation calculation, sufficient modulation can be applied to the musical tone even when the sampling period is large.

[Brief explanation of drawings]

FIG. 1 is a block diagram for explaining the principle of the present invention, FIG. 4 is a block diagram of the first embodiment of the present invention, FIG. 5 is a block diagram of the second embodiment of the present invention, and FIGS. 6 and 7 are diagrams showing the principle of division and multiplexing. 4 and 5 are block diagrams showing the modulation signal generator and its peripheral circuits, and FIGS. 8a and 8b are block diagrams showing the specific configuration of the modulation envelope circuit used in FIG. 7 and their time charts. be. DESCRIPTION OF SYMBOLS 1...Modulation signal generator, 2...Address arithmetic circuit, 3...Read/write memory, 4...Interpolation arithmetic circuit, 5...Input signal, 6...Output terminal.

Claims (1)

[Scope of Claims] 1. An address control device comprising a modulation signal generator, a read/write memory, a write control device, and a read control device, the address control device transmitting a digitized input signal to be modulated. A read control device of the address control device writes the written input signal from the read/write memory after a predetermined time delay after writing the input signal. A digital musical tone characterized in that the readout position is changed according to the modulation signal output from the modulation signal generator to obtain an output signal that modulates the input signal on the time axis. Modulator. 2. A modulation signal generator, a read/write memory, an address control device composed of a write control device and a read control device, and an interpolation calculation device, and the digitized input signal to be modulated is output from the write control device. Writes data into the read/write memory at a predetermined clock frequency in accordance with a write signal, generates a read signal by the read control device based on a modulation signal output from the modulation signal generator, and uses this read signal to write data into the read/write memory. From among the input signals written above, a plurality of sample values based on addresses that are shifted by a predetermined time and further shifted by a time roughly corresponding to the instantaneous amplitude of the modulation signal are read out, and the interpolation calculation device calculates the shift. The difference value between the amplitude value of the modulation signal corresponding to the address and the instantaneous amplitude value of the modulation signal is calculated, and the calculation is performed between the plurality of sample values and the difference value to obtain the difference value corresponding to the difference value. Digital musical tone modulation characterized in that the input signal is frequency modulated or phase modulated on the time axis by determining interpolated values of a plurality of sample values and outputting the interpolated values at the same clock frequency as the writing. Device. 3. In the statement of claim 2, a plurality of types of input signals are time-division multiplexed and input, read/write memories are provided corresponding to the plurality of types of input signals, and an address control device causes the read/write memory to receive the above input signals. A time-division multiplexed output signal is obtained by sequentially writing time-division multiplexed input signals and using the interpolation calculation device in a time-division multiplexing manner for the input signals read from the read/write memory. A digital musical tone modulation device characterized by: 4. A digital musical tone modulation device according to claim 3, characterized in that a plurality of modulation signals are generated by time division multiplexing from a modulation signal generator. 5. A digital musical tone modulation device according to claim 3, characterized in that at least two of the time-division multiplexed input signals are the same signal. 6. In claim 2, the reading/writing memory is constituted by a random access memory having a predetermined address size, and the input signal is cyclically sent to the random access memory by a write control device of the address control device. A readout control device of the write and address control devices reads out positions that are forward and backward in accordance with the modulation signal around a readout center position that is delayed by a predetermined position from the write position of the input signal. Digital musical tone modulation device. 7. In claim 6, the readout control device is provided with an adder/subtractor that adds or subtracts a modulated signal at its readout center position, and is configured to output the upper part of the sum outputted by the adder/subtractor as the readout position. A digital musical tone modulation device characterized by: 8 In the statement of claim 7, the upper part of the sum outputted by the adder/subtractor is set as the readout position, and multiple positions in the read/write memory including adjacent positions are read out, and the multiple readout outputs and the above sum are read out. A digital musical tone modulation device characterized in that the lower part is input to an interpolation calculation device, and an output is obtained by interpolation calculation according to the lower part of the sum. 9. A digital musical tone modulation device as set forth in claim 8, characterized in that the number of readout outputs is three and interpolation is performed using a quadratic function. 10. A digital musical tone modulation device according to claim 8, characterized in that the number of read outputs is two and linear interpolation is performed. 11. A digital musical tone modulation device as set forth in claim 3, characterized in that the time-division multiplexed output signals of the interpolation calculation device are converted into independent analog signals and used as musical tone signals. . 12. A digital musical tone as set forth in claim 3, characterized in that at least two or more of the time-division multiplexed output signals of the interpolation calculation device are added and converted into an analog signal. Modulator.